KR100324015B1 - Method for fabricating contact hole of semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a contact hole of a semiconductor device is provided to guarantee a process margin by using a polycrystalline silicon layer as an etch barrier layer regarding an oxide layer such that the polycrystalline silicon layer has a large etch selectivity regarding the oxide layer. CONSTITUTION: A gate electrode in which the first and second insulation layer patterns used as a mask insulation layer are stacked is formed on a semiconductor substrate(12). The third insulation layer spacer is formed on the sidewalls of the second insulation layer pattern, the first insulation layer pattern and the gate electrode. A source/drain region is formed in the semiconductor substrate at both sides of the third insulation layer spacer. The fourth insulation layer(26) is formed. A polycrystalline silicon layer(24) is formed on the fourth insulation layer. The fifth insulation layer pattern exposing a portion reserved for a contact is formed on the polycrystalline silicon layer. A predetermined thickness of the polycrystalline silicon layer exposed by the fifth insulation layer pattern is eliminated by an isotropic etch method. The sixth insulation layer is formed to fill the side surface from which the polycrystalline silicon layer is removed when the polycrystalline silicon layer is eliminated. The sixth insulation layer and the fourth insulation layer are removed to form a contact hole by an anisotropic dry etch method using plasma.

Description

Method for manufacturing contact hole of semiconductor device

The present invention relates to a method for manufacturing a contact hole of a semiconductor device, and in particular, to form a polysilicon layer having a high etching selectivity with respect to an oxide layer of an etch barrier layer used in an SAC process due to an overlay margin problem in a manufacturing process of a highly integrated device. After the isotropic etching of the polysilicon layer used to remove, and then reflow BPSG or deposit a mesophilic oxide film relates to a technique for preventing the electrical short between the micro-wiring caused by the polycrystalline silicon film.

The recent trend of high integration of semiconductor devices is greatly influenced by the development of fine pattern formation technology. In particular, the photoresist pattern is widely used as a mask for etching or ion implantation in the semiconductor device manufacturing process.

Therefore, miniaturization of the photoresist pattern is essential for high integration of semiconductor devices, and the resolution of the photoresist pattern is proportional to the wavelength and the process variable of the light source of the reduction exposure apparatus, and the numerical aperture (NA, aperture) of the reduction exposure apparatus. Inversely proportional to

Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. About μm is the limit. Therefore, an exposure apparatus using a deep ultra violet (DUV) wavelength, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, as a light source is used to form a fine pattern of 0.5 μm or less. And a contrast enhancement layer (hereinafter referred to as CEL) method for forming a separate thin film on the wafer which can improve image contrast, or S.O.G. Tri-layer resister (hereinafter referred to as TLR) method with an intermediate layer such as on glass (SOG) or a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size and spacing between the main wiring as the device is highly integrated, and the aspect ratio, which is a ratio of the diameter and the depth of the contact hole, increases. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

These contact holes have misalignment tolerance during mask alignment, lens distortion during exposure process, critical dimension variation during mask fabrication and photolithography process, and between masks to maintain spacing. The mask is formed by considering factors such as registration.

In addition, in order to overcome the limitations of the lithography process when forming contact holes, a technique of forming contact holes by a self-aligning method has been developed.

Hereinafter, a method for manufacturing a contact hole of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method for manufacturing a contact hole in a semiconductor device according to the prior art.

First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 101 so that impurities exist in a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region, and then in the semiconductor substrate 101. A device isolation insulating film (not shown) is formed on the portion intended as the device isolation region, and the gate insulating film 103, the conductive layer 105 for the gate electrode, the first insulating film 107, and the remaining semiconductor substrate 101 are formed. After sequentially forming the second insulating layer 109, the second insulating layer 109, the first insulating layer 107, and the conductive layer 105 for the gate electrode are sequentially etched using the gate electrode patterning mask to sequentially form the gate electrode. And first and second insulating films 107 and 109 stacked on top of each other. Here, the first insulating film 107 is formed of an oxide film, the second insulating film 109 is formed using a nitride film or an oxide film, and the patterns of the first and second insulating films 107 and 109 are used as a mask insulating film. do.

Thereafter, a lightly doped impurity layer (not shown) to form a lightly doped drain (LDD) region is formed on the semiconductor substrate 101 at both sides of the gate electrode, and then the conductive layer 105 for the gate electrode is formed. ) And the third insulating layer 111 is formed on the sidewalls of the patterns and the first and second insulating layers 107 and 109 by CVD to form an entire surface and anisotropically etch the third insulating layer 111. The third insulating layer 111 is formed using an oxide film. (See FIG. 1A)

Thereafter, a high concentration impurity region (not shown) is formed in the semiconductor substrate 101 on both sides of the third insulating film 111 spacer, and the fourth insulating film 113 is formed on the entire surface of the structure as a nitride film. In this case, the fourth insulating layer 113 serves as an etch stop layer.

Next, a fifth insulating layer 115 is formed on the fourth insulating layer 113 to be planarized. In this case, the fifth insulating film 115 is formed using an oxide film. (See FIG. 1B)

Subsequently, a bit line contact hole is formed by removing the fifth insulating layer 115 on the portion of the semiconductor substrate 101 which is supposed to be a bit line contact, but also removing the fourth insulating layer 113 to be a bit line contact. The semiconductor substrate 101 of the portion is exposed. (See FIG. 1C)

As described above, in the method of manufacturing a contact hole of a semiconductor device according to the related art, in the case of using a nitride film or a polysilicon layer as an etch barrier during the etching process for forming the contact hole, an etching process and a nitride film having a large etching selectivity of the nitride film relative to the oxide film It is not easy to develop an etching process, and the process of developing the nitride film etching process with respect to the oxide film and the etching process of the nitride film is not easy, so the process lacks reproducibility and reliability due to the lack of the margin of the etching process. Since a large amount of polymer is used to obtain a high selectivity for the oxide, it is difficult to secure process margins during the etching of the oxide film. When the polycrystalline silicon layer is used as the etching prevention film, a high selectivity for the oxide film can be obtained, but the fine wiring It is difficult to apply to device manufacturing process by causing electrical short between have.

The present invention to solve the problems of the prior art, by using a polysilicon layer having a large etching selectivity for the oxide film as an etching prevention film for the oxide film in the SAC process to secure a process margin to perform a reproducible process, fine SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a contact hole in a semiconductor device, which can prevent electrical shorts between wires and improve device characteristics and reliability.

1A to 1C are cross-sectional views illustrating a method for manufacturing a contact hole in a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method for manufacturing a contact hole in a semiconductor device according to a first embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 12, 101: semiconductor substrate 13, 14, 103: gate insulating film

15, 16, 105: conductive layers for gate electrodes 17, 18, 107: first insulating film

19, 20, 109: second insulating film 21, 22, 111: third insulating film

23, 26, 113: fourth insulating film 24, 25: polysilicon layer

27, 115: fifth insulating film 28: photosensitive film pattern

29: sixth insulating film

Contact hole manufacturing method of a semiconductor device according to the present invention for achieving the above object,

Forming a gate electrode on which a first insulating film pattern and a second insulating film pattern, which are used as a mask insulating film, are stacked, on a semiconductor substrate;

Forming a third insulating film spacer on sidewalls of the second insulating film pattern, the first insulating film pattern, and the gate electrode;

Forming a source / drain region on both semiconductor substrates of the third insulating film spacer;

Forming a fourth insulating film on the entire surface of the structure;

Forming a polysilicon layer on the fourth insulating film;

Forming a fifth insulating film pattern exposing a portion intended as a contact on the polysilicon layer;

Removing a predetermined thickness of the polysilicon layer exposed by the fifth insulating film pattern by an isotropic etching method;

Forming a sixth insulating layer on the structure to fill the side surface from which the polysilicon layer is removed during the polysilicon layer removal process;

The sixth and fourth insulating films may be removed by anisotropic dry etching using plasma to form contact holes.

In addition, the contact hole manufacturing method of the semiconductor device according to the present invention for achieving the above object,

Forming a gate electrode on which a mask insulating film pattern is stacked on a semiconductor substrate;

Forming a first insulating film spacer on sidewalls of the mask insulating film pattern and the gate electrode;

Forming a source / drain region on both semiconductor substrates of the first insulating film spacer;

Forming a second insulating film on the entire surface of the structure;

Forming a polysilicon layer on the second insulating film;

Forming a third insulating film over the polysilicon layer, and then flowing and planarizing the third insulating film;

Forming a third insulating film pattern exposing a portion intended to be in contact with the semiconductor substrate;

Removing the polysilicon layer exposed by the third insulating layer pattern by a dry etching method using plasma;

Removing the second insulating film;

And reflowing the third insulating layer pattern to fill side surfaces from which the polysilicon layer and the second insulating layer are removed during the removing of the polysilicon layer and the second insulating layer, thereby securing fine inter-wire insulation. do.

Hereinafter, a method of manufacturing a contact hole in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to a first embodiment of the present invention.

First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that impurities exist in a desired form in the channel portion of the well and the transistor and the lower portion of the device isolation region. After forming a device isolation oxide film (not shown) on the portion intended as the device isolation region and forming the gate oxide film 13 on the entire surface, the first electrode used as the gate electrode conductive layer 15 and the mask insulating film The insulating film 17 and the second insulating film 19 are sequentially formed. In this case, the second insulating film 19 may be formed of an oxide film or a nitride film. In the case of using the nitride film as the second insulating film 19, the oxide film is deposited in advance in a thickness of 10 to 30 nm before the nitride film is deposited, and then the nitride film is deposited. Is deposited to a thickness of 50 to 150 nm, and when the oxide film is used as the second insulating film 19, it is deposited to a thickness of 50 to 150 nm.

Next, a second photoresist layer (not shown) is coated on the second insulating layer 19, and an exposure and development process is performed to form a first photoresist pattern that protects a portion intended as a gate electrode.

Next, a word line pattern is formed by patterning the second insulating layer 19, the first insulating layer 17, and the conductive layer 15 for the gate electrode by an etching process using the first photoresist pattern as a mask for a gate electrode. The first photoresist pattern is removed.

A third insulating layer (not shown) is formed on the entire surface, and a third etching layer spacer 21 is formed on both sidewalls of the word line pattern by performing an entire surface etching process. (See Figure 2A)

Next, a fourth insulating film 23 having a thickness of 5 to 30 nm is deposited on the entire structure, and a polysilicon layer 25, which is an etch stop layer, is deposited to have a thickness of 10 to 100 nm.

Next, a fifth insulating film 27 is formed over the entire structure to planarize it. In this case, the fifth insulating layer 27 is formed using an oxide film. (See Figure 2b)

Thereafter, a second photoresist pattern (not shown) is formed on the fifth insulating layer 27 to expose a portion of the semiconductor substrate 11 to be a bit line contact.

The fifth insulating layer 27 is anisotropic dry etched and removed using the second photoresist pattern as an etching mask. In this case, the polysilicon layer 25 is hardly etched because the etch selectivity with respect to the fifth insulating layer 27 is large. (See FIG. 2C)

Next, the polysilicon layer 25 exposed by the fifth insulating layer 27 is removed. Here, the degree of removal of the polysilicon layer 25 is not removed from the polysilicon layer 25 and the bit line is not removed, the insulating film filled in the empty space during the subsequent process is sufficiently used as a diffusion barrier, parasitic The polysilicon layer 25 is removed to fill the void space so that it does not act as a capacitor. At this time, the size of ⓐ which is a portion where the polysilicon layer 25 is not removed has a range of 20 to 150 nm.

Meanwhile, a method of removing the polysilicon layer 25 is a wet etching method using an NH ₄ OH / H ₂ O ₂ mixed solution and a KOH solution, and an isotropic plasma dry etching using an NF ₃ / O ₂ / Ar mixed gas plasma. Use the method.

Next, a sixth insulating layer 29 is deposited on the entire structure. In this case, the sixth insulating layer 29 uses a medium temperature oxide (MTO) to sufficiently fill the empty space formed by removing the polysilicon layer 25. (See FIG. 2D)

Next, the sixth insulating layer 29 is removed by an anisotropic dry etching method. At this time, the fourth insulating layer 23 deposited before the polysilicon layer 25 is also removed, thereby exposing the semiconductor substrate 11 at a portion intended to be a bit line contact. (See Figure 2E)

Looking at the second embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to a second embodiment of the present invention.

First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 12 so that impurities exist in a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region, and then in the semiconductor substrate 12 After forming a device isolation oxide film (not shown) on the portion intended as the device isolation region and forming a gate oxide film 14 on the entire surface, the first electrode used as the gate electrode conductive layer 16 and the mask insulating film The insulating film 18 is formed sequentially.

Next, a first photoresist layer (not shown) is formed on the first insulating layer 18, and an exposure and development process is performed to form a first photoresist layer pattern that protects a portion intended as a gate electrode.

Next, the first insulating layer 18 is etched using the first photoresist pattern as an etching mask to form a first insulating layer 18 pattern, and the first photoresist pattern is removed.

The gate electrode conductive layer 16 is etched using the first insulating layer 18 as an etch mask to form a gate electrode.

Next, spacers of the second insulating layer 20 are formed on both sidewalls of the gate electrode and the first insulating layer 18.

A third insulating film 22 having a thickness of 5 to 30 nm is deposited on the entire structure, and a polysilicon layer 24, which is an etch stop film, is deposited on the top of the structure, having a thickness of 10 to 100 nm. (See Figure 3A)

Next, a fifth insulating film 26 is formed on the entire surface of the structure and planarized. In this case, the fourth insulating layer 26 is formed using B. P. G. (Brophospho silicate glass, hereinafter referred to as BPSG), and flows to planarize it.

Thereafter, a second photoresist layer pattern 28 is formed on the fourth insulating layer 26 to expose a portion of the semiconductor substrate 12 to be a bit line contact. (See Figure 3b)

In addition, the fourth insulating layer 26 is anisotropically dry-etched and patterned using the second photoresist layer pattern 28 as an etching mask. In this case, the polysilicon layer 24 is hardly etched because the etch selectivity with respect to the fourth insulating layer 26 is large.

Here, the fourth insulating layer 26 is etched using a gas containing hydrogen such as CF ₄ , CH ₃ F or C ₂ H ₂ , H ₂ , CH ₂ F ₂ , C ₂ HF ₅ to form the polysilicon layer. It is possible to obtain a high etching selectivity for (24), by etching using a gas such as C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ to obtain a high etching selectivity for the polysilicon layer 24 To get a wider process window. In addition, in order to stabilize the plasma, inert gases such as Ar, Ne, He, and Xe are mixed to improve the etching uniformity. In addition, the C ₂ H ₂ , H ₂ , CH ₂ F ₂ , C ₂ HF ₅ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ and the inert gas are mixed to etch high with respect to the polysilicon layer Selectivity and etching uniformity can be obtained.

Next, the second photoresist layer pattern 28 is removed, and the polysilicon layer 24 exposed by the fourth insulation layer pattern 26 is isotropically formed using gases such as CF ₄ , NF ₃ , SF _6, and the like. By etching to remove the side at the same time as the bottom, or by mixing the gas O ₂ , He, Ne, Ar, N ₂ gas to improve the etching characteristics.

Next, the third insulating layer 22 is removed by an in-situ method to expose the semiconductor substrate 12 in a portion intended for the bit line contact. In this case, the third insulating layer 22 may be removed by a dry etching method or a wet etching method to reduce plasma damage. (See FIG. 3C, FIG. 3D)

The fourth insulating layer 26 is reflowed and planarized at 800 to 900 ° C., and the empty space formed when the polysilicon layer 24 and the third insulating layer 22 are removed is filled with the fourth insulating layer 26. Prevents contact between fine wirings. (See Figure 3e)

As described above, the method for manufacturing a contact hole of a semiconductor device according to the present invention uses a polysilicon layer having a high etch selectivity as an etch barrier in the SAC process due to an overlay margin problem, and isotropic the polycrystalline silicon layer used as the etch barrier. After etching and removing, the BPSG is reflowed or MTO is deposited to prevent the electrical short between the micro wirings caused by the polysilicon film, thereby improving the characteristics and reliability of the semiconductor device.

Claims (16)

Forming a gate electrode on which a first insulating film pattern and a second insulating film pattern, which are used as a mask insulating film, are stacked, on a semiconductor substrate; Forming a third insulating film spacer on sidewalls of the second insulating film pattern, the first insulating film pattern, and the gate electrode; Forming a source / drain region on both semiconductor substrates of the third insulating film spacer; Forming a fourth insulating film on the entire surface of the structure; Forming a polysilicon layer on the fourth insulating film; Forming a fifth insulating film pattern exposing a portion intended as a contact on the polysilicon layer; Removing a predetermined thickness of the polysilicon layer exposed by the fifth insulating film pattern by an isotropic etching method; Forming a sixth insulating layer on the structure to fill the side surface from which the polysilicon layer is removed during the polysilicon layer removal process; And removing the sixth insulating layer and the fourth insulating layer by an anisotropic dry etching method using plasma to form contact holes. The method of claim 1, The second insulating layer pattern is an oxide film having a thickness of 50 to 150 nm and is used as a mask for a gate electrode. The contact hole of the semiconductor device may ensure a process margin for transient etching during the third insulating layer spacer forming process. Manufacturing method. The method according to claim 1 or 2, And forming a nitride film having a thickness of 50 to 150 nm after depositing an oxide film having a thickness of 5 to 30 nm in advance when the second insulating pattern is formed of a nitride film. The method of claim 1, The fourth insulating film is a contact hole manufacturing method of a semiconductor device, characterized in that to form a thickness of 5 to 30nm using an oxide film. The method of claim 1, The process of removing the polysilicon layer is a contact hole manufacturing method of a semiconductor device, characterized in that the wet etching method using a NH ₄ OH / H ₂ O ₂ mixed solution, KOH solution. The method of claim 1, The removing of the polysilicon layer is performed by an isotropic plasma dry etching method using NF ₃ / O ₂ / Ar, CF ₄ / O ₂ / Ar mixture gas. The method according to claim 1 or 5, The remaining portion of the polysilicon layer removal process is removed without removing the contact hole manufacturing method of the semiconductor device characterized in that it has a range of 20 ~ 150nm. The method of claim 1, The sixth insulating film is a contact hole manufacturing method of a semiconductor device, characterized in that formed using MTO or CVD oxide film. Forming a gate electrode on which a mask insulating film pattern is stacked on a semiconductor substrate; Forming a first insulating film spacer on sidewalls of the mask insulating film pattern and the gate electrode; Forming a source / drain region on both semiconductor substrates of the first insulating film spacer; Forming a second insulating film on the entire surface of the structure; Forming a polysilicon layer on the second insulating film; Forming a third insulating film over the polysilicon layer, and then flowing and planarizing the third insulating film; Forming a third insulating film pattern exposing a portion intended to be in contact with the semiconductor substrate; Removing the polysilicon layer exposed by the third insulating layer pattern by a dry etching method using plasma; Removing the second insulating film; Reflowing the third insulating layer pattern to fill sidewalls from which the polysilicon layer and the second insulating layer are removed during the removal process of the polysilicon layer and the second insulating layer to secure insulation between the micro-wires. Manufacturing method. The method of claim 9, The polysilicon layer may be formed by using a gas including hydrogen, such as CF ₄ , CH ₃ F gas, or C ₂ H ₂ , H ₂ , CH ₂ F ₂ , C ₂ HF ₅ gas. Method for manufacturing a contact hole of a semiconductor device, characterized in that for increasing the etching selectivity. The method of claim 9, In the forming of the third insulating layer pattern, an etching process is performed using gases such as C ₂ F ₆ , C ₃ F ₈ , and C ₄ F ₈ to increase the etching selectivity of the polysilicon layer and to increase the process window. Contact hole manufacturing method of a semiconductor device, characterized in that secured. The method of claim 9, The third insulating layer pattern may be formed by an etching process using a hydrogen-containing gas and a gas in which an inert gas is mixed with C ₂ F ₆ , C ₃ F ₈ , and C ₄ F ₈ gases. Way. The method of claim 9, The polysilicon layer is removed by the isotropic etching method using CF ₄ , NF ₃ , SF ₆ gas contact hole manufacturing method of a semiconductor device. The method of claim 13, The removing of the polysilicon layer is performed by mixing O ₂ , He, Ne, Ar, and N ₂ gas with the gas. The method of claim 9, The method of claim 1, wherein the second insulating layer is removed by a wet or dry etching method. The method of claim 9, And reflowing the third insulating film pattern at 800 to 900 占 폚.