KR20060126110A - Manufacturing method for semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent degradation of device performance due to impurity diffusion by forming a polycrystalline silicon layer with a low doping concentration and, subsequently, a metal plug. A gate dielectric(32) is formed on a semiconductor substrate(30). A gate electrode(34) overlapped with a hard mask layer(36) pattern is formed on the gate dielectric. Insulating spacers(38) are formed on the hard mask layer pattern and a sidewall of the gate electrode. An interlayer dielectric(40) is formed on the whole surface of the structure. The interlayer dielectric on a portion that is expected as a contact on the semiconductor substrate is removed to form a landing plug contact hole. A selective epi growth polycrystalline silicon layer(42) is formed on the semiconductor substrate exposed through the contact hole by undoping or by lE14 to 1E18/cm^3 impurity doping concentration. Impurity ion is implanted into the selective epi growth polycrystalline silicon layer to form an ohmic contact layer(43). A metal plug is formed to be connected to the ohmic contact layer.

Description

Manufacturing method for semiconductor device

1 is a cross-sectional view of a semiconductor device according to the prior art.

2a to 2c is a manufacturing process diagram of a semiconductor device according to the present invention.

         <Explanation of symbols for the main parts of the drawings>

10, 30: semiconductor substrate 12, 32: gate insulating film

14, 34: gate electrode 16, 36: hard mask layer

18, 38: spacer 20, 40: interlayer insulating film

22, 42: Selective epitaxial polysilicon layer 24, 44: Conductive layer

43: ohmic contact layer

The present invention relates to a method for manufacturing a semiconductor device, and in particular, when forming a landing plug to form a low doping concentration of the selective epitaxial polysilicon layer, and then forming a metal plug to form a smooth contact between the metal plug and the ohmic The present invention relates to a method for manufacturing a semiconductor device capable of preventing the deterioration of the device performance by impurity diffusion.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate, but is primarily proportional to the light source wavelength (??) and the process variable (k) of the reduction exposure apparatus used. It is inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A tri layer resister (hereinafter referred to as a TLR) in which a contrast enhancement layer (CEL) method or an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. A method or a silicide method for selectively injecting silicon on top of the photoresist film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the diameter of the contact hole is reduced. The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

Since the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current state of the art, there is a limit to high integration of the device.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

1 is a cross-sectional view of a semiconductor device having a metal landing plug according to the prior art.

First, the gate insulating film 12 is formed on the semiconductor substrate 10, and then the gate electrode 18 and the insulating spacer 20 overlapping the hard mask layer 16 pattern are formed on the gate insulating film 12. The interlayer insulating film 20 is formed on the entire surface of the structure.

Thereafter, the interlayer insulating layer 20 is etched using a landing plug mask to form a landing plug contact hole to expose the semiconductor substrate 10.

Next, a selective epitaxial polysilicon layer 22 is formed on the semiconductor substrate 10 exposed by the contact hole, and the doping impurities are formed to have a concentration of 1E20 / cm 3 or more for ohmic contact with the metal. After filling the contact hole by applying the landing plug metal layer 24 to the entire surface of the structure, the upper part of the metal layer 24 is etched by CMP or the like method to separate the metal layer independent of the epitaxially grown polycrystalline silicon layer 22 ( 24) Form a landing plug in a pattern.

After that, although not shown, the device is configured by forming bit lines, capacitors, metal wires, and the like on the structure.

In the method of manufacturing a semiconductor device according to the prior art as described above, a landing plug used for a bit line, a capacitor contact, or the like uses a landing plug made of a metal material having a lower resistivity than a polysilicon layer, wherein an error between the metal landing plug and the substrate is used. In order to reduce the MIC contact and contact resistance, an impurity doped select epitaxial polysilicon layer is formed on the substrate, and an impurity concentration of about 1E20 / cm 3 is formed.

As a result, impurities in the selective epitaxial polysilicon layer diffuse into the substrate during the subsequent heat treatment process, thereby deteriorating the punch characteristics of the cell transistors and lowering the Vt of the cell.

The present invention is to solve the above problems, an object of the present invention is to form a selective epitaxial polysilicon layer interposed between the substrate and the metal plug in a semiconductor device having a metal landing plug by undoping or low concentration doping and A method of manufacturing a semiconductor device capable of improving ohmic contact with subsequent ion implantation to prevent deterioration of punch characteristics of a cell transistor due to diffusion of an impurity substrate or to reduce Vt, thereby improving process yield and device operation reliability. Is in.

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a gate insulating film on the semiconductor substrate;

Forming a gate electrode overlapping the hard mask layer pattern on the gate insulating film;

Forming an insulating spacer on sidewalls of the hard mask layer pattern and the gate electrode;

Forming an interlayer insulating film on the entire surface of the structure;

Forming a contact hole for a landing plug by removing an interlayer insulating film on a portion of the semiconductor substrate, which is intended to be a contact;

Forming an epitaxially grown polysilicon layer on the semiconductor substrate exposed through the contact hole, and forming the selective epitaxial polysilicon layer by undoping or forming a doped concentration of 1E14 to 1E18 / cm 3;

And forming an ohmic contact layer by implanting impurity ions on the selective epitaxial polysilicon layer, and forming a metal plug made of a metal material in contact with the ohmic contact layer.

Further, another feature of the present invention is that ion implantation into the selective epitaxial polysilicon layer is carried out at P or As, and when the selective epitaxial polysilicon layer is formed at 1E14 to 1E18 / cm3 impurity doping concentration, subsequent ions When the implantation is performed at a concentration of 1E15 to 1E21 / cm 3 and the selective epitaxial polysilicon layer is formed by undoping, implantation of impurity ions is carried out at least twice, but the second implantation is P or As, respectively. The ion implantation is performed at concentrations of 1E13 to 1E18 / cm 3 and 1E14 to 1E18 / cm 3, respectively.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are manufacturing process diagrams of a semiconductor device according to the present invention, which is an example of using a metal plug as a landing plug.

First, an isolation region (not shown) is formed on one side of the semiconductor substrate 30 to define an active region, and a gate insulating film 32 made of an insulating material such as an oxide film or a nitride film is formed on the entire surface of the structure. A gate electrode 34 is formed on the gate insulating layer 32, and overlaps the pattern of the hard mask layer 36. An insulating spacer is formed on sidewalls of the pattern of the hard mask layer 36 and the gate electrode 34. 38). The gate electrode 34 may be formed of a polysilicon layer and a W silicide material, and the hard mask layer 36 may be formed of a nitride film, and the spacer 38 may be coated on the entire surface of the nitride film, and then etched to form an etch barrier layer. Form.

Then, an interlayer insulating film 40 made of an oxide film such as BPSG is formed on the entire surface of the structure, wet heat treatment is performed to smooth gap fill, and the upper part is etched and planarized by a chemical mechanical polishing method, followed by a landing plug mask. The contact hole 41 for the landing plug is formed by removing the interlayer insulating film 40 on the portion of the semiconductor substrate 30, which is intended to be a contact, on the semiconductor substrate 30 by using a. (See FIG. 2A).

Thereafter, a selective epitaxially grown polysilicon layer 42 is formed on the semiconductor substrate 30 exposed by the contact hole 41, but is formed by undoping, or an impurity concentration of 1E14 to 1E18 / cm 3 or less is formed. After forming to form, the ohmic contact layer 43 is formed by implanting impurity ions into the upper portion of the selective epitaxial polysilicon layer 42 for ohmic contact. As the impurity implanted herein, As or P may be used, and a doping concentration and a doping method may be variously used depending on the degree of doping of the selective epitaxial polysilicon layer 42.

Ie (1). If the selective epitaxial polysilicon layer 42 has a doping concentration of about 1E14 to 1E18 / cm 3 or a doping concentration of about the same as the semiconductor substrate 30, subsequent ion implantation is performed at about 1E15 to 1E21 / cm 3. And (2). When the selective epitaxial polysilicon layer 42 is formed by undoping, implanting impurity ions at least twice to reduce the diffusion of impurities into the lower semiconductor substrate 30 and to make ohmic contact with the upper metal plug. can do. In this case, two ion implantations are performed at concentrations of 1E13 to 1E18 / cm 3 and 1E14 to 1E18 / cm 3 at the time of one or the second ion implantation, respectively. (See FIG. 2B).

Next, a conductive layer 44 made of metal, which is a metal plug, is applied to the entire surface of the structure to fill the contact hole 41, and the conductive layer 44 on the hard mask layer 36 pattern is CMP. Or a landing plug that fills the contact hole by a method such as a front etch, and the like to form a selective epitaxial polysilicon layer 43 and a conductive layer 44 pattern. (See FIG. 2C).

Thereafter, although not shown, the semiconductor substrate having the above structure is heat treated, and bit lines, capacitors, metal wirings, and the like are formed to complete the device.

As described above, in the method of manufacturing a semiconductor device according to the present invention, in a semiconductor device in which the landing plug includes a selective epitaxial polysilicon layer and a metal plug, the selective epitaxial polysilicon layer is formed by low concentration impurity doping, and the upper portion thereof. After implanting impurity ions into the ohmic contact layer to form an ohmic contact layer, the subsequent process was performed, thereby preventing deterioration of the device characteristics due to diffusion of impurities from the selective epitaxial polysilicon layer to the semiconductor substrate and reducing contact resistance. There is an advantage that can improve the process yield and the reliability of device operation.

Claims (4)

Forming a gate insulating film on the semiconductor substrate; Forming a gate electrode overlapping the hard mask layer pattern on the gate insulating film; Forming an insulating spacer on sidewalls of the hard mask layer pattern and the gate electrode; Forming an interlayer insulating film on the entire surface of the structure; Forming a contact hole for a landing plug by removing an interlayer insulating film on a portion of the semiconductor substrate, which is intended to be a contact; Forming an epitaxially grown polysilicon layer on the semiconductor substrate exposed through the contact hole, and forming the selective epitaxial polysilicon layer by undoping or forming a doped concentration of 1E14 to 1E18 / cm 3; Forming an ohmic contact layer by implanting impurity ions on the selective epitaxial polysilicon layer; And forming a metal plug made of a metal material in contact with the ohmic contact layer. The method of manufacturing a semiconductor device according to claim 1, wherein ion implantation into the selective epitaxial polysilicon layer is performed at P or As. The method of claim 1, wherein when the selective epitaxial polysilicon layer is formed at a concentration of 1E14 to 1E18 / cm 3 impurity, subsequent ion implantation is performed at a concentration of 1E15 to 1E21 / cm 3. The method of claim 1, wherein when the selective epitaxial polysilicon layer is formed by undoping, at least two ion implantations are performed, and the second ion implantation is performed at 1E13 to 1 or 2, respectively, for P or As. A method for manufacturing a semiconductor device, characterized by performing at concentrations of 1E18 / cm 3 and 1E14 to 1E18 / cm 3.

Images