JPH04208520A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To conduct lithography and etching at the time of No.2 layer and subsequent wiring formation easily by completely burying a stepped section between wirings with a BPSG film and forming self-alignment contacts to the wirings. CONSTITUTION:A contact forming section is coated with a photo-resist 108, and a contact pattern overlapped to gate electrodes at both side is formed. The residue of polysilicon is removed and the columnar pattern of a polysilicon film 107 is shaped at a stepped section between the gate electrodes. The photo- resist 108 is taken off, a BPSG film 109 is formed, a surface is flattened through reflow, and the BPSG film 109 is etched back and the upper section of the polysilicon film 107 is projected onto the BPSG film 109. The polysilicon film 107 is removed through isotropic etching, and an oxide film 104 is etched back, thus shaping a self-alignment contact 111 while using the BPSG film 109 as a mask. Accordingly, a post-process is facilitated.

Description

[Detailed description of the invention]

[00011

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming contact holes (hereinafter referred to as self-line contacts) that are self-aligned with wiring formed on a semiconductor substrate. [0002] A conventional method for forming a self-line contact includes steps shown in FIGS. 15 to 17. First, as shown in FIG.
An oxide film 2O2 is formed to perform element isolation. After forming the gate oxide film, the two-layer structure of the polysilicon film and the oxide film is etched using a photoresist as a mask to form a two-layer wiring structure of the gate polysilicon film 203 and the oxide film 204. Next, oxide film sidewall 2
05 and HTO film (high temperature vapor phase grown oxide film) 206
is formed as an interlayer insulating film. Next, as shown in FIG. 46, a slightly larger contact pattern is formed using photoresist 208 in the contact hole forming area so as to span the wiring on both sides. Next, as shown in FIG. 17, the HTO film 206 is anisotropically etched using the photoresist 208 as a mask to open a contact hole.
Photoresist 208 is removed and self-line contacts 211 are formed. [0003]

SUMMARY OF THE INVENTION In the above-described conventional method of forming self-line contacts, the level differences between the wirings remain as they are. When forming an upper layer wiring or the like thereon after forming a contact hole, there is a problem in that patterning and etching using photoresist are difficult due to this large step. [0004]

[Means for Solving the Problems] The method for forming a self-line contact of the present invention includes the steps of forming an insulating film on wirings having oxide film sidewalls, and then forming an insulating film on the wirings until the recesses between the wirings are completely filled. A process of forming a polysilicon film and diffusing phosphorus into it, a process of performing quasi-anisotropic etching of the polysilicon film using a photoresist as a mask to form a columnar pattern of the polysilicon film in the contact hole formation area, and then A process of forming a BPSG film and planarizing it, a process of removing the columnar patterned polysilicon film by isotropic etching, and then etching back the oxide film using the BPSG film as a mask to form a self-line contact. and a step of forming. By performing the above steps, a self-line contact can be formed in a state where the stepped portion between the interconnects is completely filled with the BPSG film. [0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. 1 to 7 are cross-sectional views showing the steps of manufacturing a semiconductor device for explaining a first embodiment of the present invention. [0006] First, in FIG. 1, a LOCO3 oxide film 1O2 is formed on a semiconductor substrate 101 to form an element isolation region. Next, after forming a gate oxide film, a gate electrode having a two-layer structure of gate polysilicon 103 and oxide film 104 is formed. At this time, the film thickness of the gate polysilicon 103 is about 300 nm, and the film thickness of the oxide film 104 is about 300 nm.
It is about nm. The gate electrode was anisotropically etched by RIE using a photoresist (not shown) as a mask. The etching conditions for the oxide film 104 are CF
420SCCm, RF power 1000W, pressure 10Pa
It is. On the other hand, the etching conditions for gate polysilicon 103 are CCl2 F2 /N2 = 30se
cm/10105e, RF power 700W, pressure 18
It is Pa. Next, after removing the photoresist, the HT
An O film is formed and etched back to form an oxide film sidewall 105. Next, HTOIII
06 to a thickness of about 150 nm. [0007] On this, as shown in FIG. 2, a polysilicon film 107 of about 600 nm was formed, and phosphorus was diffused into this to give ρ3=16 ohms/square. [0008] Next, a contact pattern is formed using a photoresist 108 so as to sufficiently cover the contact forming portion and overlap the gate electrodes on both sides of the contact pattern. Quasi-anisotropic etching is again performed using RIE so that there is no remaining polysilicon in the stepped portion between the gate electrodes, thereby forming a columnar pattern of polysilicon film as shown in FIG. The etching conditions at this time are as follows. First, CCl2 F2 /N2 =
Anisotropic etching is performed under the conditions of 30 sc cm/10 sc cm, RF power of 700 W, and pressure of 18 Pa. Subsequently, SF6 /CCl2 F2=5
0sc, cm/10105c. Quasi-anisotropic etching under the conditions of RF power 40QW and pressure 12Pa is added. [0009] After removing the photoresist 108, FIG.
As shown in FIG.
00°C for 30 minutes to flatten the surface. Next, as shown in FIG. 5, the BPSG film 109 is etched back so that the upper part of the polysilicon film 107 is
Make it so that it is on the 0 film and on the 09 film. Next, in FIG. 6, polysilicon film 107 is removed by isotropic etching. Next, by etching back the oxide film, the BPS
Using the G film 109 as a mask, a self-line contact 111 shown in FIG. 7 is formed. [00101 FIGS. 8 to 14 are cross-sectional views in order of manufacturing steps of a semiconductor device for explaining a second embodiment of the present invention. The manufacturing method shown in FIGS. 8 to 10 is the same as the manufacturing method shown in FIGS. 1 to 3 in the first embodiment of the present invention. [00111 In this embodiment, in FIG.
After the film 109 is formed and reflowed, a coated insulating film 110 is further formed to completely planarize the surface of the semiconductor device. The self-line contact 111 is formed through the subsequent steps shown in FIGS. 12 to 14 (same steps as those described in FIGS. 5 to 7 of the first embodiment). [00123 In this example, BPSG after etchback
Since the flatness of the film surface is further improved, there is an advantage that lithography and etching become easier when forming wiring or the like on the gate electrode. [0013]

As described above, according to the present invention, it is possible to completely fill the stepped portion between wirings with a BPSG film and form a self-line contact to the wirings. Therefore, the area other than the contact hole becomes substantially flat, which has the effect that lithography and etching when forming the second and subsequent layers of wiring can be performed extremely easily.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an intermediate process for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 3 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 4 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 5 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 6 is a sectional view of an intermediate process for explaining the first embodiment of the present invention.

FIG. 7 is a sectional view of the final step for explaining the first embodiment of the present invention.

FIG. 8 is a cross-sectional view of an intermediate step for explaining a second embodiment of the present invention.

FIG. 9 is a sectional view of an intermediate process for explaining a second embodiment of the present invention.

FIG. 10 is a cross-sectional view of an intermediate process for explaining a second embodiment of the present invention.

FIG. 11 is a cross-sectional view of an intermediate process for explaining a second embodiment of the present invention.

FIG. 12 is a sectional view of an intermediate process for explaining a second embodiment of the present invention.

FIG. 13 is a sectional view of an intermediate process for explaining a second embodiment of the present invention.

FIG. 14 is a sectional view of the final step for explaining the second embodiment of the present invention.

FIG. 15 is a cross-sectional view of an intermediate process for explaining a conventional technique.

FIG. 16 is a cross-sectional view of an intermediate process for explaining a conventional technique.

FIG. 17 is a cross-sectional view of the final process for explaining the conventional technique.

[Explanation of symbols]

101 201 Semiconductor substrate 102 2O2LOCO3 oxide film 103 203 Gate polysilicon 104 20
4 Oxide film 105 205 Oxide film side wall 106 2
06 HTO film 107 Polysilicon film 108.208 Photoresist 109 8PSG film 110 Coated insulating film

Claims (2)

[Claims] 1. In the step of forming a self-aligned contact hole with respect to wiring formed on a semiconductor substrate, CV
forming an insulating film covering the wiring by method D; forming a polysilicon film on the insulating film until the recesses between the wirings are completely filled; and diffusing phosphorus into the polysilicon film; A step of performing quasi-anisotropic etching on the polysilicon film using a photoresist as a mask to form a columnar pattern of the polysilicon film in the contact hole formation area, and a step of etching the polysilicon film in the columnar pattern using a CVD method. A BPSG film is formed to cover the BPS.
A step of flattening the G film by reflow, and
A step of etching back the film to expose the upper part of the polysilicon film in the columnar pattern, a step of removing the polysilicon film in the columnar pattern by isotropic etching, and performing the etchback to expose the upper part of the polysilicon film on the semiconductor substrate. A method of manufacturing a semiconductor device, comprising the step of forming a contact hole. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a coated insulating film after forming and reflowing the BPSG film.