KR100367495B1 - Method for manufacturing contact hole in semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a contact hole in a semiconductor device is provided to simplify manufacturing processes by simultaneously forming contact holes at a peripheral and cell region. CONSTITUTION: A gate oxide layer(2), a gate electrode(3) and a hard mask(4) are sequentially formed on a substrate(1) defined by a cell and peripheral region. An etch barrier layer(7) and an interlayer dielectric(8) are sequentially formed on the resultant structure. A photoresist pattern is formed to expose the substrate of the cell region and to expose the hard mask(4) of the peripheral region. The first contact hole(10) is formed by etching the interlayer dielectric and the etch barrier layer. After removing the photoresist pattern, an insulating spacer(11A) is formed at both sidewalls of the first contact hole(10). The second contact hole(13) is formed to expose the gate electrode of the peripheral region by etching the exposed hard mask using the insulating spacer(11A) as a mask.

Description

Contact hole formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact hole in a semiconductor device. In particular, in the process of forming a contact hole of a self-aligning method using a nitride film as an etch barrier layer, a process of forming contact holes in a peripheral circuit region and a cell region simultaneously with a single mask process The present invention relates to a simple method for manufacturing a contact hole of a semiconductor device capable of improving process yield and reliability of device operation.

Recently, the trend of high integration of semiconductor devices is greatly influenced by the development of fine pattern formation technology. In particular, the photoresist pattern is widely used as a mask for etching or ion implantation in the semiconductor device manufacturing process.

Therefore, miniaturization of the photoresist pattern is essential for high integration of semiconductor devices. The resolution of the photoresist pattern is proportional to the wavelength and process variables of the light source of the reduction exposure apparatus, and inversely proportional to the numerical aperture (NA) of the reduction exposure apparatus. do.

In this case, the wavelength of the light source is reduced to improve the optical resolution of the reduction exposure apparatus. For example, the G-ray and i-ray reduction exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Is the limit.

Therefore, a narrow exposure apparatus using a deep ultra violet, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source to form a fine pattern of 0.5 μm or less.

In addition, the contact hole connecting the upper and lower conductive wiring is reduced in size and the distance between the peripheral wiring and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

The contact holes may have misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, and mask to maintain spacing. The mask is formed by considering factors such as liver registration.

In addition, in order to overcome the limitations of the lithography process in forming the contact holes, a self-aligned contact hole (hereinafter referred to as SAC) forming technology has been developed.

FIG. 1 is a schematic diagram illustrating a process of manufacturing a contact hole in a semiconductor device according to the prior art, and is an example of forming contact holes in a peripheral circuit region and a cell region by a SAC manufacturing method using a nitride film.

First, a device isolation oxide film (not shown) and a gate oxide film 2 on the semiconductor substrate 1, a gate electrode 3 having a polysilicon layer pattern, and a mask oxide film overlapping the gate electrode 3 ( 4) A pattern is formed, an oxide spacer 5 is formed on sidewalls of the gate electrode 3 and the mask oxide layer 4 pattern, and a source / drain junction 6 is formed through an ion implantation process. Here, one side of the semiconductor substrate 1 is a cell region I in which a pattern is dense, and the other side is a peripheral circuit region II.

Then, after the barrier nitride film 7 is formed on the entire surface of the structure, the planarization film 8 of oxide material is formed on the barrier nitride film 7 and planarized thereon, and a lithography process using a photosensitive material thereon. A first photoresist pattern (not shown) is formed to expose a portion where the contact hole is to be formed. In the peripheral circuit region II, the upper portion of the gate electrode 3 is exposed, and in the cell region I, the source / drain junction 6 portion is exposed.

Thereafter, the planarization film 8 is etched using the first photoresist pattern as a mask to expose the barrier nitride film 7, and subsequently the exposed barrier nitride film 7 is removed to form a first contact in the cell region I. The hole 10 is formed. In this case, the spacer 5 and the source / drain junction 6 are exposed in the cell region I through the first contact hole 10, and the mask oxide layer 4 pattern is exposed in the peripheral circuit region II.

Then, the first photoresist pattern is removed, and a second photoresist pattern (not shown) for exposing only the pattern of the mask oxide layer 4 of the exposed peripheral circuit region (II) is formed, and then the mask is used as a mask. The pattern of the mask oxide layer 4 is etched to form a contact hole 13 in the peripheral circuit region II exposing the gate electrode 3.

In the method of manufacturing a contact hole of a semiconductor device according to the related art as described above, a contact hole mask in a peripheral circuit region (II) must be separately formed due to a difference in structure of the contact hole in the cell region (I) and the peripheral circuit region (II). Therefore, additional reticle manufacturing, mask formation, mask removal, etc. are added, and the process of metal etching process, which is a subsequent process, is caused by the increase of the step difference with the cell area due to the front side etching of the peripheral circuit part. There is a problem that the yield and reliability of device operation are inferior.

The present invention is to solve the above problems, the object of the present invention is to form an oxide spacer on the sidewall of the etched contact hole and the primary etching only to the barrier nitride when forming the contact hole of the cell region and the peripheral circuit region together Afterwards, the spacer is continuously etched with a mask to prevent the oxide spacers from protecting the exposed portions of the gate electrode, thereby preventing short circuits between the conductive wirings, and the process is simple. It is to provide a method for manufacturing a contact hole of a semiconductor device that can improve the.

A feature of the method for manufacturing a contact hole of a semiconductor device according to the present invention for achieving the above object is to form a gate electrode with a gate oxide interposed on a semiconductor substrate in which a cell region and a peripheral circuit region are defined, but hard on top Fixing to form the gate electrode with a mask layer,

Forming an etch barrier layer and an interlayer insulating film on the entire surface of the structure;

Forming a photoresist pattern as a contact etch mask on the interlayer insulating layer, exposing an upper side of the semiconductor substrate in a cell region, and forming the photoresist pattern for exposing an upper side of a gate electrode of a peripheral circuit region;

Etching the interlayer insulating layer and the etch barrier layer using the photoresist pattern as a mask to form a first contact hole exposing the semiconductor substrate in the cell region and the hard mask layer in the peripheral circuit region, and removing the photoresist pattern;

Forming an insulating film spacer on a sidewall of the first contact hole with a material having an etching select difference from the hard mask layer and the semiconductor substrate;

And etching the hard mask layer of the peripheral circuit region using the insulating layer spacer as a mask to form a second contact hole exposing the gate electrode of the peripheral circuit region.

Hereinafter, a method for manufacturing a contact hole of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are examples of manufacturing a contact hole of a semiconductor device according to the present invention, and forming contact holes in a cell region and a peripheral circuit region at the same time.

First, a device isolation oxide film (not shown) is formed on the semiconductor substrate 1 to define a cell region I and a peripheral circuit region II. The gate oxide film 2 is formed on the entire surface of the structure. ), A mask oxide film 4 pattern is formed on the gate oxide film 2 as a gate insulating film 3 having a polysilicon layer pattern and a mask insulating film overlapping the gate electrode 3.

Next, an oxide spacer 5 is formed on sidewalls of the gate electrode 3 and the mask oxide layer 4 pattern, and a source / drain junction 6 is formed through an ion implantation process to complete a MOS field effect transistor. An etching barrier layer serving as an etch barrier during contact hole etching, for example, is formed on the entire surface of the structure, and then the barrier nitride film 7 is formed, and the B.P.S. A planarization film 8 made of Boro Phospho Silicate Glass (hereinafter referred to as BPSG) or Teos (Tetra etchyl orthor silicate (hereinafter referred to as TEOS)) oxide material is formed and planarized.

Thereafter, a portion in which a contact hole is formed through a lithography process using a photosensitive material on the planarization film 8, for example, in the peripheral circuit region II, is an upper portion of the gate electrode 3 and a cell region ( In I), the photosensitive film pattern 9 which exposes the planarization film 8 of the upper part of the source / drain junction 6 is formed. (See also FIG. 2A).

Next, the planarization layer 8 and the barrier nitride layer 7 are etched using the photoresist pattern 9 as a mask to form a first contact hole 10 in the cell region I. In this case, the spacer 5 and the source / drain junction 6 are exposed in the cell region I through the first contact hole 10, and the mask oxide layer 4 pattern is exposed in the peripheral circuit region II.

In this case, the first etching of the first contact hole 10 to the barrier nitride layer 7 is performed by reducing the etching thickness in the insulating film spacer process, which is the next process, and in the case of the entire surface etching such as the spacer etching, the etching uniformity is deteriorated. In the case of etching, the type of the etching target is changed in the middle of the etching process, resulting in discontinuity of etching at the interface of the etching target, resulting in deterioration of etching uniformity. In addition, to easily remove the nitride film on the side of the spacer. (See also FIG. 2B).

Thereafter, an etch selectivity difference with the mask oxide film 4 and the semiconductor substrate 1, such as an insulating material, for example, chemical vapor deposition (CVD) or a nitride film, is applied to the entire surface of the structure. Is formed of a material having a relatively large material, and is formed of a material having an etching selectivity difference from that of the mask oxide film 4 pattern (see FIG. 2C). After the insulating film spacers 11A having the insulating film 11 pattern are formed on the sidewalls of the holes 10, in the peripheral circuit region II exposed by the insulating film spacers 11A inside the contact hole 10. The pattern of the mask oxide layer 4 is etched to form a second contact hole 13 in the peripheral circuit region II exposing the gate electrode 3. (See also 2D).

As described above, in the method of manufacturing a contact hole of a semiconductor device according to the present invention, when forming contact holes in a cell region and a peripheral circuit region having different structures in a SAC using a barrier nitride layer as an etch barrier for contact hole etching, The interlayer insulating film and the barrier nitride film are etched using an etching process using a contact etching mask that exposes a source / drain junction in the cell region and exposes an upper side of the mask oxide layer pattern overlapping the gate electrode in the peripheral circuit region. After the first contact hole is formed, an insulating film spacer is formed on the sidewall of the first contact hole, and the mask oxide film pattern of the peripheral circuit area is etched using the insulating film spacer as a mask to form a second contact hole in the peripheral circuit area. Simple process can improve process yield and reliability of device operation. When forming the second contact hole, there is no need to form an additional reticle or an etching mask, thereby reducing manufacturing costs.

1 is a schematic view for explaining a process for manufacturing a contact hole in a semiconductor device according to the prior art.

2A to 2D are manufacturing process diagrams of a semiconductor device according to one embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

1 semiconductor substrate 2 gate oxide film

3: gate electrode 4: mask oxide film

5 oxide film spacer 6 source / drain junction

7: barrier nitride film 8: planarization film

9: photosensitive film pattern 10: first contact hole

11 insulating film 11A insulating film spacer

13: second contact hole

Claims (5)

Forming a gate electrode having a gate oxide layer interposed therebetween on a semiconductor substrate having a cell region and a peripheral circuit region defined therein, and forming the gate electrode having a hard mask layer thereon; Forming an etch barrier layer and an interlayer insulating film on the entire surface of the structure; Forming a photoresist pattern as a contact etch mask on the interlayer insulating layer, exposing an upper side of the semiconductor substrate in a cell region, and forming the photoresist pattern for exposing an upper side of a gate electrode of a peripheral circuit region; Etching the interlayer insulating film and the etch barrier layer using the photoresist pattern as a mask to form a first contact hole exposing the semiconductor substrate in the cell region and the hard mask layer in the peripheral circuit region, and removing the photoresist pattern; Forming an insulating film spacer on a sidewall of the first contact hole with a material having an etching select difference from the hard mask layer and the semiconductor substrate; And etching the hard mask layer in the peripheral circuit region using the insulating film spacer as a mask to form a second contact hole exposing the gate electrode in the peripheral circuit region. The method of claim 1, The method of claim 1, wherein the hard mask layer is formed of an oxide film. The method of claim 1, And forming the etch barrier layer as a nitride film. The method of claim 1, And forming the interlayer dielectric layer from a BPSG or TEOS oxide layer. The method of claim 1, And forming the insulating film spacer into an oxide film or a nitride film formed by a CVD method.