KR100876842B1 - Method for manufacturing of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device, in which a dummy storage electrode is formed in a fuse region so as to leave a constant thickness of a residual insulating film on a plate electrode of a fuse region, thereby eliminating a step between a cell region and a plate electrode of a fuse region. Therefore, during the etching process for opening the fuse, an insulating film having a predetermined thickness is left on the plate electrode of the fuse region, thereby preventing a fuse fail due to laser blowing.

Cylindrical, Capacitor, Blowing

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A and 2B are photographs for explaining problems of the method of manufacturing a semiconductor device according to the prior art.

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

4 is a plan view showing a semiconductor device according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a plate electrode as a fuse.

Recently, a DRAM device having a high capacity has been used as a semiconductor memory device. The DRAM element is composed of a memory cell region for storing information data in the form of electric charge and a peripheral circuit region for input / output of data, and basically includes one transistor and one capacitor. However, as the memory devices are highly integrated and the design rules become smaller, it is difficult to secure the capacitance of the capacitor.

As a solution to this, the lower electrode of the capacitor is formed into a three-dimensional structure such as a cylinder structure and a concave structure.

The cylinder structure forms a trench for forming a storage electrode in the oxide film, deposits a titanium nitride (TiN) film inside the trench to form a lower electrode, and then performs a full dip-out process for removing the oxide film. The dielectric film and the upper electrode are formed.

On the other hand, as semiconductor devices are highly integrated, memory capacity increases, and chip size increases.In the case of manufacturing a semiconductor device, if a defect occurs in any one of many fine cells, the entire device is treated as a defective product. Disposal results in low device yield.

Therefore, the current yield of the chip is improved by replacing an extra redundancy cell previously formed in the memory with a cell in which a defect has occurred during the manufacturing process to restore the entire memory.

In the repair operation using the redundancy cell, when a defective memory cell is selected through a test after wafer processing is completed, a program for converting the corresponding address into an address signal of the spare cell is executed in the internal circuit. Therefore, when an address signal corresponding to a defective line is input in actual use, the selection is changed to a spare line instead of the defective cell.

In order to perform the repair operation as described above, after completing the semiconductor device, the fuse box is opened by removing an oxide layer on the top of the fuse line in order to repair the circuit in which the failure occurs, and the corresponding fuse line is lasered. It must be cut through. In this case, the wiring broken by the laser irradiation is called a fuse line, and the broken portion and the area surrounding the wiring are called a fuse box.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a storage electrode contact hole 25 that forms an interlayer insulating layer 23 on a semiconductor substrate 21 on which a cell region and a fuse region are intended and exposes the semiconductor substrate 21 using a storage electrode contact mask. To form.

Then, the storage electrode contact plug 27 filling the storage electrode contact hole is formed.

In this case, the process of forming the storage electrode contact plug 27 on the semiconductor substrate 21 will be described in more detail as follows.

First, an isolation layer is formed on the semiconductor substrate 21 on which the cell region and the fuse region are intended, and a recess gate is formed in the gate intended region.

In addition, a landing plug contact hole exposing the semiconductor substrate 21 of the bit line contact region and the storage electrode contact region by forming a lower insulating layer on the entire surface and etching the lower insulating layer by a photolithography process using a landing plug contact mask. To form.

Then, after forming a landing plug to fill the landing plug contact hole, a first interlayer insulating film is formed over the entire surface.

Next, the first interlayer insulating layer is etched by a photolithography process using a bit line contact mask to form a bit line contact hole.

Next, a conductive film is embedded in the bit line contact hole to form a bit line contact plug.

Next, a bit line is formed on the bit line contact plug, and a second interlayer insulating film covering the bit line is formed.

Next, the second interlayer insulating layer and the first interlayer insulating layer of the cell region are etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole.

Thereafter, a conductive film is embedded in the storage electrode contact hole to form the storage electrode contact plug 27.

Next, an etch stop layer 29 is formed on the interlayer insulating layer 23. In this case, the etch stop layer 29 is formed of a nitride layer.

Next, the first sacrificial oxide film 31, the second sacrificial oxide film 33, the hard mask layer 35, and the anti-reflection film 37 are sequentially formed on the etch stop layer 29.

Next, a first photoresist film (not shown) is formed on the antireflection film 37, and the first photoresist film is exposed and developed with a storage electrode mask (not shown) to form a first photoresist film pattern 39.

Referring to FIG. 1B, the anti-reflection film 37, the hard mask layer 35, the second sacrificial oxide film 33, the first sacrificial oxide film 31, and the etch stop film 29 are formed by using the first photoresist pattern 39 as a mask. ) Is etched to form the storage electrode region 41.

Next, the first photosensitive film pattern 39, the antireflection film 37, and the hard mask layer 35 are removed.

Referring to FIG. 1C, a conductive film 43 is formed over the entire surface including the storage electrode region 41.

At this time, the conductive film 43 is formed in a stacked structure of a titanium (Ti) film and a titanium nitride (TiN) film.

Referring to FIG. 1D, a second photoresist layer (not shown) is formed on the entire surface, and the storage electrode 44 is formed by performing a planarization process on the second photoresist layer until the second sacrificial oxide layer 33 is exposed. To complete.

Next, the second photoresist film is removed, and a capping oxide film 45 is formed on the entire surface.

Referring to FIG. 1E, the capping oxide layer 45, the second sacrificial oxide layer 33, and the first sacrificial oxide layer 31 may be formed by performing a full dip-out process using a chemical solution. Remove it completely.

Next, a dielectric film 47 is formed over the storage electrode 44.

Referring to FIG. 1F, a titanium nitride (TiN) film 49a and a polysilicon film 49b are sequentially stacked on the dielectric film 47 to form a plate electrode 49 to complete a capacitor.

In this case, the plate electrode 49 in the fuse area is used as a fuse.

Subsequently, a fourth interlayer insulating film (not shown), a first metal interconnection contact plug (not shown), a first metal wiring (not shown), a fifth interlayer insulating film (not shown), and an upper portion of the plate electrode 49 are formed thereon. A contact plug for a metal wiring (not shown), a second metal wiring (not shown), and a protective film (not shown) are formed.

Next, a fuse open area (not shown) is formed by a photolithography process using a fuse open mask (not shown) to leave the fourth interlayer insulating film having a predetermined thickness on the plate electrode 49 of the fuse area.

Next, a fuse blowing process of cutting the plate electrode 49 in the fuse area corresponding to the cell in which the failure occurs is performed by laser.

2A and 2B are photographs for explaining a problem of a method of manufacturing a semiconductor device according to the prior art.

2A and 2B, the capping oxide layer 45, the second sacrificial oxide layer 33, and the first sacrificial oxide layer 31 are completely removed during a full dip-out process. Therefore, a step is formed largely between the plate electrode 49 of the cell region and the fuse region, and the fourth interlayer insulating layer is formed thickly on the plate electrode 49.

As a result, the fourth interlayer insulating layer on the plate electrode 49 may not be sufficiently removed due to the lack of an etching target in the photolithography process using the fuse open mask, and thus the thickness is formed thicker than a target value (about 2500 kV).

That is, it can be seen that the fuse box edge portion (FIG. 2A) is formed to a thickness of about 12500 kPa and the fuse box inside (FIG. 2B) is formed to a thickness of about 14000 kPa.

In the above-described method of manufacturing a semiconductor device according to the related art, the fourth interlayer insulating film on the plate electrode is thickly formed by a full dip-out process for forming a cylindrical capacitor, thereby forming a fuse open mask. In the photolithography process used, an etching target is insufficient.

Therefore, the fourth interlayer insulating film is thicker than the target value (about 2500 kV) on the plate electrode, so that the plate electrode is not broken during laser blowing, causing a problem.

SUMMARY OF THE INVENTION The present invention was created to solve the above problems, and by forming a dummy capacitor in the fuse region, a method of manufacturing a semiconductor device capable of leaving an insulating film having a predetermined thickness on the plate electrode of the fuse region during an etching process for opening the fuse. The purpose is to provide.

A method of manufacturing a semiconductor device according to the present invention includes forming an insulating layer on a semiconductor substrate; Etching the insulating layer to form a storage electrode region in a cell region by using a photolithography process using a storage electrode mask, and forming a dummy storage electrode region in a fuse region; Forming a storage electrode in the cell region and forming a dummy storage electrode in the fuse region; Removing the insulating layer by performing a full dip-out process; And sequentially forming a dielectric film and a plate electrode in front of the storage electrode and the dummy storage electrode.

Forming an interlayer insulating film between the semiconductor substrate and the insulating layer, further comprising forming an etch stop film between the semiconductor substrate and the insulating layer, wherein the insulating layer comprises a first sacrificial oxide film and a first insulating film; 2 is a laminated structure of the sacrificial oxide film, and further comprising the step of sequentially forming a hard mask layer and an anti-reflection film on the insulating layer,

The forming of the storage electrode region and the dummy storage electrode region may include forming the storage electrode region by a photolithography process using a first storage electrode mask that defines the storage electrode region of the cell region, and the storage electrode region of the fuse region. Forming a dummy storage electrode region by a photolithography process using a second storage electrode mask defining a;

The forming of the storage electrode region and the dummy storage electrode region may include applying a first photoresist layer on the insulating layer; Exposing the first photoresist film by using the first storage electrode mask; Developing the first photoresist film to form a first photoresist pattern; Etching the insulating layer using the first photoresist pattern as a mask to form a storage electrode region; Applying a second photoresist film on the insulating layer; Exposing the second photoresist layer by using the second storage electrode mask; Developing the second photoresist film to form a second photoresist pattern; Etching the insulating layer using the second photoresist pattern as a mask to form a dummy storage electrode region;

The forming of the storage electrode region and the dummy storage electrode region may include applying a photoresist film on the insulating layer; Exposing the photoresist using the first storage electrode mask; Exposing the photoresist using the second storage electrode mask; Developing the photoresist to form a photoresist pattern; Etching the insulating layer using the photoresist pattern as a mask to form a storage electrode region and a dummy storage electrode;

The conductive layer may be formed in a stacked structure of a titanium (Ti) layer and a titanium nitride (TiN) layer, and after the forming of the storage electrode and the dummy storage electrode, forming a capping oxide layer over the entire surface. Further comprising, the capping oxide film is removed during the full dip-out process, the plate electrode is characterized in that the titanium nitride (TiN) film and a polysilicon film formed .

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 3A, a storage electrode contact hole 125 is formed in which an interlayer insulating film 123 is formed on a semiconductor substrate 121 where a cell region and a fuse region are intended, and exposes the semiconductor substrate 121 using a storage electrode contact mask. To form.

A storage electrode contact plug 127 is formed to fill the storage electrode contact hole 125.

In this case, a process of forming the storage electrode contact plug 127 on the semiconductor substrate 121 will be described in more detail as follows.

First, an isolation layer is formed on the semiconductor substrate 121 where the cell region and the fuse region are intended, and a recess gate is formed in the gate intended region.

The lower insulating layer is formed on the entire surface, and the lower insulating layer is etched by a photolithography process using a landing plug contact mask to expose the semiconductor substrate 121 of the bit line contact region and the storage electrode contact region. To form.

Then, after forming a landing plug to fill the landing plug contact hole, a first interlayer insulating film is formed over the entire surface.

Next, the first interlayer insulating layer is etched by a photolithography process using a bit line contact mask to form a bit line contact hole.

Next, a conductive film is embedded in the bit line contact hole to form a bit line contact plug.

Next, a bit line is formed on the bit line contact plug, and a second interlayer insulating film covering the bit line is formed.

Next, the second interlayer insulating layer and the first interlayer insulating layer of the cell region are etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole.

Next, the conductive electrode is buried in the storage electrode contact hole to form the storage electrode contact plug 127.

Next, an etch stop layer 129 is formed on the interlayer insulating layer 123. In this case, the etch stop film 129 is formed of a nitride film.

Next, the first sacrificial oxide layer 131, the second sacrificial oxide layer 133, the hard mask layer 135, and the anti-reflection layer 137 are sequentially formed on the etch stop layer 129.

Next, a first photoresist film (not shown) is formed on the anti-reflection film 137, and the first photoresist film is exposed and developed with a storage electrode mask (not shown) to define the storage electrode area in the cell area. 1 Photosensitive film pattern 139 is formed.

Referring to FIG. 3B, the anti-reflection film 137, the hard mask layer 135, the second sacrificial oxide film 133, the first sacrificial oxide film 131, and the etch stop film 129 using the first photoresist pattern 139 as a mask. ) Is etched to form the storage electrode region 141.

Next, the first photoresist film pattern 139, the antireflection film 137, and the hard mask layer 135 are removed.

Referring to FIG. 3C, a second photoresist layer (not shown) is formed on the entire surface, and the second photoresist layer is exposed and developed with a storage electrode mask (not shown) for a fuse region to form a second photoresist pattern 143. do.

Referring to FIG. 3D, the second sacrificial oxide layer 133, the first sacrificial oxide layer 131, and the etch stop layer 129 are etched using the second photoresist layer pattern 143 as a mask to form a dummy storage electrode region 145. do.

The second photoresist pattern 143 is removed.

In the process of forming the storage electrode region 141 and the dummy storage electrode region 145 of FIGS. 3C and 3D, the photoresist is coated on the second sacrificial oxide layer 133 and subjected to a first exposure using a storage electrode mask. And performing a second exposure process using the storage electrode mask for the fuse region, and forming a photoresist pattern in the cell region and the fuse region as a developing process, using the anti-reflection film 137, the hard mask layer 135, and the second sacrificial layer as a mask. The oxide layer 133, the first sacrificial oxide layer 131, and the etch stop layer 129 may be etched to form the storage electrode region 141 and the dummy storage electrode region 145.

In this case, the photoresist pattern is formed in a combination of the first photoresist pattern 139 and the second photoresist pattern 143.

Referring to FIG. 3E, when the storage electrode region 141 and the dummy storage electrode region 145 are formed using the photoresist pattern in which the first photoresist pattern 139 and the second photoresist pattern 143 are combined as a mask, The anti-reflection film 137 and the hard mask layer 135 formed on the second sacrificial oxide film 133 are removed.

Next, a conductive film 147 is formed over the entire surface including the storage electrode region and the dummy storage electrode regions 141 and 145.

In this case, the conductive film 147 may be formed in a stacked structure of a titanium (Ti) film and a titanium nitride (TiN) film.

Referring to FIG. 3F, a third photosensitive film (not shown) is formed on the entire surface.

The planarization process is performed until the second sacrificial oxide film 133 is exposed. In this case, a third photoresist layer remains in the storage electrode region and the dummy storage electrode regions 141 and 145.

Next, the third photoresist layer in the storage electrode region and the dummy storage electrode regions 141 and 145 is removed to store the storage electrode 148 in the storage electrode region 141 of the cell region and the dummy storage electrode region 145 of the fuse region, respectively. To form.

In this case, the storage electrode 148 formed in the dummy storage electrode region 145 of the fuse region is preferably a dummy storage electrode.

A capping oxide film 149 is then formed over the entire surface to fill the storage electrode region and the dummy storage electrode regions 141 and 145.

Referring to FIG. 3G, the capping oxide layer 149, the second sacrificial oxide layer 133, and the first sacrificial oxide layer 131 are removed by performing a full dip-out process using a chemical solution. do.

Next, a dielectric film 151 is formed over the storage electrode 148.

Referring to FIG. 3H, a titanium nitride (TiN) film 153a and a polysilicon film 153b are sequentially stacked on the dielectric film 151 to form a plate electrode 153 to form capacitor and fuse regions of a cell region. A dummy capacitor 161 of FIG. 4 is formed.

In this case, the plate electrode 153 in the fuse region is preferably used as a fuse.

Subsequently, a fourth interlayer insulating film (not shown), a first contact plug for metal wiring (not shown), a first metal wiring (not shown), a fifth interlayer insulating film (not shown), and a second layer are disposed on the plate electrode 153. A contact plug (not shown), a second metal wiring (not shown), and a protective film (not shown) for metal wiring are formed.

Next, a fuse open region is formed by a photolithography process using a fuse open mask (not shown) to leave the fourth interlayer insulating layer having a predetermined thickness on the plate electrode 153 of the fuse region.

Next, a fuse blowing process of cutting the plate electrode 153 in the fuse area corresponding to the cell in which the failure occurs with a laser is performed.

4 is a plan view showing a semiconductor device according to the present invention.

Referring to FIG. 4, it can be seen that the dummy capacitor 161 is formed on the semiconductor substrate 121 in the fuse region.

Accordingly, the thickness of the fourth interlayer insulating layer to be removed when forming the fuse open region 163 may be reduced compared to the conventional art, and thus the fourth interlayer insulating layer may be left on the plate electrode 153 in the fuse region by the target thickness.

As described above, in the method of manufacturing a semiconductor device according to the present invention, a dummy capacitor is formed in the fuse region to remove a step between the cell region and the plate electrode 153 formed in the fuse region, thereby forming an upper portion of the plate electrode 153 in the fuse region. The thickness of the fourth interlayer insulating film to be formed can be made thinner than conventional.

Accordingly, the fourth interlayer insulating film may be left on the plate electrode 153 of the fuse region by the target thickness during the fuse open region forming process.

In the method of fabricating a semiconductor device according to the present invention, a dummy capacitor is formed in a fuse region to remove a step between a cell region and a plate electrode of a fuse region, thereby forming an insulating film having a predetermined thickness on the plate electrode of the fuse region during the etching process for opening the fuse. It is possible to leave and to prevent the fuse failure due to the subsequent laser blowing (blowing).

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (12)

Forming an insulating layer on the semiconductor substrate; Forming a storage electrode region of the cell region by a photolithography process using a first storage electrode mask, and forming a dummy storage electrode region in the fuse region by a photolithography process using a second storage electrode mask; Forming a storage electrode in the cell region and forming a dummy storage electrode in the fuse region; Removing the insulating layer by performing a full dip-out process; And Sequentially forming a dielectric film and a plate electrode in front of the storage electrode and the dummy storage electrode; Method of manufacturing a semiconductor device comprising a. 2. The method of claim 1, further comprising forming an interlayer insulating film between the semiconductor substrate and the insulating layer. The method of claim 1, further comprising forming an etch stop layer between the semiconductor substrate and the insulating layer. The method of claim 1, wherein the insulating layer has a stacked structure of a first sacrificial oxide film and a second sacrificial oxide film. The method of claim 1, further comprising sequentially forming a hard mask layer and an anti-reflection film on the insulating layer. delete The method of claim 1, wherein the forming of the storage electrode region and the dummy storage electrode region is performed. Applying a first photosensitive film on the insulating layer; Exposing the first photoresist film by using the first storage electrode mask; Developing the first photoresist film to form a first photoresist pattern; Etching the insulating layer using the first photoresist pattern as a mask to form a storage electrode region; Applying a second photoresist film on the insulating layer; Exposing the second photoresist layer by using the second storage electrode mask; Developing the second photoresist film to form a second photoresist pattern; Etching the insulating layer with the second photoresist pattern as a mask to form a dummy storage electrode region Method of manufacturing a semiconductor device, characterized in that it further comprises. The method of claim 1, wherein the forming of the storage electrode region and the dummy storage electrode region is performed. Applying a photoresist film on the insulating layer; Exposing the photoresist using the first storage electrode mask; Exposing the photoresist using the second storage electrode mask; Developing the photoresist to form a photoresist pattern; Etching the insulating layer using the photoresist pattern as a mask to form a storage electrode region and a dummy storage electrode; Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the storage electrode and the dummy storage electrode have a stacked structure of a titanium (Ti) film and a titanium nitride (TiN) film. The method of claim 1, further comprising forming a capping oxide layer over an entire surface after the forming of the storage electrode and the dummy storage electrode. The method of claim 10, wherein the capping oxide layer is removed during the full dip-out process. The method of claim 1, wherein the plate electrode is formed in a stacked structure of a titanium nitride (TiN) film and a polysilicon film.

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