KR20010077761A - A method of fabricating a semiconductor - Google Patents

A method of fabricating a semiconductor Download PDF

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Publication number
KR20010077761A
KR20010077761A KR1020000005795A KR20000005795A KR20010077761A KR 20010077761 A KR20010077761 A KR 20010077761A KR 1020000005795 A KR1020000005795 A KR 1020000005795A KR 20000005795 A KR20000005795 A KR 20000005795A KR 20010077761 A KR20010077761 A KR 20010077761A
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South Korea
Prior art keywords
film
forming
semiconductor substrate
insulating film
insulating
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KR1020000005795A
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Korean (ko)
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박제민
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윤종용
삼성전자 주식회사
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Priority to KR1020000005795A priority Critical patent/KR20010077761A/en
Publication of KR20010077761A publication Critical patent/KR20010077761A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Abstract

PURPOSE: A method for manufacturing a semiconductor is provided to increase a processing margin in the succeeding metal contact process by decreasing a step coverage between a cell array region and a core/periphery surrounding. CONSTITUTION: The first insulating film(206) including a gate pattern(202) and a bit line(204) is formed on a semiconductor substrate(200) comprising a cell array region(A) and a core/periphery region(B). A photoresist film is formed on the first insulating film(206). By patterning the photoresist film, a photoresist pattern is formed to expose the cell array region(A). The first insulating film(206) is etched by using the photoresist pattern as a mask. The photoresist pattern is removed. The second insulating film(210) is formed on the substrate(200). A contact plug(212) is formed in the second and the first insulating film(210, 206). A capacitor is formed on the contact plug(212). A flattening film is formed on the substrate.

Description

반도체 제조 방법{A METHOD OF FABRICATING A SEMICONDUCTOR}Semiconductor manufacturing method {A METHOD OF FABRICATING A SEMICONDUCTOR}

본 발명은 반도체에 관한 것으로써, 좀 더 구체적으로 반도체 제조 방법에 관한 것이다.The present invention relates to a semiconductor and, more particularly, to a semiconductor manufacturing method.

반도체가 점점 고집적화 되어 가면서 반도체 소자의 크기가 점점 작아지고있다. 디램(DRAM)에 있어서, 메모리 용량이 고용량화 되어 가면서 단위 면적 내에 형성되는 셀의 개수가 증가되고 있다. 이것은 반대로 단위 셀이 차지하는 면적이 감소하고 있다는 것을 의미한다. 이러한 셀 면적 감소는 커패시터의 전극 표면적 감소를 초래하여 디램 동작에 필요한 최소 정전용량(capacitance)인 25fF을 확보하기가 점점 어려워지고 있다. 스택형 커패시터 중 하나인 실린더형 커패시터 형성시 상기와 같은 문제점을 해결하기 위해 스토리지 전극을 높게 형성한다. 그러나, 스토리지 전극이 높아지면서 셀 어레이 영역과 코아/주변 영역간의 단차가 극심해져 새로운 문제점을 초래하고 있다.As semiconductors are becoming increasingly integrated, the size of semiconductor devices is becoming smaller. In DRAM, as the memory capacity becomes higher, the number of cells formed in the unit area is increasing. This in turn means that the area occupied by the unit cell is decreasing. This reduction in cell area leads to a reduction in the electrode surface area of the capacitor, making it increasingly difficult to obtain 25 fF, the minimum capacitance required for DRAM operation. In order to solve the above problems when forming a cylindrical capacitor, which is one of the stacked capacitors, the storage electrode is formed high. However, as the storage electrode increases, the step difference between the cell array region and the core / peripheral region is severe, which causes new problems.

도 1은 종래의 반도체 제조시 발생되는 문제점을 보여주는 단면도이다.1 is a cross-sectional view showing a problem occurring in the conventional semiconductor manufacturing.

도 1을 참조하면, 셀 어레이 영역(A)과 코아/주변 영역(B)으로 정의된 반도체 기판(100) 상에 게이트 패턴(102)을 형성한다. 상기 게이트 패턴(102)을 포함하여 상기 반도체 기판(100) 전면에 제 1 절연막(106)을 형성한다. 상기 제 1 절연막(106)은 비트라인(bit line; 104)을 내포한다. 상기 제 1 절연막(106) 상에 제 2 절연막(108)을 형성한 후 상기 제 2 절연막(108)과 제 1 절연막(106) 내에 콘택 플러그(110)를 형성한다. 상기 콘택 플러그(110)를 포함하여 상기 제 2 절연막(108) 상에 식각 저지막(112)을 형성한다. 이 분야에서 잘 알려진 공정을 통해 상기 콘택 플러그(110) 상에 커패시터의 스토리지 전극(114)을 형성한다. 상기 반도체 기판(100) 전면에 유전체막(116)과 플레이트 전극(118)을 차례로 형성한다. 상기 제 1 절연막(106)이 노출될 때까지 상기 코아/주변 영역(B)의 상기 플레이트 전극, 유전체막, 식각 저지막 및 제 2 절연막(118, 116, 112, 108)을 차례로식각한다. 상기 반도체 기판(108) 전면에 제 3 절연막(120)을 형성한다. 이 때, 상기 스토리지 전극(114)의 높이가 상기 제 1 절연막(106)의 높이보다 훨씬 높기 때문에 도 1에 도시된 바와 같이, 상기 셀 어레이 영역(A)과 상기 코아/주변 영역(B)간에 단차(H1)가 크게 생긴다. 이러한 단차(H1)로 인하여 후속 금속 콘택 공정시 DOF(Depth Of Focus) 마진이 부족하여 정확한 노광을 할 수가 없게 된다. 즉, 셀 어레이 영역(A)과 코아/주변 영역(B)에 금속 콘택홀을 형성하기 위해 동시에 노광을 할 때 일 영역에 초점을 맞추면 다른 영역은 초점이 안 맞게 된다. 이러한, 상태에서 패터닝을 하면 깨끗한 패턴이 형성되지 못한다.Referring to FIG. 1, a gate pattern 102 is formed on a semiconductor substrate 100 defined by a cell array region A and a core / peripheral region B. Referring to FIG. The first insulating layer 106 is formed on the entire surface of the semiconductor substrate 100 including the gate pattern 102. The first insulating layer 106 includes a bit line 104. After the second insulating film 108 is formed on the first insulating film 106, the contact plug 110 is formed in the second insulating film 108 and the first insulating film 106. An etch stop layer 112 is formed on the second insulating layer 108 including the contact plug 110. The storage electrode 114 of the capacitor is formed on the contact plug 110 through a process well known in the art. The dielectric film 116 and the plate electrode 118 are sequentially formed on the entire surface of the semiconductor substrate 100. The plate electrode, the dielectric film, the etch stop film, and the second insulating films 118, 116, 112, and 108 in the core / peripheral region B are sequentially etched until the first insulating film 106 is exposed. The third insulating layer 120 is formed on the entire surface of the semiconductor substrate 108. At this time, since the height of the storage electrode 114 is much higher than the height of the first insulating layer 106, as shown in Figure 1, between the cell array region (A) and the core / peripheral region (B) Step H1 is large. Due to such a step H1, the depth of focus (DOF) margin is insufficient in the subsequent metal contact process, so that accurate exposure cannot be performed. That is, when focusing on one area when simultaneously exposing to form a metal contact hole in the cell array area A and the core / peripheral area B, the other area becomes out of focus. Patterning in such a state does not form a clean pattern.

본 발명의 목적은 커패시터 형성시 셀 영역과 코아/주변 영역간의 단차를 감소시키기 위한 반도체 제조 방법을 제공하는 것이다.It is an object of the present invention to provide a semiconductor manufacturing method for reducing the step difference between a cell region and a core / peripheral region in forming a capacitor.

도 1은 종래의 반도체 제조시 셀 어레이 영역과 코아/주변 영역간에 발생되는 단차를 보여주는 단면도; 및1 is a cross-sectional view showing a step generated between a cell array region and a core / peripheral region in the conventional semiconductor manufacturing; And

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 제조 방법을 순차적으로 보여주는 단면도이다.2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

200 : 반도체 기판 202 게이트 패턴200: semiconductor substrate 202 gate pattern

204 : 비트라인 206 : 제 1 절연막204: bit line 206: first insulating film

212 : 콘택 플러그 214 : 식각 저지막212: contact plug 214: etch stop film

216 : 스토리지 전극 218 : 유전체막216 storage electrode 218 dielectric film

220 : 플레이트 전극 222 : 제 5 절연막220 plate electrode 222 fifth insulating film

상술한 목적을 달성하기 위한 본 발명에 의하면, 셀 어레이 영역과 코아/주변 영역으로 정의된 반도체 기판에 있어서, 상기 반도체 제조 방법은 반도체 기판 상에 게이트 패턴과 비트라인을 내포하는 제 1 절연막을 형성한다. 상기 제 1 절연막 상에 포토레지스트막을 형성한다. 사진 공정을 통해 상기 셀 어레이 영역이 노출되도록 상기 포토레지스트막을 패터닝하여 포토레지스트 패턴을 형성한다. 상기 포토레지스트 패턴을 식각 마스크로 사용하여 상기 제 1 절연막을 소정 두께 식각한다. 상기 포토레지스트 패턴을 제거한다. 상기 반도체 기판 상에 제 2 절연막을 형성한다. 상기 제 2, 제 1 절연막 내에 콘택 플러그를 형성한다. 상기 콘택 플러그 상에 커패시터를 형성한다. 상기 반도체 기판 전면에 평탄화막을 형성한다.According to the present invention for achieving the above object, in the semiconductor substrate defined by the cell array region and the core / peripheral region, the semiconductor manufacturing method forms a first insulating film containing a gate pattern and a bit line on the semiconductor substrate do. A photoresist film is formed on the first insulating film. The photoresist layer is patterned to expose the cell array region through a photolithography process to form a photoresist pattern. The first insulating layer is etched by a predetermined thickness using the photoresist pattern as an etching mask. The photoresist pattern is removed. A second insulating film is formed on the semiconductor substrate. Contact plugs are formed in the second and first insulating films. A capacitor is formed on the contact plug. A planarization film is formed on the entire surface of the semiconductor substrate.

(실시예)(Example)

도 2a 내지 도 2e를 참조하여 본 발명의 실시예에 따른 반도체 제조 방법을 상세히 설명한다.A semiconductor manufacturing method according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2A through 2E.

본 발명의 신규한 반도체 제조 방법은 비트라인 형성 후 형성되는 층간 절연막의 셀 영역을 소정 두께 식각하여 코아/주변 영역보다 낮게 만든다.The novel semiconductor manufacturing method of the present invention etches the cell region of the interlayer insulating film formed after the bit line is formed to a predetermined thickness to lower the core / peripheral region.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 제조 방법을 순차적으로 보여주는 단면도이다.2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor according to an embodiment of the present invention.

도 2a를 참조하면, 셀 어레이 영역(cell array region; A)과 코아/주변 영역(core/periphery region; B)으로 정의된 반도체 기판(200) 상에 게이트 패턴(202)을 형성한다. 상기 게이트 패턴(202)을 포함하여 상기 반도체 기판(200) 상에 제 1 절연막(206)을 형성한다. 상기 제 1 절연막(206)은 화학기상증착(CVD:Chemical Vapor Deposition) 방식에 의한 BPSG(Boro-Phosphoru Silicate Glass) 또는 USG(Undoped Silicate Glass)를 사용하여 형성한다. 상기 제 1 절연막(206)은 비트라인(204)을 내포한다. 상기 비트라인(204)은 상기 게이트 패턴(202)들 사이에 위치한다. 상기 제 1 절연막(206) 상에 포토레지스트막을 형성한다. 사진 공정을 통해 상기 포토레지스트막을 패터닝하되 상기 셀 어레이 영역(A)만 노출되도록 포토레지스트 패턴(208)을 형성한다. 상기 포토레지스트 패턴(208)을 식각 마스크로 사용하여 상기 셀 어레이 영역(A)의 상기 제 1절연막(206)을 소정 두께 식각한다. 상기 제 1 절연막(206) 식각은 산화막 식각액인 HF 또는 BOE(HF+NH4F)를 사용하여 등방성(isotropy) 습식 식각한다. 도 2a에서 보는 바와 같이, 상기 포토레지스트 패턴(208) 아래가 언더컷(undercut)되어 상기 셀 어레이 영역(A)과 상기 코아/주변 영역(B)간의 단차 부위가 급경사가 아닌 완만한 경사로 형성된다. 상기 단차 부위가 수직에 가까운 급경사로 형성되면 후속 콘택 플러그 형성시 도전 잔유물이 상기 단차 부위에 남아 결함 요인으로 작용할 소지가 있다. 이를 방지하기 위하여 상기 단차 부위를 완만하게 형성하는 것이다. 상기 제 1 절연막(206) 식각 공정을 습식 식각이 아닌 건식 식각(dry etch)을 사용하여 수행할 수도 있다.Referring to FIG. 2A, a gate pattern 202 is formed on a semiconductor substrate 200 defined by a cell array region A and a core / periphery region B. Referring to FIG. The first insulating layer 206 is formed on the semiconductor substrate 200 including the gate pattern 202. The first insulating layer 206 is formed using BPSG (Boro-Phosphoru Silicate Glass) or USG (Undoped Silicate Glass) by chemical vapor deposition (CVD). The first insulating layer 206 includes a bit line 204. The bit line 204 is positioned between the gate patterns 202. A photoresist film is formed on the first insulating film 206. The photoresist layer is patterned through a photolithography process, and the photoresist pattern 208 is formed to expose only the cell array region A. FIG. The first insulating layer 206 of the cell array region A is etched by a predetermined thickness using the photoresist pattern 208 as an etching mask. The first insulating layer 206 is etched by isotropy wet etching using HF or BOE (HF + NH4F), which is an oxide film etching solution. As shown in FIG. 2A, the lower portion of the photoresist pattern 208 is undercut to form a stepped portion between the cell array region A and the core / peripheral region B with a gentle slope rather than a steep slope. If the stepped portion is formed with a steep slope close to the vertical, conductive residue may remain in the stepped portion to act as a defect factor when forming a subsequent contact plug. In order to prevent this, the step portion is gently formed. The etching process of the first insulating layer 206 may be performed using dry etching rather than wet etching.

도 2b를 참조하면, 상기 제 1 절연막(206) 상에 제 2 절연막(210)을 형성한다. 상기 제 2 절연막(210)은 예를 들면, PE-산화막으로서 후속 식각 공정시 하부 막질을 보호하기 위한 보호막으로서 작용한다. 상기 반도체 기판(200) 상부가 노출될 때까지 상기 제 2 절연막(210)과 제 1 절연막(206)을 식각하여 콘택홀을 형성한다. 상기 콘택홀을 채우도록 상기 반도체 기판(200) 전면에 제 1 도전막을 형성한다. 상기 제 2 절연막(210)이 노출되도록 상기 제 1 도전막을 식각하여 상기 제 2 절연막(210)과 제 1 절연막(206) 내에 스토리지 전극용 콘택 플러그(212)를 형성한다. 상기 콘택 플러그(212)를 포함하여 상기 제 2 절연막(210) 상에 식각 저지막(214)을 형성한다. 상기 식각 저지막(214)은 실리콘 질화막 또는 실리콘옥시나이트라이드를 사용하여 형성한다.Referring to FIG. 2B, a second insulating film 210 is formed on the first insulating film 206. The second insulating film 210 is, for example, a PE-oxide film and functions as a protective film for protecting the lower film quality in a subsequent etching process. The second insulating layer 210 and the first insulating layer 206 are etched to form contact holes until the upper portion of the semiconductor substrate 200 is exposed. A first conductive layer is formed on the entire surface of the semiconductor substrate 200 to fill the contact hole. The first conductive layer is etched to expose the second insulating layer 210 to form contact plugs 212 for storage electrodes in the second insulating layer 210 and the first insulating layer 206. An etch stop layer 214 is formed on the second insulating layer 210 including the contact plug 212. The etch stop layer 214 is formed using a silicon nitride film or silicon oxynitride.

도 2c를 참조하면, 상기 식각 저지막(214) 상에 제 3 절연막(216)을 약12000Å 내지 15000Å 두께 범위로 형성한다. 상기 제 3 절연막(216)은 화학기상증착(CVD) 방식에 의한 USG를 사용하여 형성한다. 상기 제 3 절연막(216)의 두께가 후속 스토리지 전극의 높이를 결정한다. 상기 콘택 플러그(212)가 노출되도록 상기 제 3 절연막(216)과 상기 식각 저지막(214)을 패터닝하여 개구부(218)를 형성한다. 이 때, 상기 제 2 절연막(210)을 더 식각하여 상기 콘택 플러그(212)가 충분히 노출되도록 한다.Referring to FIG. 2C, a third insulating layer 216 is formed on the etch stop layer 214 in a thickness range of about 12000 μm to 15000 μm. The third insulating layer 216 is formed using USG by chemical vapor deposition (CVD). The thickness of the third insulating layer 216 determines the height of the subsequent storage electrode. The opening 218 is formed by patterning the third insulating layer 216 and the etch stop layer 214 so that the contact plug 212 is exposed. At this time, the second insulating layer 210 is further etched to expose the contact plug 212 sufficiently.

도 2d를 참조하면, 제 2 도전막을 상기 개구부(218) 내벽을 포함하여 상기 반도체 기판(200) 전면에 콘포말(conformal)하게 형성한다. 상기 개구부(218)가 채워지도록 상기 제 2 도전막 상에 제 4 절연막(도면에 미도시)을 형성한다. 상기 제 3 절연막(216)이 노출될 때까지 상기 제 4 절연막과 제 2 도전막을 평탄화 식각한다. 이 때, 상기 제 2 도전막이 셀 단위로 분리되어 스토리지 전극(216)이 된다. 상기 스토리지 전극(216)이 드러나도록 상기 식각 저지막(214)이 노출될 때까지 상기 제 4 절연막의 잔유물과 상기 제 3 절연막(216)을 제거한다. 상기 반도체 기판(200) 전면에 유전체막(218)을 콘포말하게 형성한다. 상기 유전체막(218) 상에 플레이트 전극(220)을 형성한다.Referring to FIG. 2D, a second conductive layer is formed conformally on the entire surface of the semiconductor substrate 200 including the inner wall of the opening 218. A fourth insulating film (not shown) is formed on the second conductive film to fill the opening 218. The fourth insulating film and the second conductive film are planarized and etched until the third insulating film 216 is exposed. In this case, the second conductive layer is separated into cells to form the storage electrode 216. The residue of the fourth insulating layer and the third insulating layer 216 are removed until the etch stop layer 214 is exposed so that the storage electrode 216 is exposed. A dielectric film 218 is conformally formed over the semiconductor substrate 200. The plate electrode 220 is formed on the dielectric film 218.

도 2e를 참조하면, 사진 식각 공정을 통해 상기 코아/주변 영역(B)의 상기 제 1 절연막(206)이 노출되도록 상기 코아/주변 영역(B)의 상기 플레이트 전극, 유전체막 식각 저지막 및 제 2 절연막(220, 218, 214, 210)을 패터닝하여 제거한다. 상기 반도체 기판(200) 전면에 제 5 절연막(222)을 형성한다. 상기 제 5 절연막(222)은 평탄화막질로서 화학기상증착(CVD) 방식에 의한 BPSG막으로 형성한다. 도 2e에서 보는 바와 같이, 상기 코아/주변 영역(B)의 상기 제 1 절연막(206)이 상기 셀 어레이 영역(A)의 상기 제 1 절연막(206)보다 높게 형성되어 있기 때문에 상기 제 5 절연막(222)을 형성하더라도 상기 셀 어레이 영역(A)과 상기 코아/주변 영역(B)간의 단차(H2)가 종래의 경우에 발생하던 단차(H1)보다 감소된다. 따라서, 후속 공정인 금속 콘택 공정시 DOF(Depth Of Focus) 마진과 얼라인 마진(align margin)이 확보된다.Referring to FIG. 2E, the plate electrode, the dielectric layer etch stop layer, and the first layer of the core / peripheral region B are exposed to expose the first insulating layer 206 of the core / peripheral region B through a photolithography process. 2 The insulating films 220, 218, 214, and 210 are patterned and removed. The fifth insulating layer 222 is formed on the entire surface of the semiconductor substrate 200. The fifth insulating film 222 is formed as a planarization film and formed of a BPSG film by chemical vapor deposition (CVD). As shown in FIG. 2E, since the first insulating film 206 of the core / peripheral region B is formed higher than the first insulating film 206 of the cell array region A, the fifth insulating film ( Even if 222 is formed, the step H2 between the cell array area A and the core / peripheral area B is reduced than the step H1 that occurs in the conventional case. Therefore, a DOF (of depth of focus) margin and an alignment margin are secured in a subsequent metal contact process.

본 발명은 셀 어레이 영역과 코아/주변 영역간의 단차를 감소시킴으로써 후속 금속 콘택 공정시 공정 마진을 증대시키는 효과를 얻을 수 있다.The present invention can achieve the effect of increasing the process margin in subsequent metal contact processes by reducing the step between the cell array region and the core / peripheral region.

Claims (3)

셀 어레이 영역과 코아/주변 영역으로 정의된 반도체 기판에 있어서,A semiconductor substrate defined by a cell array region and a core / peripheral region, 상기 반도체 기판 상에 게이트 패턴과 비트라인을 내포하는 제 1 절연막을 형성하는 단계;Forming a first insulating film including a gate pattern and a bit line on the semiconductor substrate; 상기 제 1 절연막 상에 포토레지스트막을 형성하는 단계;Forming a photoresist film on the first insulating film; 사진 공정을 통해 상기 셀 어레이 영역이 노출되도록 상기 포토레지스트막을 패터닝하여 포토레지스트 패턴을 형성하는 단계;Patterning the photoresist film to expose the cell array region through a photolithography process to form a photoresist pattern; 상기 포토레지스트 패턴을 식각 마스크로 사용하여 상기 제 1 절연막을 소정 두께 식각하는 단계;Etching the first insulating layer by a predetermined thickness using the photoresist pattern as an etching mask; 상기 포토레지스트 패턴을 제거하는 단계;Removing the photoresist pattern; 상기 반도체 기판 상에 제 2 절연막을 형성하는 단계;Forming a second insulating film on the semiconductor substrate; 상기 제 2, 제 1 절연막 내에 콘택 플러그를 형성하는 단계;Forming a contact plug in the second and first insulating layers; 상기 콘택 플러그 상에 커패시터를 형성하는 단계; 및Forming a capacitor on the contact plug; And 상기 반도체 기판 전면에 평탄화막을 형성하는 단계를 포함하는 반도체 제조 방법.Forming a planarization film on the entire surface of the semiconductor substrate. 제 1 항에 있어서,The method of claim 1, 상기 커패시터를 형성하는 단계는,Forming the capacitor, 상기 반도체 기판 상에 식각 저지막과 희생 절연막을 차례로 형성하는 단계;Sequentially forming an etch stop layer and a sacrificial insulating layer on the semiconductor substrate; 상기 콘택 플러그가 노출되도록 상기 희생산화막과 식각 저지막을 패터닝하여 개구부를 형성하는 단계;Patterning the sacrificial oxide layer and an etch stop layer to expose the contact plug to form an opening; 상기 개구부 내벽에 스토리지 전극을 형성하는 단계;Forming a storage electrode on an inner wall of the opening; 상기 희생 산화막을 제거하는 단계;Removing the sacrificial oxide film; 상기 반도체 기판 전면에 유전체막과 플레이트 전극을 형성하는 단계;Forming a dielectric film and a plate electrode on the entire surface of the semiconductor substrate; 상기 코아/주변 영역의 상기 플레이트 전극, 유전체막, 식각 저지막 및 제 2 절연막을 식각하는 단계를 포함하는 반도체 제조 방법.Etching the plate electrode, the dielectric layer, the etch stop layer, and the second insulating layer in the core / peripheral region. 제 1 항에 있어서,The method of claim 1, 상기 평탄화막은 BPSG막인 것을 특징으로 하는 반도체 제조 방법.The planarization film is a semiconductor manufacturing method, characterized in that the BPSG film.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7598180B2 (en) 2003-03-24 2009-10-06 Samsung Electronics Co., Ltd. Semiconductor process for removing defects due to edge chips of a semiconductor wafer and semiconductor device fabricated thereby
KR101034598B1 (en) * 2003-12-30 2011-05-12 주식회사 하이닉스반도체 Method for forming landing plug contact in semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7598180B2 (en) 2003-03-24 2009-10-06 Samsung Electronics Co., Ltd. Semiconductor process for removing defects due to edge chips of a semiconductor wafer and semiconductor device fabricated thereby
KR100958702B1 (en) * 2003-03-24 2010-05-18 삼성전자주식회사 semiconductor process for removing defects due to edge chips of a semiconductor wafer
KR101034598B1 (en) * 2003-12-30 2011-05-12 주식회사 하이닉스반도체 Method for forming landing plug contact in semiconductor device

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