TWI449085B - Process for semiconductor device - Google Patents
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Description
本發明是有關於一種積體電路的製程方法，且特別是有關於一種半導體元件的製程方法。The present invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a semiconductor device.
離子植入製程是一種經常使用於半導體元件製程中用來形成各種摻雜區的方法。典型的離子植入製程是透過具有開口圖案的單一層的光阻層來做為植入罩幕。然而，隨著元件不斷地小型化，對於高低起伏落差較大的表面來說，所欲形成的開口圖案的高寬比(aspect ratio)過高，製程的裕度空間(process window)非常小，時有曝光製程的景深不足，以致顯影之後有光阻層破裂或殘留，所形成的開口圖案無法得到所需的輪廓，而導致所形成的摻雜區輪廓或位置不正確，甚至有無法形成開口圖案的情形。The ion implantation process is a method often used in the fabrication of semiconductor devices to form various doped regions. A typical ion implantation process uses a single layer of photoresist layer with an open pattern as an implant mask. However, as the components are continuously miniaturized, the aspect ratio of the opening pattern to be formed is too high for a surface having a large undulation drop, and the process window is very small. The depth of field of the exposure process is insufficient, so that the photoresist layer is broken or left after development, and the formed opening pattern cannot obtain the desired contour, resulting in an incorrect contour or position of the formed doping region, and even an opening cannot be formed. The situation of the pattern.
本發明提供一種半導體元件的製程方法，可以形成具有所需輪廓的離子植入罩幕，以將離子植入於正確的區域以形成摻雜區。The present invention provides a method of fabricating a semiconductor device that can form an ion implantation mask having a desired profile to implant ions in the correct regions to form doped regions.
本發明提出一種半導體元件的製程方法，包括在高低起伏表面上形成平坦層。接著，在平坦層上形成硬罩幕層，然後，在硬罩幕層上形成光阻層。硬罩幕層與平坦層之材質不同，且與光阻層之材質不同。之後，對光阻層進行曝光顯影製程，使光阻層圖案化，形成第一開口，裸露出硬罩幕層。然後，蝕刻移除第一開口所裸露的硬罩幕層與其下方的平坦層，以形成第二開口。繼之，以硬罩幕層與平坦層做為植入罩幕，進行離子植入製程，以於第二開口底部的高低起伏表面其下方的基底中形成摻雜區。然後，移除硬罩幕層，再移除平坦層，裸露出高低起伏表面。The present invention provides a method of fabricating a semiconductor device comprising forming a planar layer on a high and low relief surface. Next, a hard mask layer is formed on the flat layer, and then a photoresist layer is formed on the hard mask layer. The material of the hard mask layer is different from that of the flat layer, and is different from the material of the photoresist layer. Thereafter, the photoresist layer is subjected to an exposure and development process to pattern the photoresist layer to form a first opening, and the hard mask layer is exposed. Then, the hard mask layer exposed by the first opening and the flat layer under the first opening are removed by etching to form a second opening. Then, the hard mask layer and the flat layer are used as an implant mask to perform an ion implantation process to form a doped region in the substrate below the high and low relief surface at the bottom of the second opening. Then, remove the hard mask layer, then remove the flat layer to expose the high and low undulating surface.
依照本發明一實施例所述，上述平坦層與上述光阻層之材質相同。According to an embodiment of the invention, the flat layer is the same material as the photoresist layer.
依照本發明一實施例所述，上述平坦層與上述光阻層之材質不相同。According to an embodiment of the invention, the flat layer and the material of the photoresist layer are different.
依照本發明一實施例所述，上述平坦層與上述光阻層之材質各自包括有機材料、無機材料或聚合物材料。According to an embodiment of the invention, the material of the flat layer and the photoresist layer respectively comprise an organic material, an inorganic material or a polymer material.
依照本發明一實施例所述，上述平坦層與上述光阻層之材質各自包括感光材料。According to an embodiment of the invention, the material of the flat layer and the photoresist layer each comprise a photosensitive material.
依照本發明一實施例所述，上述平坦層之材質包括不感光材料。According to an embodiment of the invention, the material of the flat layer comprises a non-photosensitive material.
依照本發明一實施例所述，上述硬罩幕層之材質包括不感光材料。According to an embodiment of the invention, the material of the hard mask layer comprises a non-photosensitive material.
依照本發明一實施例所述，上述硬罩幕層對上述平坦層的蝕刻選擇比為6至10。According to an embodiment of the invention, the hard mask layer has an etching selectivity ratio of 6 to 10 to the flat layer.
依照本發明一實施例所述，上述平坦層與上述光阻層之材質包括富碳型光阻；上述硬罩幕層之材質包括富矽型光阻。According to an embodiment of the invention, the material of the flat layer and the photoresist layer comprises a carbon-rich photoresist; and the material of the hard mask layer comprises a germanium-rich photoresist.
依照本發明一實施例所述，上述平坦層、上述硬罩幕層以及上述光阻層之厚度分別為500nm至550nm、25nm至35nm與150nm至200 nm。According to an embodiment of the invention, the flat layer, the hard mask layer, and the photoresist layer have thicknesses of 500 nm to 550 nm, 25 nm to 35 nm, and 150 nm to 200 nm, respectively.
依照本發明一實施例所述，上述半導體元件的製程方法更包括在進行上述離子植入製程之後，在移除上述硬罩幕層之前，於上述第二開口之中填入保護層，且在移除上述硬罩幕層之後，移除上述保護層。According to an embodiment of the present invention, the method for fabricating the semiconductor device further includes: after performing the ion implantation process, filling a protective layer in the second opening before removing the hard mask layer, and After removing the above hard mask layer, the above protective layer is removed.
依照本發明一實施例所述，上述保護層之材質包括有機材料、無機材料或聚合物材料。According to an embodiment of the invention, the material of the protective layer comprises an organic material, an inorganic material or a polymer material.
依照本發明一實施例所述，上述保護層之材質包括感光材料。According to an embodiment of the invention, the material of the protective layer comprises a photosensitive material.
依照本發明一實施例所述，上述保護層之材質包括富碳型光阻。According to an embodiment of the invention, the material of the protective layer comprises a carbon-rich photoresist.
依照本發明一實施例所述，上述保護層之材質包括不感光材料。According to an embodiment of the invention, the material of the protective layer comprises a non-photosensitive material.
依照本發明一實施例所述，上述保護層與上述平坦層之材質相同。According to an embodiment of the invention, the protective layer is made of the same material as the flat layer.
依照本發明一實施例所述，上述保護層與上述平坦層之材質不相同。According to an embodiment of the invention, the protective layer and the flat layer are different in material.
依照本發明一實施例所述，上述半導體元件的製程方法更包括在移除上述平坦層的同時，移除上述保護層。According to an embodiment of the invention, the method of fabricating the semiconductor device further includes removing the protective layer while removing the planar layer.
依照本發明一實施例所述，上述保護層的形成方法包括形成保護材料層，填入於上述第二開口中並且覆蓋於在上述硬罩幕層上，之後，移除上述硬罩幕層上的保護材料層，使上述硬罩幕層裸露出來。According to an embodiment of the present invention, the method for forming the protective layer includes forming a protective material layer, filling the second opening and covering the hard mask layer, and then removing the hard mask layer. The protective material layer exposes the above hard mask layer.
依照本發明一實施例所述，上述基底上具有多個堆疊結構，且上述平坦層覆蓋上述些堆疊結構且填入於上述些堆疊結構之間的空間，上述第二開口使上述些空間其中之一裸露出來。According to an embodiment of the invention, the substrate has a plurality of stacked structures, and the flat layer covers the stacked structures and fills a space between the stacked structures, and the second opening makes the space A bare out.
依照本發明一實施例所述，上述平坦層的厚度為500nm至550nm。According to an embodiment of the invention, the flat layer has a thickness of 500 nm to 550 nm.
基於上述，本發明之半導體元件的製程方法可以形成具有所需輪廓的離子植入罩幕可以將離子植入正確的區域來形成摻雜區。Based on the above, the method of fabricating the semiconductor device of the present invention can form an ion implantation mask having a desired profile to implant ions into the correct region to form a doped region.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1至4是依據本發明一實施例所繪示之一種半導體元件的製程方法的剖面示意圖。1 to 4 are schematic cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment of the invention.
請參照圖1，提供一個具有高低起伏表面100。在一實施例中，高低起伏表面100的高低落差例如是100nm至200nm。在另一實施例中，高低起伏表面100的高低落差例如是100nm至500nm。此外，在一實施例中，構成高低起伏表面100包括基底10以及堆疊結構12。基底10之材質例如是半導體，例如是矽，或是化合物半導體。堆疊結構12的高度例如是150nm至300nm。堆疊結構12例如是包括閘介電層14、閘極導體層16以及頂蓋層18，但並不以此為限。閘介電層14之材質例如是氧化矽。閘極導體層16之材質例如是摻雜多晶矽、金屬矽化物或其組合。閘極導體層16例如是做為非揮發性記憶元件的控制閘。頂蓋層18之材質為絕緣材料，例如是氮化矽或是氧化矽。在另一實施例中，除了基底10以及堆疊結構12之外，構成高低起伏表面100還包括介電層20。介電層20位於堆疊結構12的側壁上。介電層20例如是氮化矽、氧化矽或是氧化矽/氮化矽/氧化矽堆疊層。介電層20例如是做為非揮發性記憶元件中控制閘與浮置閘之間的閘間介電層。此外，在又一實施例中，除了基底10、堆疊結構12以及介電層20之外，構成高低起伏表面100還包括介電層22。介電層22覆蓋在堆疊結構12上以及堆疊結構12之間的空間的基底10表面上。介電層22之材質例如是氧化矽，或是其他的介電材料。介電層的厚度例如是30nm至100nm。為方便起見，本發明是以基底10上具有堆疊結構12、介電層20以及介電層22做為實施例來舉例說明高低起伏表面100，但並不以此為限。Referring to Figure 1, a high and low relief surface 100 is provided. In an embodiment, the height difference of the high and low relief surface 100 is, for example, 100 nm to 200 nm. In another embodiment, the height difference of the high and low relief surface 100 is, for example, 100 nm to 500 nm. Moreover, in an embodiment, the high and low relief surface 100 comprises a substrate 10 and a stacked structure 12. The material of the substrate 10 is, for example, a semiconductor such as germanium or a compound semiconductor. The height of the stacked structure 12 is, for example, 150 nm to 300 nm. The stack structure 12 includes, for example, the gate dielectric layer 14, the gate conductor layer 16, and the cap layer 18, but is not limited thereto. The material of the gate dielectric layer 14 is, for example, hafnium oxide. The material of the gate conductor layer 16 is, for example, doped polysilicon, metal halide or a combination thereof. The gate conductor layer 16 is, for example, a control gate that is a non-volatile memory element. The material of the cap layer 18 is an insulating material such as tantalum nitride or tantalum oxide. In another embodiment, in addition to the substrate 10 and the stacked structure 12, the high and low relief surface 100 further includes a dielectric layer 20. Dielectric layer 20 is on the sidewalls of stack structure 12. The dielectric layer 20 is, for example, tantalum nitride, hafnium oxide or a tantalum oxide/tantalum nitride/yttria stack. The dielectric layer 20 is, for example, a dielectric layer between the gates and the floating gates in the non-volatile memory element. Moreover, in yet another embodiment, in addition to the substrate 10, the stacked structure 12, and the dielectric layer 20, the high and low relief surface 100 further includes a dielectric layer 22. The dielectric layer 22 covers the surface of the substrate 10 on the stacked structure 12 and the space between the stacked structures 12. The material of the dielectric layer 22 is, for example, yttrium oxide or other dielectric material. The thickness of the dielectric layer is, for example, 30 nm to 100 nm. For convenience, the present invention exemplifies the high and low relief surface 100 by using the stacked structure 12, the dielectric layer 20, and the dielectric layer 22 on the substrate 10 as an embodiment, but is not limited thereto.
請參照圖1與圖3，為在基底10中形成摻雜區36(如圖3所示)，本發明實施例係先製作植入罩幕。植入罩幕的的製程係在高低起伏表面100上依序形成平坦層24、硬罩幕層26以及光阻層28。平坦層24覆蓋介電層22的表面且填滿堆疊結構12之間的空間。平坦層24可以是感光材料或是不感光材料。平坦層24的材料可以是有機材料、無機材料或聚合物材料。平坦層24之材料例如是富碳型光阻。平坦層24的厚度例如是500nm至550nm。所述的厚度是指堆疊結構12之間之介電層22以上的厚度。平坦層24可以旋塗的方式形成，或其他任何已知的方式來形成。Referring to FIG. 1 and FIG. 3, in order to form a doping region 36 (shown in FIG. 3) in the substrate 10, an embodiment of the present invention is to first fabricate an implant mask. The process of implanting the mask forms a flat layer 24, a hard mask layer 26, and a photoresist layer 28 on the high and low relief surface 100 in sequence. The planarization layer 24 covers the surface of the dielectric layer 22 and fills the space between the stacked structures 12. The flat layer 24 can be a photosensitive material or a non-photosensitive material. The material of the flat layer 24 may be an organic material, an inorganic material or a polymer material. The material of the flat layer 24 is, for example, a carbon-rich photoresist. The thickness of the flat layer 24 is, for example, 500 nm to 550 nm. The thickness refers to the thickness above the dielectric layer 22 between the stacked structures 12. The planar layer 24 can be formed by spin coating, or in any other known manner.
硬罩幕層26之材質與平坦層24不同，且與光阻層28不同。硬罩幕層26對平坦層24的蝕刻選擇比為6以上，例如是6至10。硬罩幕層26之材質例如是富矽型光阻或氮化矽，但並不以此為限。硬罩幕層26的厚度例如是25nm至35nm。硬罩幕層26可以旋塗的方式形成，或其他任何已知的方式來形成。The material of the hard mask layer 26 is different from that of the flat layer 24 and is different from the photoresist layer 28. The etching selectivity ratio of the hard mask layer 26 to the flat layer 24 is 6 or more, for example, 6 to 10. The material of the hard mask layer 26 is, for example, a germanium-rich photoresist or tantalum nitride, but is not limited thereto. The thickness of the hard mask layer 26 is, for example, 25 nm to 35 nm. The hard mask layer 26 can be formed by spin coating, or in any other known manner.
光阻層28之材質可與平坦層24之材質相同或相異。光阻層28之材質例如是富碳型光阻，但並不以此為限。光阻層28可以旋塗的方式形成，或其他任何已知的方式來形成。光阻層28在後續將形成開口30圖案(請參照圖2)，此光阻層28的開口30圖案將再轉移至硬罩幕層26，因此，光阻層28厚度，僅需足以將其開口30圖案完整轉移至硬罩幕層26即可。光阻層28的厚度例如是150nm至200nm。平坦層24、硬罩幕層26以及光阻層28之厚度分別為500nm至550nm、25nm至35nm與150nm至200nm。The material of the photoresist layer 28 may be the same as or different from the material of the flat layer 24. The material of the photoresist layer 28 is, for example, a carbon-rich photoresist, but is not limited thereto. The photoresist layer 28 can be formed by spin coating, or in any other known manner. The photoresist layer 28 will subsequently form an opening 30 pattern (please refer to FIG. 2), and the pattern of the opening 30 of the photoresist layer 28 will be transferred to the hard mask layer 26, so that the thickness of the photoresist layer 28 is only sufficient to The opening 30 pattern is completely transferred to the hard mask layer 26. The thickness of the photoresist layer 28 is, for example, 150 nm to 200 nm. The thickness of the flat layer 24, the hard mask layer 26, and the photoresist layer 28 are 500 nm to 550 nm, 25 nm to 35 nm, and 150 nm to 200 nm, respectively.
之後，請參照圖2，對光阻層28進行曝光顯影製程，使光阻層28圖案化，形成第一開口30，裸露出硬罩幕層26。由於光阻層28是位於具有平坦的表面的平坦層24上方，而且光阻層28的厚度相當薄，在進行曝光時有足夠的景深，因此，非常易於控制，且可以使得所形成之第一開口30具有所需的輪廓。Thereafter, referring to FIG. 2, the photoresist layer 28 is subjected to an exposure and development process to pattern the photoresist layer 28 to form a first opening 30, and the hard mask layer 26 is exposed. Since the photoresist layer 28 is located above the flat layer 24 having a flat surface, and the thickness of the photoresist layer 28 is relatively thin, there is sufficient depth of field when performing exposure, and therefore, it is very easy to control and can be formed first. The opening 30 has the desired contour.
然後，請參照圖3，蝕刻移除第一開口30所裸露的硬罩幕層26與其下方的平坦層24，以形成第二開口32，裸露出堆疊結構12之間的空間上的介電層22。第二開口32的高寬比例如是10至20。蝕刻的方法可以採用非等向性蝕刻法，例如是乾式蝕刻法，所使用的蝕刻氣體例如是HBr。在一實施例中，光阻層28與平坦層24之材質相同，在硬罩幕層26蝕刻之後，在進行蝕刻平坦層24的過程中，光阻層28會被消耗殆盡，而裸露出硬罩幕層26。由於硬罩幕層26對平坦層24的蝕刻選擇比為6至10，因此在蝕刻平坦層24的過程中硬罩幕層26可做為硬罩幕。由於硬罩幕層26以及平坦層24是藉由蝕刻選擇比的差異以蝕刻的方式圖案化，因此，可將欲移除的硬罩幕層26以及平坦層24完全移除，製程易於控制，使得所形成的第二開口32具有所需的輪廓，不會如同使用曝光製程圖案化，在高深寬比的情形時，會受限於曝光時景深不足。Then, referring to FIG. 3, the hard mask layer 26 exposed by the first opening 30 and the flat layer 24 under the first opening 30 are etched away to form a second opening 32, and the dielectric layer between the stacked structures 12 is exposed. twenty two. The aspect ratio of the second opening 32 is, for example, 10 to 20. The etching method may be an anisotropic etching method such as a dry etching method using an etching gas such as HBr. In one embodiment, the photoresist layer 28 is made of the same material as the planar layer 24. After the hard mask layer 26 is etched, during the etching of the planar layer 24, the photoresist layer 28 is exhausted and exposed. Hard mask layer 26. Since the etching selectivity ratio of the hard mask layer 26 to the flat layer 24 is 6 to 10, the hard mask layer 26 can be used as a hard mask during the etching of the flat layer 24. Since the hard mask layer 26 and the flat layer 24 are patterned by etching in a difference in etching selectivity, the hard mask layer 26 and the flat layer 24 to be removed can be completely removed, and the process is easy to control. The resulting second opening 32 has a desired profile that does not resemble the use of an exposure process, and in the case of high aspect ratios, is limited by insufficient depth of field during exposure.
繼之，請繼續參照圖3，以硬罩幕層26與平坦層24做為植入罩幕，進行離子植入製程34，以於第二開口32底部的基底10中形成摻雜區36。摻雜區36例如是源極區或是汲極區。由於做為植入罩幕的硬罩幕層26與平坦層24中的第二開口32的輪廓非常良好，因此，離子植入製程34可以將離子植入正確的區域而形成具有所需輪廓的摻雜區36。Next, referring to FIG. 3, the hard mask layer 26 and the flat layer 24 are used as an implant mask to perform an ion implantation process 34 to form a doped region 36 in the substrate 10 at the bottom of the second opening 32. The doped region 36 is, for example, a source region or a drain region. Since the contour of the hard mask layer 26 as the implant mask and the second opening 32 in the planar layer 24 is very good, the ion implantation process 34 can implant ions into the correct region to form the desired contour. Doped region 36.
然後，請參照圖4，移除硬罩幕層26，再移除平坦層24，使堆疊結構12上的介電層22以及堆疊結構12側壁上的介電層20裸露出來。移除硬罩幕層26的方法例如是以乾蝕刻方法，利用HBr做為蝕刻氣體(蝕刻溶液)。在一實施例中，硬罩幕層26的材質為富矽光阻層，平坦層24的材質為富碳光阻層，由於硬罩幕層26的厚度非常薄，易於移除，不會有富矽光阻層過厚所衍生的殘留問題。平坦層24的材質為富碳光阻層，相較於富矽光阻層，非常易於移除，其可以利用任何已知的方法，例如是以氧氣電漿(O2 plasma)，或以有機溶劑移除，但並不以此為限。Then, referring to FIG. 4, the hard mask layer 26 is removed, and the planar layer 24 is removed to expose the dielectric layer 22 on the stacked structure 12 and the dielectric layer 20 on the sidewalls of the stacked structure 12. The method of removing the hard mask layer 26 is, for example, a dry etching method using HBr as an etching gas (etching solution). In one embodiment, the hard mask layer 26 is made of a germanium-rich photoresist layer, and the flat layer 24 is made of a carbon-rich photoresist layer. Since the thickness of the hard mask layer 26 is very thin, it is easy to remove, and there is no The residual problem derived from the thick ruthenium resist layer. The material of the flat layer 24 is a carbon-rich photoresist layer, which is very easy to remove compared to the germanium-rich photoresist layer, and can be used by any known method, such as oxygen plasma (O 2 plasma), or organic Solvent removal, but not limited to this.
上述實施例，係在基底10中形成摻雜區36之後，隨即移除硬罩幕層26。然而，在另一實施例中，請參照圖3A與3B，亦可以在基底10中形成摻雜區36之後，移除硬罩幕層26之前，先形成保護材料層38，覆蓋硬罩幕層26並填入第二開口32之中然後，再移除硬罩幕層26上方所裸露的保護材料層38，留下第二開口32中的保護層38a，並使上述硬罩幕層26裸露出來。之後，再移除硬罩幕層26。保護層38a之材質包括有機材料、無機材料或聚合物材料。保護層38a之材質可以是感光材料或是不感光材料。保護層38a之材質例如是富碳型光阻。在移除硬罩幕層26的過程中，介電層22被保護層38a所覆蓋，不會裸露出來，因此，保護層38a可以避免介電層22暴露於蝕刻環境中，故可防止介電層22損傷的問題。此外，在一實施例中，保護層38a之材質與上述平坦層24相同，在移除上述平坦層24時，保護層38a可以同時被移除，以簡化製程步驟。In the above embodiment, after the doping region 36 is formed in the substrate 10, the hard mask layer 26 is removed. However, in another embodiment, referring to FIGS. 3A and 3B, after the doping region 36 is formed in the substrate 10, the protective material layer 38 is formed to cover the hard mask layer before the hard mask layer 26 is removed. 26 and filling into the second opening 32, and then removing the exposed protective material layer 38 over the hard mask layer 26, leaving the protective layer 38a in the second opening 32, and exposing the hard mask layer 26 come out. Thereafter, the hard mask layer 26 is removed. The material of the protective layer 38a includes an organic material, an inorganic material, or a polymer material. The material of the protective layer 38a may be a photosensitive material or a non-photosensitive material. The material of the protective layer 38a is, for example, a carbon-rich photoresist. During the process of removing the hard mask layer 26, the dielectric layer 22 is covered by the protective layer 38a and is not exposed. Therefore, the protective layer 38a can prevent the dielectric layer 22 from being exposed to the etching environment, thereby preventing dielectric The problem of layer 22 damage. In addition, in an embodiment, the material of the protective layer 38a is the same as that of the flat layer 24 described above. When the flat layer 24 is removed, the protective layer 38a can be simultaneously removed to simplify the process steps.
綜上所述，本發明利用平坦層、硬罩幕層以及光阻層所組成的三層結構來形成離子植入製程所需的罩幕。光阻層的圖案是透過曝光顯影製程來形成；而硬罩幕層以及平坦層則是以蝕刻的方式來圖案化。由於光阻層是位於具有平坦的表面的平坦層上方，而且光阻層的厚度相當薄，在進行曝光時有足夠的景深，因此，非常易於控制所形成之第一開口的輪廓。再者，由於硬罩幕層對平坦層具有高的蝕刻選擇比，因此在蝕刻平坦層的過程中，硬罩幕層可做為蝕刻硬罩幕。此外，雖然，平坦層需要足夠的厚度來提供平坦的表面，但是，由於做為植入罩幕的硬罩幕層以及平坦層是以蝕刻的方式圖案化，因此，易於控制所形成的第二開口的輪廓，使得離子植入製程可以將離子植入正確的區域而形成具有所需輪廓之摻雜區。另外，在基底中形成摻雜區之後，移除硬罩幕層之前，先在第二開口中形成保護層，可以避免高低起伏表面在後續移除硬罩幕層的過程中遭到損傷。另一方面，保護層的材質可以選用與平坦層相同的材料，以在移除上述平坦層的同時被移除，以節省製程的步驟。In summary, the present invention utilizes a three-layer structure consisting of a flat layer, a hard mask layer, and a photoresist layer to form a mask required for an ion implantation process. The pattern of the photoresist layer is formed by an exposure development process; and the hard mask layer and the planar layer are patterned by etching. Since the photoresist layer is located above the flat layer having a flat surface, and the thickness of the photoresist layer is relatively thin, there is sufficient depth of field when performing exposure, and therefore, it is very easy to control the contour of the formed first opening. Moreover, since the hard mask layer has a high etching selectivity ratio to the flat layer, the hard mask layer can be used as an etching hard mask during the etching of the flat layer. In addition, although the flat layer requires a sufficient thickness to provide a flat surface, since the hard mask layer and the flat layer as the implant mask are patterned in an etched manner, it is easy to control the formed second The contour of the opening allows the ion implantation process to implant ions into the correct region to form a doped region having the desired profile. In addition, after the doped region is formed in the substrate, a protective layer is formed in the second opening before the hard mask layer is removed, so that the high and low relief surface can be prevented from being damaged during the subsequent removal of the hard mask layer. On the other hand, the material of the protective layer may be selected from the same material as the flat layer to be removed while removing the flat layer to save the process.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
10．．．基底10. . . Base
12．．．堆疊結構12. . . Stack structure
14．．．閘介電層14. . . Gate dielectric layer
16．．．閘極導體層16. . . Gate conductor layer
18．．．頂蓋層18. . . Roof layer
20．．．介電層20. . . Dielectric layer
22．．．介電層twenty two. . . Dielectric layer
24．．．平坦層twenty four. . . Flat layer
26．．．硬罩幕層26. . . Hard mask layer
28．．．光阻層28. . . Photoresist layer
30．．．第一開口30. . . First opening
32．．．第二開口32. . . Second opening
34．．．離子植入製程34. . . Ion implantation process
36．．．摻雜區36. . . Doped region
38．．．保護材料層38. . . Protective material layer
38a．．．保護層38a. . . The protective layer
100．．．高低起伏表面100. . . High and low undulating surface
圖1至4是依據本發明一實施例所繪示之一種半導體元件的製程方法的剖面示意圖。1 to 4 are schematic cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment of the invention.
10．．．基底10. . . Base
12．．．堆疊結構12. . . Stack structure
14．．．閘介電層14. . . Gate dielectric layer
16．．．閘極導體層16. . . Gate conductor layer
18．．．頂蓋層18. . . Roof layer
20．．．介電層20. . . Dielectric layer
22．．．介電層twenty two. . . Dielectric layer
24．．．平坦層twenty four. . . Flat layer
26．．．硬罩幕層26. . . Hard mask layer
28．．．光阻層28. . . Photoresist layer
30．．．第一開口30. . . First opening
100．．．高低起伏表面100. . . High and low undulating surface
Claims (18)
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|---|---|---|---|---|
| US6025273A (en) * | 1998-04-06 | 2000-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask |
| US6287961B1 (en) * | 1999-01-04 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
| TW505984B (en) * | 1997-12-12 | 2002-10-11 | Applied Materials Inc | Method of etching patterned layers useful as masking during subsequent etching or for damascene structures |
| TW516111B (en) * | 2001-06-08 | 2003-01-01 | Winbond Electronics Corp | Manufacturing method of triple self-aligned split-gate non-volatile memory device |
| TW587312B (en) * | 2003-03-28 | 2004-05-11 | Macronix Int Co Ltd | Manufacturing method for self-aligned multi-level virtually grounded mask ROM |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW505984B (en) * | 1997-12-12 | 2002-10-11 | Applied Materials Inc | Method of etching patterned layers useful as masking during subsequent etching or for damascene structures |
| US6025273A (en) * | 1998-04-06 | 2000-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask |
| US6287961B1 (en) * | 1999-01-04 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
| TW516111B (en) * | 2001-06-08 | 2003-01-01 | Winbond Electronics Corp | Manufacturing method of triple self-aligned split-gate non-volatile memory device |
| TW587312B (en) * | 2003-03-28 | 2004-05-11 | Macronix Int Co Ltd | Manufacturing method for self-aligned multi-level virtually grounded mask ROM |
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