TW587312B - Manufacturing method for self-aligned multi-level virtually grounded mask ROM - Google Patents

Abstract

The present invention is a manufacturing method for self-aligned multi-level virtually grounded mask ROM, which includes the following steps: providing a semiconductor substrate, which is covered with a hard mask thereon, and has a trench crossing the hard mask and a part of the substrate; forming a plurality of parallel openings on the hard mask to expose the semiconductor substrate; implanting the first type of ions in the semiconductor substrate along the parallel openings to form a plurality of parallel buried diffusion areas; depositing an insulation layer on the hard mask, filling the trench and planarizing the insulation layer to form a plurality of insulators and a trench isolation area; removing the pad oxide layer in the hard mask; forming a plurality of nitrified spacers on the insulators and on the sidewall of the trench isolation area; covering an interlayer dielectric on the insulators, the trench isolation area and the nitrified spacers; then, etching the interlayer dielectric and the pad oxide layer to form a plurality of contact windows among the buried diffusion areas, and selecting at least one of them for conducting the second type of ion implantation procedure to at least form a doping area.

Description

587312

The technical field to which the invention belongs: 0 right month i !! The manufacturing method of the read-only memory in the leather screen type, in particular, a self-aligned multi-level virtual ground mask read-only memory system. The prior art: non-volatile Memory (nonvolatile memory) can be divided into two types. The first type is Mask R〇M; Mask read 〇nly memory 疋 'When the memory is made, it has been programmed, that is, the logic has been defined. 〇 ” And logic "Γ, can not be rewritten after leaving the factory. Therefore, M ask R 0 Μ can be used for testing, so the reliability is high. The other is field programmable memory ) Means that it has not been programmed when making the memory, and can be programmed according to the needs of the user after leaving the factory. The traditional Mask ROM is a metal-oxide-semiconductor (MOS transistor; metal-oxide-semiconductor). The transistor is used as a memory uni t. The programmatic way is to adjust the threshold voltage of some MOS transistors by ion implantation to define logic "0 π and logic π 1 π. However, with the increasing density of integrated circuits and the shrinking development of component sizes, the introduction of Mask ROM in deep sub-micron processes has encountered process technical limitations and difficulties, that is, when ion implantation enters the channel area of the memory cell (channel region), because the implantation area is not easy to accurately control and misalignment is easy to occur, the threshold voltage of the transistor is changed, and because the implantation area is not aligned,

0389-8467twf (nl); P910384; DAVID.ptd Page 5 587312 V. Description of the invention (2) Will change the word line (word ^ · causes the memory unit to store data in the direction of blt llne). Adjacent area $, which affects the overall memory cell :: bad: phase transfer mask (PSM; phase shif-evening nature). S knows the problem, but this method will increase the process time chart to solve the above problem The consideration of the benefits. The cost of operation is not in line with the historical process of reading and memorizing the shame of the curtain, because only one ion implantation ... Contains the logical symbol of the memory unit that "has" or "many workers sheltered, will, and get one by one. If PK love :, that is, " 〇, or T increase ... the base of the memory unit, so ^ 2 Body size *, which must be accumulated, resulting in a reduction in the yield of transistor elements. ㈢ Reduce the memory of the body. Summary of the invention: In view of this, the object of the present invention is to provide an improved process of the body to avoid the occurrence of dislocation. , F-actual read-only memory, etc. The threshold voltage of the solar system changes in order to achieve In the above problem, the present invention provides a method for manufacturing a ground-mask-type read-only memory; == self-aligned multi-level virtual conductor substrate, one of which has an opening formed thereon (including: provide-half mask), the hard cover The curtain includes an oxide layer and a curtain (hard sculpting the semiconductor substrate, forming a chemical layer at the opening, and selectively forming an energy bismuth with a plurality of parallel openings on the selective curtain, continued from the hard mask sensitive pattern) to The energy-sensitive pattern (energy ㈣ the hard mask to expose the semiconductor substrate .; Medium

587312 forms a plurality of regions), an oxygen edge layer is deposited thereon, formed in an upper trench, and the contact window between the oxidation spacer wall, the nitrided spacer layer, and the dielectric layer diffusion region forms at least sidewalls that are aligned. The effect can be greatly reduced. In addition, the character lines have or pressure differences, and memory capacity. In the improved process, it is avoided that Xi greatly shortens the area-sensitive figure into the trench to form a plurality of removed insulators and dielectric layers of the hard-slot isolation area in the semi-conducting window. Finally, the fifth invention description (3) Type ion, followed by (buried diffusion case) next to the hard mask groove, planarizing the oxidized insulating oxide insulator and forming a plurality of nitrogen on the sidewall of the pad nitride layer in the mask. The trench isolation region and the above Afterwards, the selective implantation of the above-mentioned type II ion implantation program on the semiconductor substrate embedded in the semiconductor substrate was performed. According to the ion implantation program of the self-insulator and the trench isolation region according to the present invention, it was indeed caused by misalignment. The memory can be multiplied under the premise that the electricity between the memory units is used. In addition, the production of the area of the invention can complete the complicated steps of production at the same time, which is simple and economical. After the diffusion, the electrochemical insulating layer is removed, and a trench isolation region on the buried diffusion region is filled in. The chemical insulator and the trench and the above oxidation are covered with a Between the layers and the pad oxide layer, a plurality of contacts are formed, and at least one of them is selected to carry out the first doping region. Improved process, and then combined with the oxidized nitriding spacer structure to reduce the chance of dislocation, thereby avoiding a multi-stage method The improved process is designed with no connection difference to increase the memory so that it does not affect the yield. In the known technology of oxidized insulator and trench isolation, the two must be divided into successive time, so that this process is more concise, and the purpose, characteristics and The advantages are more obvious and easier to understand

587312

In conjunction with the attached drawings, a detailed description is given below. A preferred embodiment is given below: Implementation method:

As shown in FIG. 1, a semiconductor (P-type monocrystalline) substrate 100 is provided, on which a hard mask curtain (one of the openings 105) is formed. A silicon oxide layer is grown on the far semiconductor substrate 100 by a thermal oxidation process, a silicon nitride layer is deposited on the silicon oxide layer, and a photoresist pattern (not labeled) is formed on the silicon nitride layer by a development process. Using the photoresist pattern as an etching mask, the silicon nitride layer and the silicon oxide layer are etched to form a hard mask 'which includes a pad oxide layer 102 and a pad nitride layer 104, and is removed by conventional steps. A photoresist pattern is used to etch the semiconductor substrate to form a trench 106 at the opening 105. Next, as shown in FIG. 2, an energy-sensitive pattern 108 is formed on the hard mask like a conventional photoresist pattern. The energy-sensitive pattern 108 has a plurality of parallel openings 109. An energy-sensitive layer covering the hard mask and filling the groove is defined by the exposure and development procedures to form the energy-sensitive pattern I 0 8. The energy-sensitive pattern 108 is used as an etching mask to etch The hard mask is used to expose the semiconductor substrate 100, and the energy-sensitive pattern 108 is used as a cloth mask, and N-type ions such as phosphorus ions or phosphorus ions are implanted in the opening 109 in the semiconductor substrate 100. Arsenic ions, forming multiple buried buried diffusion regions

II 〇, the energy-sensitive pattern 108 is also covered and protected by the trench 106. As shown in FIG. 3, the energy-sensitive pattern 108 is removed by a conventional cleaning solvent or solution, and the upper surfaces of the semiconductor substrate 100, the trenches 106, and the hard mask are exposed. As shown in FIG. 4, an oxide 'insulating layer 11 2 is deposited on the hard mask.

0389-8467twf (nl); P910384; DAVID.ptd p. 8 587312

: Into the gap between the trench 106 and the hard cover ', wherein the oxide insulating layer 112 is preferably deposited by a high-density plasma chemical vapor deposition method, and then, as shown in FIG. 5, this The oxide insulating layer 112 is planarized by a chemical mechanical polishing method. A plurality of oxide insulators 112a are formed on the buried diffusion region 110, and a trench isolation region 112b is formed in the trench 106. As shown in FIG. 6, the pad nitride layer 104 is removed with a hot phosphoric acid solution, and the pad oxide layer 102 is exposed. Say

As shown in Figs. 7 and 8, a silicon nitride layer is deposited using SiH ^ Cl2 as the main reaction gas in a low pressure chemical vapor deposition method, and the silicon nitride layer 11 is etched back to the above. A plurality of nitrided spacers 114a and a trench isolation region 112b are formed on the sidewall of the oxidized insulator 2a.

As shown in FIG. 9, an interlayer dielectric layer 116 is formed on the oxidized insulator 2 and the nitrided spacer 114 =. The interlayer dielectric layer 116 is a silicon oxide formed by a chemical vapor deposition method. BSG or BPSG, followed by mechanical polishing, and the negative dielectric material with low dielectric constant formed by spin coating can replace the above-mentioned silicon oxide, BSG or BPSG. An energy-sensitive pattern 11 8 having a plurality of openings 丨 2 0 is formed on the interlayer dielectric layer 11 6 by a conventional lithography process, and the above-mentioned openings 1 2 0 of the energy-sensitive pattern 丨 8 are passed through an active ion etching method. Carry out the anisotropic surname of the interlayer dielectric layer 116 and the pad oxide layer 102 to form a plurality of contact windows 1 2 2, 1 2 4, 1 2 6 to expose any two buried diffusion regions 110 The semiconductor substrate. As shown in Fig. 10, after the energy-sensitive pattern 118 is removed, the first ion distribution procedure is performed. In this step, the interlayer dielectric layer 丨 6 is overlaid.

0389-8467twf (nl); P9l0384; DAVID.ptd page 9 587312 V. Description of the invention (6) Cover a first fabric cover 130 and expose one of the contact windows 122 to the conductor substrate 1001), with a first dose (D1) of p-type ions such as boron di 132. The semiconductor substrate 100b forms a doped region having the first dose as shown in FIG. 11. After the first implantation mask 13 is removed, the first ion implantation procedure is performed. In this step, the The interlayer interlayer layer 116 is covered with the first implant mask 134 'and exposes a part of the semiconductor substrate in the contact windows 122, 124,.... . … The first one touches the second one

Type ions such as boron implanted into the semiconductor substrate (1001) and 10 吒, forming a doped region 132a and a doped region 136. Among them, the first dose ii) is higher than the second dose 02), or the first dose (D1) is equal to or lower than the second dose and as shown in FIG. A gate dielectric layer 140 and a polycrystalline silicon layer 142 as a gate electrode are patterned. q According to the present invention, a self-aligned multi-level virtual ground-mask-type read-only memory, a method of making xe, and a memory cell without P-type ion implantation, because it is not connected to the character = has the highest voltage, π The memory cell C4 implanted with a non-buffered ion has the lowest voltage because it is connected to the word line.

Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the invention. Anyone who is familiar with this art can make some changes and retouch without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention is determined by the scope of the attached patent application.

587312 Brief description of the drawings Figures 1 to 12 are a series of cross-sectional views, showing the manufacturing process according to the embodiment of the present invention in green. Explanation of symbols: 11 2b ~ trench spacer; 11 4 ~ silicon nitride layer; 11 4a ~ nitride spacer; 11 6 ~ interlayer dielectric layer; 122, 124, 126 ~ contact 130, 134 ~ first implant Covers 132, 132a, 136 ~ doped 140 ~ gate dielectric layer; 14 ~ 2 polycrystalline silicon layer; 100 ~ semiconductor substrate; 102 ~ pad oxide layer; 104 ~ pad nitride layer; 1 0 5, 1 0 9, 1 2 0 ~ opening 1 0 6 ~ groove; window 108, 118 ~ energy sensitive pattern; curtain 1 10 ~ buried diffusion area; 11 2 ~ oxide insulation layer; 11 2a ~ oxide insulator;

Cl, C2, C3, C4 ~ memory unit

0389-8467twf (nl); P910384; DAVID.ptd Page 11

Claims (1)

587312 VI. Application Patent Scope 1 · A method for manufacturing a self-aligned multi-level virtual ground mask type read-only memory, comprising: providing a semiconductor substrate, the substrate is covered with a hard mask (where the hard mask) The mask includes an oxide layer and a nitride layer, and has a groove passing through the hard mask and a part of the substrate. A plurality of parallel openings are formed on the hard mask to expose the semiconductor substrate. The first type ions are implanted in parallel in the semiconductor substrate to form a plurality of parallel buried diffusion regions; an insulating layer is deposited on the hard mask, and the trench is filled; An insulating layer, forming a plurality of insulators on the buried diffusion region and forming a trench isolation region in the trench; removing the hafnium nitride layer in the hard mask; between the insulator and the trench isolation region A plurality of nitrided spacers are formed on the sidewall; and an interlayer dielectric layer is covered on the insulator, the trench isolation region, and the nitrided spacers. Xingnong 2 = 1 please make the self-aligned multi-level virtual ground memorizer manufacturing method described in the first item of the patent scope ... covering the interlayer dielectric layer and selectively etching the interlayer dielectric layer and the pad oxide layer, & Forming holes / holes between the above-mentioned buried diffusion regions on the substrate; and several contact windows (contact entered into the above-mentioned contact windows on the semiconductor substrate, at least _ 0389-8467twf (nl); P910384; DAVID.ptd, page 12, 587312, Shen Jing's patent scope, the second type of separation & • The soil carving in the implantation process, so that at least one doped region (doped regi0n) is formed. 0 3 If you want | ^. «I request a patent The manufacturing method of self-aligned multi-level virtual ground ^ read-only memory described in the first item of the scope, wherein the step of covering a hard mask further includes: growing a silicon oxide layer on a semiconductor substrate by a thermal oxidation process; A vapor deposition method is used to deposit a silicon nitride layer on the oxide layer; a photoresist pattern is formed on the silicon nitride layer by a f-shower; and the silicon nitride layer and the silicon oxide layer are etched to form a silicon nitride layer. The hard mask includes a pad oxide layer and a pad nitride layer. 1 it as: Please refer to the self-aligned multi-level virtual ground phase as described in item 1 of the patent scope: 2 Master's memory method, the middle is formed by high-density plasma chemical lice phase / child product method The insulating layer 5 ^ The manufacturing method of the self-aligned multi-level virtual ground memory body described in item 1 of the patent scope, wherein the planarization process of the insulating layer is decompressed by chemical mechanical polishing. Act 6 type id: Fan! The self-aligned multi-step virtual ground wall described in item 1 is more = method, and a plurality of nitrided gaps are formed in a plurality of insulators in a 盖 cover IIh. Ifcit r〇-τ- 石Nitrided layer; and 〃 # ^ away from the surface conformably deposited-the money is engraved on the stone Nitrided layer to form a plurality of nitriding spacers. Please refer to the self-alignment mask described in item 丨 of the patent scope Method for manufacturing read-only memory, in which the first type is N-type IH 0389-8467twf (nl); P910384; DAVID.ptd Page 13 587312 VI. Patent Application Range Ion, Type 8. 8. A method, including: providing half of the formation with an oxide layer and a selective etching of Hard mask pattern; burying diffusion of the semiconductor in the semiconducting line with the energy to remove the planarization of the oxidized insulator in the hard mask to remove the hard oxynitride spacer; on the oxygen, covering One layer 9. For example, if you apply for a mask-type read-only recording of the sensitive map substrate and the body substrate area; the quantity-sensitive screen sinks and oxidizes and ions in the mask are chemically insulated and the dielectric dielectric patent Fan Yi's ion system is P- Type ion. I aimed at the conductor substrate of the read-only memory of the multi-level virtual ground mask type; a hard mask with an opening, wherein the hard mask includes a nitride layer; the semiconductor substrate was engraved to form a semiconductor substrate at the opening. A trench; an energy-sensitive case with a plurality of parallel openings is formed on the screen as an etching mask, and the hard mask is etched to implant the first type ions in a storm to form a plurality of flat patterns; an oxide insulating layer is accumulated, And filling the trench; an edge layer forming a trench isolation region in the plurality of trenches formed on the above-mentioned buried diffusion region; the pad nitride layer; a body and a plurality of individual trenches formed on the sidewall of the trench isolation region and the trench The trench isolation region and the above-mentioned nitrided spacer layer. The self-aligned multi-stage virtual ground manufacturing method according to item 8, wherein the interlayer dielectric layer step is covered 0389-8467twf (nl); P910384; DAVID.ptd p. 14 Including ^ 7312 6. The scope of the patent application after the step further includes: Selective: When the layer is electrically connected to the pad oxide layer, the above-mentioned buried diffusion regions on Dow form a plurality of the above-mentioned contact windows that contact the semiconductor substrate. In the at least one type of ion implantation process, at least one doped region is formed. 10. The manufacturing method of a self-aligned mask type read-only memory as described in item 8 of the patent application scope, wherein a mask with a mask is formed. The steps further include: growing a stone on a semiconductor substrate by a thermal oxidation process, and depositing a silicon nitride film on the silicon nitride layer by a development process by chemical vapor deposition using a chemical vapor deposition method to etch the silicon nitrogen And a silicon oxide layer to form a hard pad oxide layer and a pad nitride layer. 11. The method for manufacturing a self-aligned mask type read-only memory as described in item 8 of the scope of patent application, wherein forming an energy step further comprises: covering an energy sensitive layer on a hard mask and filling in ; And defining the energy-sensitive layer in a sensitive pattern by exposure and development procedures. 1 2 · The manufacturing method of self-aligned mask type read-only memory as described in item 8 of the scope of patent application, wherein the planarization process of the dielectric layer is oxidized chemically. 1 3 · Self-aligned to the semiconductor tooth as described in item 8 of the scope of the patent application, and one of them, a hard oxide layer with a multi-level virtual ground and an opening; a silicon nitride layer; a case, and a mask, It includes a multi-level virtual grounding quantity sensitive pattern into a trench to form an energy multi-level virtual grounding mechanical polishing method multi-level virtual grounding 587312 VI. Scope of patent application f. The manufacturing method of f-type read-only memory, t is a high-density plasma chemical vapor deposition method to form the oxide dielectric layer. 1 4 · The method for manufacturing a self-aligned multi-level virtual ground mask type read-only memory as described in item 8 of the scope of patent application, wherein the step of forming a plurality of nitrided spacers further includes: ^ a plurality of oxidized insulators and A silicon nitride layer is compliantly deposited on the surface of a trench isolation region; and the silicon nitride layer is etched back to form a plurality of nitrided spacers. 1 5 · The method for manufacturing a self-aligned multi-level virtual ground mask type read-only memory as described in item 8 of Shenjing's patent scope, wherein the first type ion system is 1 ^ type I ion and the second type ion system It is a P-type ion. 0389-8467twf (nl); P910384; DAVID.ptd Page 16