JP2011165933A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance workability of patterning that uses a sidewall transfer technology. <P>SOLUTION: A carbon film 9a is formed on a processed film 8 for forming a gate electrode MG by using a CVD method, and then an SOG film is formed. The carbon film 9a is half-etched with a resist pattern using a lithographic technology, and the width dimension is reduced by half from Wa to Wb, and a core material pattern portion 9b is formed. An amorphous silicon film 14 is formed over the entire surface, and then a spacer pattern 14a is formed by using etch-back processing. The core material pattern portion 9b and the carbon film 9a are etched, by using the spacer pattern as a mask and forms a mask pattern 9. Since a resist is not used as a core material pattern, processing at high temperatures is possible, and workability is enhanced. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device that forms a fine pattern.

  In manufacturing technology for forming a line-and-space pattern on a semiconductor substrate, in recent years, it has been required to be finer than the exposure limit of lithography technology. Therefore, conventionally, in addition to optical patterning technology, a film is formed on the upper surface and side wall of the pattern formed by exposure, and spacer processing is performed on the film to form a spacer pattern, which is used as a mask pattern. Technology to do this is being developed.

  This is a technique for forming a fine pattern by using a spacer pattern formed in this way as a mask and transferring it to a base film to be processed such as a gate electrode or element separation. As a result, it is possible to form a fine pattern having a width half that of the pattern formed by optical exposure, and a manufacturing technique using such a sidewall transfer process is now becoming mainstream.

  For example, in the sidewall transfer process disclosed in Patent Document 1, a carbon film as a mask film is formed on a film to be processed, and a resist pattern serving as a core material pattern is formed on the upper surface. Subsequently, a silicon oxide film as a mask film is formed so as to cover the resist pattern, and an etch back process is performed to form spacer-like patterns on both side walls. The carbon film is patterned using this mask pattern, and the film to be processed is further patterned.

  In this case, since the resist pattern is used as the core material pattern, after the resist film is formed, it is not possible to be exposed to high temperature for film formation or processing, and a process that can be performed at low temperature is a basic condition. As a restriction. However, in the patterning process, there is a situation in which the controllability of the pattern cannot be improved unless high-temperature processing is generally performed, and such a technique of Patent Document 1 is an unsuitable process in a processing process that requires workability. .

JP 2009-302143 A

  An object of the present invention is to provide a method of manufacturing a semiconductor device that can improve the processability of patterning using a sidewall transfer technique.

  A method for manufacturing a semiconductor device of one embodiment of the present invention includes a step of forming a carbon-containing film made of a material containing carbon (C) on a workpiece, and patterning the carbon-containing film from an upper surface to an intermediate depth. Forming a core material pattern portion by processing, forming a mask film having a predetermined thickness so as to cover an upper surface and a side surface of the core material pattern portion, and an upper surface of the carbon-containing film; and Etch-back processing to expose the upper surface of the core material pattern portion and the upper surface of the carbon-containing film to form a mask pattern on the sidewall of the core material pattern portion; and the mask pattern is transferred to the carbon-containing film. And a step of etching the core pattern portion and the carbon-containing film.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming a carbon-containing film made of a material containing carbon (C) on a workpiece; Forming a core material pattern portion having a predetermined interval by patterning to a depth of a predetermined depth, and forming a mask film having a predetermined thickness so as to cover the upper surface and side surfaces of the core material pattern portion and the upper surface of the carbon-containing film. A step of forming a resist pattern on the mask film at a position different from the core material pattern portion; and after forming the resist pattern, the mask film is etched back to form an upper surface of the core material pattern portion. And exposing the upper surface of the carbon-containing film excluding the resist pattern portion to form a mask pattern on the sidewall of the core material pattern portion and the resist pattern portion , Having characterized in that comprising the step of the mask pattern in the carbon-containing layer is etched using the core pattern portion and the carbon-containing layer so that it will be transcribed.

  According to the present invention, it is possible to improve the processability of patterning using a sidewall transfer technique.

1 is a schematic plan view showing a layout pattern of transistors in a part of a memory cell region and a peripheral circuit region of a NAND flash memory device according to a first embodiment of the present invention. FIG. 1A is a schematic cross-sectional view schematically showing a processing step of a gate electrode at a portion indicated by a cutting line AA in FIG. FIG. 1A is a schematic cross-sectional view schematically showing a groove processing step for forming an element isolation insulating film at a portion indicated by a cutting line BB in FIG. (A), (b), (c) is typical sectional drawing which shows each process of forming the mask pattern in the case of processing the part shown by the cutting line AA in Fig.1 (a) (the 1) (D), (e), (f) is typical sectional drawing which shows each process of forming the mask pattern in the case of processing the part shown by the cutting line AA in Fig.1 (a) (the 2) The 2nd Embodiment of this invention is shown, (a), (b), (c) is the part shown by the cutting line AA in FIG. 1 (a) and the cutting line CC in FIG.1 (b). Typical sectional drawing which shows each process of forming the mask pattern in the case of processing (Part 1) (D), (e), and (f) each form the mask pattern in the case of processing the part shown by the cutting line AA in FIG. 1 (a) and the cutting line CC in FIG. 1 (b). Schematic sectional view showing the process (Part 2)

(First embodiment)
Hereinafter, a first embodiment of the present invention applied to a processing process of a NAND flash memory device will be described with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  The NAND type flash memory device includes a memory cell region in which a large number of memory cell transistors are arranged in a matrix and a peripheral circuit region including a peripheral circuit transistor for driving the memory cell transistor.

  FIG. 1A shows a partial layout pattern of the memory cell region, and FIG. 1B is a plan view showing transistors in the peripheral circuit region. In FIG. 1A, a plurality of element isolation insulating films 2 formed by STI (shallow trench isolation) technology are formed on a silicon substrate 1 as a semiconductor substrate along the Y direction in FIG. . A plurality of element isolation insulating films 2 are formed at a predetermined interval in the X direction in FIG. 1A, and thereby a plurality of active regions 3 are separately formed on the surface layer portion of the silicon substrate 1.

  A plurality of word lines WL of memory cell transistors are formed along the X direction in FIG. 1A so as to be orthogonal to the active region 3. In addition, a selection gate line SGL1 of a pair of selection gate transistors is formed along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of select gate lines SGL1. A gate electrode MG of the memory cell transistor is formed on the active region 3 intersecting with the word line WL, and a gate electrode (selection gate electrode) SG of the selection gate transistor is formed on the active region 3 intersecting with the selection gate line SGL1. Yes.

  In FIG. 1B, an element isolation insulating film 2 is formed on a silicon substrate 1 so as to leave a rectangular active region 3a. The transistor TrP formed in the peripheral circuit region is provided in the rectangular active region 3a. An isolated gate electrode PG is formed across the active region 3a, and source / drain regions formed by diffusing impurities are provided on both sides thereof.

  Next, the processing steps to be applied in the present embodiment will be described. First, FIGS. 2A and 2B, which are shown as the first object, show schematic cross sections before and after processing when performing batch processing of gate electrodes to be word lines WL of a NAND flash memory device. In FIG. 1A, this corresponds to the portion indicated by the cutting line AA.

  In FIG. 2A showing a state before processing, a gate insulating film 4 is formed on the upper surface of the silicon substrate 1, and a film constituting the gate electrode MG is laminated on the upper surface. The films constituting the gate electrode MG are the polycrystalline silicon film 5, the intergate insulating film 6, the polycrystalline silicon film 7, and the silicon nitride film 8 from the bottom. These films 5 to 8 are processed films. A state in which a mask pattern 9 made of a carbon film is formed on the upper surface of the silicon nitride film 8 is shown.

  Then, using the mask pattern 9 having the above-described structure, the silicon nitride film 8 that is a film to be processed is first etched and patterned, then the mask pattern 9 is removed, and a processed pattern of the patterned silicon nitride film 8 is obtained. The polycrystalline silicon film 7, the inter-gate insulating film 6, and the polycrystalline silicon film 5 constituting the gate electrode MG are sequentially processed to obtain the configuration shown in FIG.

  Prior to the processing step of the gate electrode MG, a process of forming a mask pattern 9 is performed. The mask pattern 9 is formed with a pattern width dimension (line dimension Wb) of, for example, about 25 nm and is adjacent to the mask pattern 9. The distance dimension (space dimension Wb) is also formed at about 25 nm, for example. That is, the line and space dimension is 25/25 nm. As will be described later, the fine mask pattern 9 is formed by reducing the pitch from the patterning dimension Wa in the photolithography processing step to about ½.

  Next, FIGS. 3A and 3B shown as the second object are schematic cross sections before and after the processing step for forming the element isolation groove (trench) of the NAND flash memory device. This corresponds to the portion indicated by the section line BB in FIG. However, FIG. 1A shows a plan view in a state in which the word line WL is formed. However, in the configuration in this case, the processing step before forming the word line WL is an object.

  In the state before processing shown in FIG. 3A, the gate insulating film 4 is formed on the silicon substrate 1, the polycrystalline silicon film 5 serving as the floating electrode of the gate electrode MG is formed on the upper surface, and the upper surface is further formed. A silicon nitride film 10 for processing is laminated. A silicon oxide film 11 as a patterned film is formed in a predetermined pattern with respect to the silicon substrate 1, the gate insulating film 4, the polycrystalline silicon film 5 and the silicon nitride film 10 as the final processed film. Has been. The silicon oxide film 11 is formed by forming a mask pattern on the upper surface in a manufacturing process prior to this and etching using the mask pattern. The silicon oxide film 11 is formed with a pattern width dimension (line dimension Wb) of, for example, about 25 nm, and an interval dimension (space dimension Wb) with adjacent ones, for example, of about 25 nm.

  Using the silicon oxide film 11 as a mask, as shown in FIG. 3B, the underlying silicon nitride film 10, the polycrystalline silicon film 5, the gate insulating film 4 and the silicon substrate 1 are etched by the RIE method or the like. A groove 1 a having a predetermined depth is formed in the silicon substrate 1. In the trench 1a, a silicon oxide film or the like is embedded and formed as an element isolation insulating film in a later step, and the element isolation insulating film 2 in the memory cell region described above is formed.

  Next, with respect to the process of forming the mask pattern 9 shown in FIG. 2 (a), the steps of a series of manufacturing steps shown in FIGS. 4 (a) to (c) and FIGS. 5 (d) to (f) are schematically shown. This will be described with reference to a cross-sectional view. 4 and 5 show the upper part of the part shown in FIG. 2 from the part of the silicon nitride film 8 and the polycrystalline silicon film 7 as the films to be processed. The inter-gate insulating film 6, the polycrystalline silicon film 5, the gate insulating film 4 and the silicon substrate 1 are not shown.

  First, as shown in FIG. 4A, a silicon nitride film 8 is formed on the polycrystalline silicon film 7 to be a control electrode. Next, a carbon film 9 a is formed on the upper surface of the silicon nitride film 8 as a carbon-containing film containing carbon (C). The carbon film 9a is formed in an atmosphere at a wafer temperature of about 500 ° C. by CVD (chemical vapor deposition), and the film thickness is about 300 nm, for example. Thereafter, an SOG (spin on glass) film 12 is formed, the resist film is exposed with a pattern of L / S (line and space) = 50/50 nm (width dimension Wa = 50 nm), and a resist pattern is developed through a development process. 13 is formed.

Next, as shown in FIG. 4B, the pattern is transferred to the SOG film 12 using the resist pattern 13 as a mask. In this transfer processing, for example, etching using CHF ₃ / O ₂ = 100/10 sccm as a processing gas is performed.

Subsequently, the carbon film 9a is subjected to half etching using the SOG film 12 to which the resist pattern 13 is transferred as a mask. In the half-etching of the carbon film 9a, a predetermined amount is etched from the upper surface to an intermediate depth under processing conditions using O ₂ / CH ₄ or the like as a processing gas. As a result, the core material pattern portion 9b formed by processing the carbon film 9a is formed on the upper surface portion of the carbon film 9a.

  Here, a half-etching process is performed in which the carbon film 9a is dug in the depth direction by, for example, about 100 nm, and the width dimension Wb of the line pattern, that is, the width dimension Wb of the core material pattern portion 9b is simultaneously reduced by this process. Etching isotropically so as to be about 25 nm which is about half of the thickness. As a result, the width of the SOG film 12 is also narrowed to become the SOG film 12a having the width Wb as shown in FIG. 4B.

  Further, by this etching process, the width dimension Wc of the space between the core material pattern portions 9b becomes approximately three times the width dimension Wb of the core material pattern portions 9b. Note that the width dimension Wb of the core material pattern portion 9b can be adjusted when the SOG film 12 is processed.

  Thereafter, as shown in FIG. 4C, the patterned SOG film 12a is removed by wet etching. In this case, the SOG film 12a remaining on the upper surface of the core material pattern portion 9b can be left as it is without being wet-etched.

  Next, as shown in FIG. 5D, an amorphous silicon film 14 is formed on the carbon film 9a on which the core material pattern portion 9b is formed. The amorphous silicon film 14 is formed with a film thickness of, for example, about 25 nm so as to have a film thickness substantially equal to the width dimension Wb of the core material pattern portion 9b, and is along the upper surface and side surfaces of the core material pattern portion 9b. It is formed so as to cover the entire surface along the upper surface of the carbon film 9a between the material pattern portions 9b.

  Subsequently, as shown in FIG. 5E, spacer processing is performed by etching back the amorphous silicon film 14. Thereby, the amorphous silicon film 14 is in a state in which the portions formed on the upper surface of the core material pattern portion 9b and the upper surface of the carbon film 9a between the core material pattern portions 9b are removed by etching and exposed, and the core material pattern portion 9b. The portions remaining on the both side walls are formed as spacer patterns 14a.

  Thereafter, as shown in FIG. 5F, the exposed carbon film 9a and core material pattern portion 9b are etched using the spacer pattern 14a as a mask. As a result, the spacer pattern 14a itself is etched to some extent to become a spacer pattern 14b whose height is reduced as shown in the figure. However, the carbon film 9a located immediately below the spacer pattern 14b remains, and the mask pattern 9 Is transferred and formed on the carbon film 9a. The mask pattern 9 is formed so that the width dimension is Wb and the distance between the mask patterns 9 is also Wb, and is half the width dimension Wa of the resist pattern 13 and approximately half the pitch of the resist pattern 13. It can be patterned.

  The mask pattern 9 sequentially etches the silicon nitride film 8, the polycrystalline silicon film 7, the inter-gate insulating film 6, and the polycrystalline silicon film 5, which are a laminated structure for forming the gate electrode MG provided as a film to be processed. Can be used as a mask.

  According to the first embodiment, the carbon film 9a is partially processed from the upper surface to the height of the intermediate portion to form the core material pattern portion 9b, and the spacer pattern 14a is formed thereon, so that the resist pattern Compared to the conventional technique using as a core material pattern, the processing can be performed at a high temperature. In the case of using a resist pattern, for example, up to about 200 ° C. is the upper limit temperature at which heat treatment can be performed. It can be carried out. Thereby, processability or process capability can be improved in the film formation process or processing process, and the mask pattern 9 can be formed with high accuracy. As a result, the processability of the film to be processed can be improved.

  Further, according to the present embodiment, since the core material pattern portion 9b is formed by half-etching the carbon film 9a, a process that does not use a material such as a stopper film as a base of the core material pattern can be achieved. . As a result, even when there is a heat treatment up to about 500 ° C. in the mask pattern formation process, problems such as the stopper film peeling off due to moisture generated from the carbon film as the mask film formed under the stopper film occur. Can be prevented.

  Since the carbon film 9a formed by the CVD method is used as the film for the mask pattern 9, since the workability in the vertical direction is high at the time of etching and the etching selectivity with the silicon film is large, the half etch depth should be reduced. Can do. In this case, the half-etch depth, that is, the height of the core material pattern portion 9b defines the height dimension of the spacer pattern 14a, and the spacer pattern 14a ensures a sufficient height as an etching mask for the carbon film 9a. It only has to be done.

  Further, the thickness dimension of the mask pattern 9 to be formed is determined to an appropriate amount depending on the film thickness and material of the film to be processed. As a result, the film thickness of the carbon film 9a is not less than the sum (thickness) of the height dimension required for the spacer pattern 14a and the height dimension required for the mask pattern 9, and is desired as process capability. What is necessary is just to set to the film thickness which added the film thickness to be added.

(Second Embodiment)
FIGS. 6 and 7 show a second embodiment of the present invention, and the following description will focus on parts that are different from the first embodiment. In the first embodiment, the formation of the pattern of the memory cell region shown in FIG. 1A is targeted. However, in the second embodiment, the pattern is formed in the peripheral circuit region shown in FIG. The pattern formation of the isolated gate electrode PG of the transistor TrP is also targeted.

  6A and 6B, each of the partial diagrams (a) to (f) uses the memory cell region shown in FIG. 1A as the first region and the peripheral circuit region shown in FIG. 1B as the second region. For the sake of convenience. The processing of the first region has the same processing state transition as that of the first embodiment, and is a step of adding a process for forming a pattern for the transistor TrP of the second region to this processing step.

Note that the second embodiment can be applied to any of the processing objects in FIGS. 2 and 3 as in the first embodiment.
First, as shown in FIG. 6A, a silicon nitride film 8 and a carbon film 9a as a carbon-containing film containing carbon (C) are formed on the polycrystalline silicon film 7 serving as a control electrode. The carbon film 9a is formed by an CVD method in an atmosphere with a wafer temperature of about 500 ° C., and the film thickness is, for example, about 300 nm. Next, the SOG film 12 is formed, and then the resist film is exposed with a pattern of L / S (line and space) = 50/50 nm (width dimension Wa = 50 nm) corresponding to the first region. Form.

  Next, as shown in FIG. 6B, the pattern is transferred to the SOG film 12 using the resist pattern 13 formed in the first region as a mask. Subsequently, the carbon film 9a is subjected to half etching using the SOG film 12 to which the resist pattern 13 is transferred as a mask. In these steps, the processing conditions are substantially the same as those in the first embodiment, and therefore will be omitted. As a result, the core material pattern portion 9b having the width Wb formed by processing the carbon film 9a is formed on the upper surface portion of the carbon film 9a in the first region.

  Thereafter, as shown in FIG. 6 (c), the patterned SOG film 12a is removed by wet etching, and then the first region and the core material pattern portion in which the core material pattern portion 9b of the carbon film 9a is formed. An amorphous silicon film 14 is formed on the upper surface of the second region where 9b is not formed. The amorphous silicon film 14 is formed with a film thickness of, for example, about 25 nm so as to have a film thickness substantially equal to the width dimension Wb of the core material pattern portion 9b, and is along the upper surface and side surfaces of the core material pattern portion 9b. It is formed so as to cover the entire surface along the upper surface of the carbon film 9a between the material pattern portions 9b.

  Next, as shown in FIG. 7D, a resist pattern 15 is formed in order to form a mask pattern corresponding to the isolated gate electrode PG in the second region. The resist pattern 15 is formed with a width dimension Wd of 50 nm or more, for example, and has a dimension that can be patterned by a normal photolithography technique. In addition, unlike the line and space pattern of the first region, the resist pattern 15 is formed as a pattern of the isolated gate electrode PG having a rectangular shape, and has a long rectangular shape that is the shape of the gate electrode PG. It is an isolated pattern. In addition, when applied to the object of FIG. 3, it is a rectangular isolated pattern close to a square corresponding to the shape of the active region forming the transistor TrP. Note that such an isolated pattern by the resist pattern 15 can be formed in an arbitrary shape that can be formed by a photolithography technique as corresponding to an element formed in the peripheral circuit region.

  Subsequently, as shown in FIG. 7E, the amorphous silicon film 14 is etched back to perform spacer processing. At this time, since the core material pattern portion 9b is formed in the first region, the amorphous silicon in the portion formed on the upper surface of the core material pattern portion 9b and the upper surface of the carbon film 9a between the core material pattern portions 9b. The film 14 is removed by etching and exposed, and the amorphous silicon film 14 is left on both side walls of the core material pattern portion 9b to form the spacer pattern 14a. In the second region, the amorphous silicon film 14 of the other part is etched except for the part immediately below where the resist pattern 15 is formed, and the isolated pattern part 14c is formed.

  Thereafter, as shown in FIG. 7F, the exposed carbon film 9a and core material pattern portion 9b are etched using the spacer pattern 14a and the isolated pattern portion 14c as a mask. As a result, the carbon film 9a located immediately below the spacer pattern 14b remains and the mask pattern 9 is transferred and formed on the carbon film 9a, and the carbon film 9a located directly below the isolated pattern portion 14c remains. An isolated mask pattern 16 is transferred and formed on the carbon film 16a.

  According to the second embodiment, in addition to the process corresponding to the first region in the first embodiment, the step of forming the resist pattern 15 for the transistor TrP corresponding to the second region is added. Therefore, it is possible to form the mask pattern 9 for performing line and space processing corresponding to the first region, and to form the isolated mask pattern 16 corresponding to the second region. Thereby, while forming the mask pattern 9 for forming a fine pattern that cannot be formed by the photolithography technique, it is possible to form the isolated mask pattern 16 having an arbitrary shape that can be formed by the photolithography technique at the same time. Complex patterning can be achieved without significantly increasing the number of processes.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
In the half etching process, the carbon film 9a is etched in the depth direction and the slimming process is performed at this stage. However, the resist pattern 13 formed by the photolithography process is slimmed in advance to obtain a width. It can also be formed to the dimension Wb. In this case, the core material pattern portion 9b can be formed only by performing anisotropic etching in the half-etching process.

  In the processing step of the underlying film to be processed using the mask pattern 9, the silicon nitride film 8 is etched using the mask pattern 9 as a mask, and then the films 5 to 7 of the gate electrode MG are further etched while leaving the mask pattern 9. It may be processed.

The carbon-containing film can be applied as long as it contains carbon in addition to the carbon film 9a formed by the CVD method used in this embodiment.
In the second embodiment, the first region is made to correspond to the memory cell region, and the second region is made to correspond to the peripheral circuit region. However, the present invention is not limited to this, and the first region where the line and space pattern is formed It can be applied to various objects to be processed corresponding to the second region where the isolated pattern is formed.

  The SOG film 12 is not an essential configuration for forming the mask pattern 9, and can be used as necessary. In this case, depending on the characteristics of another carbon-containing film that replaces the carbon film 9a formed under the SOG film 12, the SOG film 12 may be omitted.

A film other than a silicon nitride film or a silicon oxide film may be used as a base material for the mask pattern 9 as long as selectivity with other films can be obtained when used as a mask film.
The workpiece to be transferred using the mask pattern 9 as a mask may be an amorphous silicon film, a polycrystalline silicon film, or another insulating film, in addition to the silicon nitride film and the silicon oxide film, or as another conductor film or semiconductor film. Also good. Further, in the case of forming an element isolation trench using the mask pattern 9 as a mask, the groove is not limited to the structure of FIG. 3 in which a semiconductor substrate and a gate insulating film or a gate electrode formed on the upper surface thereof are processed materials. What is necessary is just to perform the process of groove | channel using the surface layer part of a semiconductor substrate as a workpiece.

  The target device is not limited to a NAND flash memory device, but can be applied to a NOR flash memory, an SRAM, or other semiconductor memory devices, and can also be applied to general semiconductor devices including line and space pattern formation. .

  In the drawings, 4 is a gate insulating film, 5 is a polycrystalline silicon film, 6 is an inter-gate insulating film, 7 is a polycrystalline silicon film, 8 is a silicon nitride film, 9 is a mask pattern, and 9a is a carbon film (carbon-containing film). 9b is a core material pattern portion, 12 is an SOG film, 13 and 15 are resist patterns, 14 is an amorphous silicon film (spacer film), 14a and 14b are spacer patterns, 14c is an isolated pattern portion, 16 is an isolated mask pattern, MG Is a gate electrode, and PG is an isolated gate electrode.

Claims (5)

Forming a carbon-containing film made of a material containing carbon (C) on a workpiece;
Patterning the carbon-containing film from the upper surface to an intermediate depth to form a core material pattern portion; and
Forming a mask film having a predetermined thickness so as to cover the upper surface and side surfaces of the core material pattern portion and the upper surface of the carbon-containing film;
Etching back the mask film to expose the upper surface of the core material pattern portion and the upper surface of the carbon-containing film to form a mask pattern on the sidewall of the core material pattern portion;
Etching the core pattern portion and the carbon-containing film so that the mask pattern is transferred to the carbon-containing film. A method for manufacturing a semiconductor device, comprising: Forming a carbon-containing film made of a material containing carbon (C) on a workpiece;
Patterning the carbon-containing film from the upper surface to an intermediate depth to form a core material pattern portion at a predetermined interval; and
Forming a mask film having a predetermined thickness so as to cover the upper surface and side surfaces of the core material pattern portion and the upper surface of the carbon-containing film;
Forming a resist pattern at a position different from the core material pattern portion on the mask film;
After forming the resist pattern, the mask film is etched back to expose the upper surface of the core material pattern portion and the upper surface of the carbon-containing film excluding the resist pattern portion, thereby forming a sidewall of the core material pattern portion. And forming a mask pattern in the resist pattern portion;
Etching the core pattern portion and the carbon-containing film so that the mask pattern is transferred to the carbon-containing film. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the workpiece is an electrode film formed on a semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the workpiece is a groove processing layer of a surface layer portion of a semiconductor substrate or a composite layer including the groove processing layer and an insulating film and a conductive film formed on an upper surface of the groove processing layer. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the carbon-containing film is a carbon film formed by a chemical vapor deposition (CVD) method.

Images