JP2001326287A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a pattern capable of being easily applied to patterning of a floating gate electrode of a floating gate type transistor, by enabling a microminiaturization of the pattern of a resolution limit or more of a photolithographic technique by a simple method. SOLUTION: A method for manufacturing a semiconductor device comprises the step of patterning an inorganic insulating film of a lower part of a dry etching mask in a sectional taper-like state with a transfer pattern of a photosensitive resin film formed in a photolithographic step as the etching mask. The method also comprises the steps of patterning a material film of a lower part of the mask with the inorganic insulating film of a sectional taper-like state as an etching mask or etching on the way of a thickness of the material film, then thermally oxidizing it, converting its residue to an oxide, and patterning the material film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a simple method of transferring a pattern having a resolution equal to or less than the resolution limit of a photolithography technique.

[0002]

2. Description of the Related Art At present, in a manufacturing process of a semiconductor device, a photolithography technique is used to form a pattern on a semiconductor substrate. In the photolithography technique, a reticle pattern is usually transferred onto a semiconductor substrate coated with a photosensitive resin film such as a resist film by a reduction projection exposure apparatus, and a resist mask having a predetermined pattern is obtained by development. In such a photolithography technique, as is generally well known as a Rayleigh equation, a limit resolution R (a dimension of a limit fine pattern that can be resolved) is R = K1 × λ / NA.
(Where K1 is a constant that depends on processes such as the performance of the photosensitive resin). In this case, the depth of focus (the range in which the shift of the focal position is allowable) DOF is DOF = K
2 × λ / NA ² (where K2 is a process-dependent constant). Here, λ is the exposure wavelength, and NA is the numerical aperture of the projection lens system.

In order to form a fine pattern by reducing the critical resolution R, the exposure wavelength is shortened and the numerical aperture is increased. However, increasing the NA or shortening the wavelength reduces the depth of focus. The current photolithography technology uses a KrF excimer laser (wavelength: 248 nm) as an exposure source and increases the NA (NA: about 0.6) to produce a semiconductor device with a minimum pattern of 0.18 μm. I have to.

[0004] Semiconductor devices include memory devices such as DRAMs and logic devices. Among them, a flash memory (hereinafter referred to as a flash EEPROM) having a floating gate transistor structure has been widely used as a nonvolatile memory element capable of writing and erasing information. In this flash EEPROM, source and drain regions are provided on a semiconductor surface, and a channel region is formed between the source and drain regions. Then, a first insulating film, a floating gate electrode, which are sequentially formed on the channel region,
A second insulating film and a control gate electrode are formed, and a so-called floating gate transistor is formed. Usually, in this floating gate type transistor, a floating gate electrode is formed on a silicon oxide film on the main surface of a semiconductor substrate, and a composite insulating film of a silicon oxide film and a silicon nitride film is provided on the floating gate electrode. Then, a control gate electrode is formed on the interlayer insulating film.

In particular, in a floating gate transistor constituting a flash EEPROM, it is essential to increase the occupancy of the floating gate electrode. And a simple and reliable method is desired. In view of the above, various methods for compensating for the above-described photolithography technology and for transferring a pattern having a smaller resolution than the resolution limit of the photolithography technology, that is, the above-described R, have been studied.

For example, after a resist mask having a predetermined pattern is formed in a photolithography process, an organic film is formed on the side wall of the resist mask, and the size of the organic film is smaller than the size of the transfer pattern formed in the photolithography process. The method of conversion is described in JP-A-62-120030 or JP-A-11-186230.

[0007] The technique described in Japanese Patent Application Laid-Open No. 62-120030 will be described below with reference to FIG. FIG.
3A to 3C are cross-sectional views in the order of manufacturing steps when this method is applied to the formation of the floating gate electrode.

[0008] As shown in FIG.
An element isolation insulating film 102 is formed in a predetermined region on the surface of the device. Here, the element isolation insulating film 102 is formed in the trench. Then, a tunnel oxide film 103 having a thickness of about 10 nm is formed on the surface of the silicon substrate 101. Further, a polycrystalline silicon film 104 containing a phosphorus impurity is formed on the tunnel oxide film 103. Then, in order to form the floating gate electrode, a resist mask 105 for the floating gate electrode is formed on the polycrystalline silicon film 104 by a photolithography technique.

Next, an organic film is deposited on the entire surface so as to cover the surface of the resist mask 105 and the exposed portion of the polycrystalline silicon film 104. Then, etch back is performed by known reactive ion etching (RIE), and FIG.
As shown in (b), a sidewall mask 106 is formed on the side wall of the resist mask 105. In the RIE in this etch-back step, oxygen (O ₂ ) is used as a reaction gas.

Next, as shown in FIG. 7C, the polycrystalline silicon film 104 is dry-etched using the resist mask 105 and the sidewall mask 106 as an etching mask. Thus, the floating gate electrode pattern 107 is formed.

Then, a resist mask 105 and a side wall mask 106 used as a mask for the above etching are used.
Is removed. In this way, as shown in FIG. 7D, a gate electrode pattern 107 is formed on the surface of the tunnel oxide film 103 on the silicon substrate 101. Hereinafter, as described later, the gate electrode pattern 10 is used.
7 is again patterned by dry etching to form a final floating gate electrode.

In any case, in the above method, FIG.
The space dimension between the resist masks 105 shown in FIG.
However, as shown in FIG. 7D, the space dimension between the completed floating gate electrode patterns 107 is d2, and the value of d2 is smaller than the value of d1. This difference is twice the width of the sidewall mask 106. In this manner, pattern transfer having a space equal to or less than the resolution limit of the photolithography technique can be performed.

[0013]

In the method using the above-mentioned conventional technique, a plasma-excited oxygen active species is used as an etching gas in an etch-back step for forming the sidewall mask 106. For this reason, when the polycrystalline silicon film 104 is exposed by RIE of the organic film formed on the entire surface, its surface is exposed to the above-mentioned oxygen active species to form a silicon oxide film. Then, when processing the polycrystalline silicon film in the RIE process of FIG. 7C, the silicon oxide film formed by the oxygen active species becomes a hindrance to etching, and uniform processing becomes difficult.

Further, the above-mentioned Japanese Patent Application Laid-Open No. 11-186230
In the method of applying the technique described in Japanese Patent Application Laid-Open Publication No. H10-107,197 to the formation of the floating gate electrode pattern 107, the surface of the polycrystalline silicon film serving as the floating gate electrode is used in plasma deposition for reducing the size of the transfer pattern. Also, a deposit such as an organic polymer is formed. For this reason, the technique of the above-mentioned publication cannot be applied at all.

An object of the present invention is to provide a method of manufacturing a semiconductor device which facilitates fine processing of a pattern below the resolution limit of the photolithography technique by a simple method, and a nonvolatile memory such as a flash EEPROM. It is another object of the present invention to provide a pattern forming method which can be easily applied to patterning of a floating gate electrode.

[0016]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises, in processing for forming a semiconductor element, forming an inorganic insulating film and a photosensitive resin film on a material film to be processed in this order. And forming a predetermined first pattern on the photosensitive resin film, and further using the photosensitive resin film on which the first pattern is formed as an etching mask to form the inorganic insulating film. Dry etching such that the cross section thereof has a forward tapered shape, forming a second pattern having a size smaller than the size of the first pattern in a lower region of the inorganic insulating film; Patterning the material film by dry etching using the formed inorganic insulating film as an etching mask. Here, in the step of patterning the material film, a cross-sectional shape of the material film is formed in a forward tapered shape.

Alternatively, in a method of manufacturing a semiconductor device according to the present invention, in a process for forming a semiconductor element, a step of laminating an inorganic insulating film and a photosensitive resin film on a material film to be processed in this order. And a predetermined first material on the photosensitive resin film.
Is formed, and the inorganic insulating film is dry-etched using the photosensitive resin film on which the first pattern is formed as an etching mask so that the cross section thereof becomes a forward tapered shape. Forming a second pattern having a size smaller than that of the inorganic insulating film in a lower region of the inorganic insulating film; and dry-etching using the inorganic insulating film on which the second pattern is formed as an etching mask. Etching the material film halfway through the film thickness such that the cross section of the material becomes forward tapered;
Removing the inorganic insulating film on which the second pattern is formed, performing thermal oxidation on the material film etched halfway through the film thickness, and converting the remaining portion of the etching process into oxide to pattern the oxide film. including.

Here, the material film is a conductor film composed of a polycrystalline silicon film or a polycrystalline silicon-germanium alloy film. Alternatively, the material film is formed of an amorphous silicon film or an amorphous silicon-germanium alloy film. Further, the inorganic insulating film is formed of a silicon nitride film.

In the present invention, the patterned material film is used as a floating gate electrode of a floating gate type transistor, and the floating gate type transistor is used as a memory cell of a flash memory.

As described above, according to the method of the present invention, a tapered mask smaller in size than the transfer pattern formed in the photolithography step can be easily formed on the base material film to be etched. Here, the tapered mask is formed of an inorganic insulating film. Then, the underlying material film is processed by dry etching using the tapered mask having the reduced pattern as an etching mask. In this manner, a pattern having a size smaller than the resolution limit of the photolithography technique can be formed on the underlying material film.

When the floating gate electrode of the memory cell constituting the flash EEPROM is formed by the method of the present invention, the dimension between the adjacent floating gate electrodes can be easily reduced to the resolution limit of the photolithography technique, and the flash EEPROM is formed. It becomes easy to achieve ultra-high integration. In addition, the capacitance value of the floating gate electrode is increased,
The operating performance of the flash EEPROM is greatly improved.
In particular, the operating voltage for writing and erasing is reduced.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view and a sectional view of a flash EEPROM to which the present invention is applied.
Here, FIG. 1B is a cross-sectional view taken along a line AB shown in FIG. 1A. In FIG. 1A, the floating gate electrode is hatched for clarity. And FIG.
FIG. 3 is a cross-sectional view in the order of manufacturing steps. First Flash EEP
The ROM will be described.

As shown in FIGS. 1 (a) and 1 (b),
An element isolation insulating film 2 is formed in a surface region of a silicon substrate 1 of one conductivity type. Then, a first insulating film 3 is formed on the entire surface by a silicon oxide film having a thickness of about 10 nm, and a floating gate electrode 4 is formed on the first insulating film 3. Here, the floating gate electrode 4 has an isolated rectangular pattern as shown in FIG. Then, a control gate electrode 6 is formed on the second insulating film 5 covering the floating gate electrode 4. Further, as shown in FIG. 1A, a diffusion layer 7 of the opposite conductivity type is formed to face the floating gate electrode 4 so as to face the source / drain region of the floating gate transistor. Further, an interlayer insulating film 8 covering the entire surface
Are formed, and although not shown, a wiring layer is formed to complete a flash EEPROM.

Here, if the flash EEPROM is designed with a minimum dimension of 0.18 μm determined by the photolithography technique, the dimensions of the above-mentioned rectangular floating gate electrode 4 have a long side of about 500 nm and a short side of about 200 nm. become. Then, it is necessary to make the space D between the floating gate electrodes 4 shown in FIG. 1A less than the resolution limit by photolithography.

Next, the pattern forming method of the present invention will be described with reference to FIG. Here, the same components as those in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2A, the silicon substrate 1
An element isolation insulating film 2 is formed in a predetermined region on the surface by a trench element isolation method. Then, a first insulating film 3 is formed on the surface of the silicon substrate 1 with a silicon oxide film having a thickness of about 10 nm. Further, a polycrystalline silicon film 9 containing a phosphorus impurity is formed on the first insulating film 3. Here, the thickness of the polycrystalline silicon film 9 is 100 nm. Then, a transfer insulating film 10 which is an inorganic insulating film laminated on the polycrystalline silicon film 9 is deposited. Here, the insulating film for transfer 1
As 0, a silicon nitride film having a thickness of 40 nm is used.

Next, as shown in FIG. 2B, a resist mask 11, which is a photosensitive resin film, is pattern-transferred to the surface of the transfer insulating film 10 by reduction projection exposure using a KrF excimer laser. Here, the space between the patterns is d1, and this value is about 0.2 μm.

Next, a mixed gas of CHF ₃ , Ar, and O ₂ is plasma-excited, and the transfer insulating film 10 is dry-etched using the resist mask 11 as an etching mask. In this way, a tapered mask 12 having a tapered cross section as shown in FIG. 2C is formed. here,
The taper angle is set to be 45 degrees. The pattern dimension, that is, the space dimension of the lower region of the tapered mask 12 in contact with the polycrystalline silicon film 9 is 0.12 μm.

Next, a mixed gas of Cl ₂ , HBr, and O ₂ is plasma-excited, and the polycrystalline silicon film 9 is dry-etched using the tapered mask 12 as an etching mask. In this way, as shown in FIG. 2D, the floating gate electrode pattern 13 is formed. Here, FIG.
As shown in (d), the space d3 between the adjacent floating gate electrode patterns 13 is smaller than the value d1. This dimension is substantially the same as the pattern dimension in the lower region of the tapered mask 12 described above.

Then, the tapered mask 12 is removed with a chemical solution. In this way, as shown in FIG.
The floating gate electrode pattern 13 is formed on the surface of the first insulating film 3 on the silicon substrate 1.

Thereafter, the second insulating film 5 described with reference to FIG. 1 is formed. The second insulating film 5 is a silicon oxide film having a thickness of 10 nm / a silicon nitride film having a thickness of 8 nm / a film thickness of 10 n.
m is a laminated insulating film of a silicon oxide film. And FIG.
The control gate electrode 6 shown in FIG. 1A is formed by patterning, and the control gate electrode 6 is used as an etching mask to dry-etch the floating gate electrode pattern 13 again to form the final floating gate electrode 4. become.

According to the present invention, as described with reference to FIG. 2D, the space d3 between the floating gate electrode patterns 12 is used.
Is about 80 nm smaller than the d1 value. As a result, the long side dimension of the floating gate electrode 4 in the state shown in FIG.
It increases from 00 nm to 580 nm. For this reason, the surface area of the floating gate electrode 4 increases by about 15%, and the floating gate electrode 4 and the control gate electrode 6 shown in FIG.
Is used as the counter electrode, and the capacitance value of the capacitor using the second insulating film as the capacitive insulating film is increased by about 15%. Therefore, the operation performance of the flash EEPROM is improved. For example, it becomes easy to lower the voltage of the operation of writing and erasing information or to improve the operation speed. Also, according to the present invention, the size between the floating gate electrodes is reduced, and the flash EE
Ultra-high integration of the PROM is facilitated.

Next, a second embodiment of the present invention will be described with reference to FIGS. Here, the same components as those in FIG. 1 are denoted by the same reference numerals. A feature of this embodiment is that the floating gate electrode pattern as described above is also formed to have a tapered cross section.

As shown in FIG. 3A, an element isolation insulating film 2 is formed in a predetermined region on the surface of the silicon substrate 1 as in the first embodiment. Then, a first silicon oxide film is used.
Is formed on the surface of the silicon substrate 1. Further, an amorphous silicon film 14 containing a phosphorus impurity is formed on the first insulating film 3. Here, the thickness of the amorphous silicon film 14 is 100 nm. The transfer insulating film 10 which is an inorganic insulating film laminated on the amorphous silicon film 14
Is deposited. Here, a silicon nitride film having a thickness of 30 nm is used as the transfer insulating film 10.

Next, as shown in FIG. 3B, a resist mask 11 is pattern-transferred to the surface of the transfer insulating film 10. Here, the space between the patterns is d1, and this value is about 0.2 μm.

Next, as in the first embodiment, the CHF
_3. A mixed gas of Ar and O ₂ is plasma-excited, and the transfer insulating film 10 is dry-etched using the resist mask 11 as an etching mask. Thus, FIG.
A tapered mask 12 having a tapered cross section as shown in FIG. Here, the taper angle is set to be 45 degrees. The pattern dimension interval in the lower region of the tapered mask 12 in contact with the surface of the amorphous silicon film 14 is 0.14 μm.

Next, Cl ₂ , HBr, O ₂ , CH ₃ Cl
Is excited by plasma, and the tapered mask 12
Is used as an etching mask to dry-etch the amorphous silicon film 14 into a tapered shape. In this way,
As shown in FIG. 3D, a floating gate electrode pattern 15 having a tapered cross section is formed. In this dry etching step, the tapered surface of the floating gate electrode pattern 15 can be formed so as to be smooth. This is because in the dry etching of the amorphous silicon film 14, unlike in the case of the dry etching of the polycrystalline silicon film, since there is no crystal grain boundary, the surface after the etching becomes very smooth.

In this way, as shown in FIG. 3D, the space d4 between the lower regions of the adjacent floating gate electrode patterns 15 becomes smaller than the value d1. In this case, the value of d4 is about 80 nm. That is, the d4 value is reduced by about 120 nm from the d1 value.

Then, the tapered mask 12 is removed with a chemical solution. In this way, as shown in FIG.
A floating gate electrode pattern 15 having a tapered cross section is formed on the surface of the first insulating film 3 on the silicon substrate 1. Then, a heat treatment is performed to form the floating gate electrode pattern 15 into a polycrystalline structure.

Thereafter, as shown in FIG. 4B, a second insulating film 5 is formed, a control gate electrode 6 is patterned, and a floating gate electrode pattern is formed in the same manner as described in the first embodiment. 15 is again dry-etched to form the final floating gate electrode 4a. Then, an interlayer insulating film 8 is deposited on the entire surface.

According to the present invention, as described with reference to FIG. 3D, the space d4 between the floating gate electrode patterns 15 is formed.
Is about 120 nm smaller than the d1 value. As a result,
The long side dimension of the floating gate electrode 4 in the state shown in FIG. 4B increases from 500 nm to 620 nm. For this reason, the surface area of the floating gate electrode 4a increases by about 25%, and the capacitance value of the capacitor increases by about 25%. For this reason, the operation performance of the flash EEPROM is further improved as compared with the case described in the first embodiment.

Next, a third embodiment of the present invention will be described with reference to FIGS. Here, the same components as those in FIGS. 3 and 4 are denoted by the same reference numerals. A feature of the present embodiment is that in the formation of the floating gate electrode pattern described above, separation by oxidation of an amorphous silicon film is also used.

As shown in FIG. 5A, an element isolation insulating film 2 is formed in a predetermined region on the surface of a silicon substrate 1 as in the second embodiment. Then, a first insulating film 3 is formed on the surface of the silicon substrate 1, and an amorphous silicon film 14 containing a phosphorus impurity is formed on the first insulating film 3. And
Transfer insulating film 1 laminated on this amorphous silicon film 14
0 is deposited, and a tapered mask 12 having a tapered cross section is formed by dry etching.

Next, Cl ₂ , HBr, O ₂ , CH ₃ Cl
Is excited by plasma, and the tapered mask 12
Is used as an etching mask to dry-etch the amorphous silicon film 14 into a tapered shape. Here, unlike the case of the second embodiment, the amorphous silicon film 14 is not completely separated by etching. As shown in FIG. 5A, adjacent floating gate electrode patterns 15 a are connected by an etching residue 16.

Then, the tapered mask 12 is removed with a chemical solution. In this way, as shown in FIG.
On the surface of the first insulating film 3 on the silicon substrate 1, a floating gate electrode pattern 15a having a tapered cross section is formed without being separated.

Next, the surface of the unseparated floating gate electrode pattern 15a is thermally oxidized. Here, the oxidation temperature is about 850 ° C. In this process, as shown in FIG. 5C, the silicon in the above-mentioned remaining etching part 16 is converted into a thermal oxide film 17 which is a silicon oxide film. A thermal oxide film 17 is formed on the surface of the floating gate electrode pattern 15a, and at the same time, the structure changes to a polycrystalline silicon structure. Floating gate electrode pattern 15a separated from each other by this thermal oxidation process
The space between them is about 40 nm.

Next, the thermal oxide film 17 is removed by etching with a chemical solution, and as shown in FIG. 6A, the second insulating film 5 is formed so as to cover the surface of the oxidized and separated floating gate electrode pattern 15a. To form Thereafter, as shown in FIG. 6B, the control gate electrode 6 is patterned to form the floating gate electrode pattern 1 in the same manner as described in the second embodiment.
5a is again dry-etched and the final floating gate electrode 4
a will be formed. Then, an interlayer insulating film 8 is formed on the entire surface.
Is deposited.

According to the present invention, as described with reference to FIG. 5C, the floating gate electrode patterns 15a are separated by thermal oxidation, and the spacing is about 40 nm. As a result,
The long side dimension of the floating gate electrode 4a in the state shown in FIG. 6B further increases from 500 nm to 660 nm. For this reason, the surface area of the floating gate electrode 4a increases by about 30%, and the capacitance value of the above-described capacitor increases by about 30%. For this reason, the operation performance of the flash EEPROM is further improved as compared with the case described in the second embodiment.

In the third embodiment, the thermal oxide film 17 described with reference to FIG. 5C may have a thickness of about 10 nm and may be used as a second insulating film without being removed by etching. With this method, the space between the floating gate electrodes 4a is further narrowed, and the capacitance value of the above-described capacitor is increased.

In the embodiment of the present invention, the case where the present invention is applied to formation of a floating gate electrode of a flash EEPROM is described. The application of the pattern forming method of the present invention is not limited to a flash EEPROM. In addition, the pattern forming method of the present invention can be similarly applied to patterning of a conductor material or an insulator material used for a semiconductor device. For example, the present invention can be similarly applied to a case where a lower electrode of a capacitor used in a semiconductor device is formed.

It should be noted that the present invention is not limited to the above embodiments, and it is apparent that each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

[0052]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the transfer pattern of the photosensitive resin film formed in the photolithography process is used as a dry etching mask, and the inorganic insulating film thereunder is patterned into a tapered cross section. I do. Then, using the inorganic insulating film having a tapered cross section as an etching mask, the material film thereunder is patterned. Alternatively, after etching the material film halfway through the film thickness, the material film is patterned by performing thermal oxidation to convert the remainder to an oxide.

In this manner, a pattern having a size smaller than the resolution limit of the photolithography technique can be formed on the underlying material film.

When the floating gate electrode of the memory cell constituting the flash EEPROM is formed by the method of the present invention, the dimension between the adjacent floating gate electrodes can be easily reduced below the resolution limit of the photolithography technique. It becomes easy to achieve ultra-high integration. In addition, the capacitance value of the floating gate electrode is increased,
The operating performance of the flash EEPROM is greatly improved.

The information charge retention characteristics of the flash EEPROM are improved, and the number of times of writing and erasing of the information charge is increased, which is effective in improving the performance of the nonvolatile semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a flash EEPROM for explaining the present invention.
M and M are a plan view and a sectional view.

FIGS. 2A and 2B are cross-sectional views illustrating a first embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view illustrating a second embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a sectional view illustrating a second embodiment of the present invention in the order of manufacturing steps.

FIG. 5 is a sectional view illustrating a third embodiment of the present invention in the order of manufacturing steps.

FIG. 6 is a sectional view illustrating a third embodiment of the present invention in the order of manufacturing steps.

FIG. 7 is a cross-sectional view in the order of manufacturing steps for explaining a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1,101 Silicon substrate 2,102 Element isolation insulating film 3 First insulating film 4,4a Floating gate electrode 5 Second insulating film 6 Control gate electrode 7 Diffusion layer 8 Interlayer insulating film 9,104 Polycrystalline silicon film 10 Transfer Insulating film 11, 105 Resist mask 12 Tapered mask 13, 15, 15a, 107 Pattern for floating gate electrode 14 Amorphous silicon film 16 Residual etching 17 Thermal oxide film 103 Tunnel oxide film 106 Side wall mask d1, d2, d3, d4, D space

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/28 301 H01L 21/302 L 21/3065 27/10 434 27/115 F term (reference) 4M104 AA01 BB01 CC05 DD08 DD12 DD17 DD62 DD65 DD66 DD71 DD74 DD78 DD86 DD88 EE15 EE17 FF08 GG16 HH14 5F001 AA02 AA04 AA25 AA30 AA43 AA63 AB02 AE08 AG02 AG28 5F004 AA16 DA00 DA04 DA16 DA23 DA26 DB02 DB07 EF08 EP03 EP03 EP03 EP03 EP02 PR12

Claims (9)

[Claims] In a process for forming a semiconductor element, an inorganic insulating film and a photosensitive resin film are laminated and formed in this order on a material film to be processed, and a predetermined process is performed on the photosensitive resin film. Forming a first pattern, further using the photosensitive resin film on which the first pattern is formed as an etching mask, dry-etching the inorganic insulating film so that a cross section thereof is forward-tapered; Forming a second pattern having a size smaller than the size of the pattern in the lower region of the inorganic insulating film, and dry etching using the inorganic insulating film on which the second pattern is formed as an etching mask. Patterning a film. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein in the step of patterning the material film, a cross-sectional shape of the material film is formed in a forward tapered shape. 3. A process for forming a semiconductor element by laminating an inorganic insulating film and a photosensitive resin film on a material film to be processed in this order, and forming a predetermined film on the photosensitive resin film. Forming a first pattern, further using the photosensitive resin film on which the first pattern is formed as an etching mask, dry-etching the inorganic insulating film so that a cross section thereof is forward-tapered; Forming a second pattern having a size smaller than the size of the pattern in a lower region of the inorganic insulating film, and dry-etching using the inorganic insulating film on which the second pattern is formed as an etching mask, A step of etching the material film to an intermediate thickness so that the cross section of the material film has a forward tapered shape, and after removing the inorganic insulating film on which the second pattern is formed, Subjecting the material film etched to the middle of the film thickness to thermal oxidation, and converting the remainder of the etching process to an oxide and patterning the oxide. 4. The method for manufacturing a semiconductor device according to claim 1, wherein said material film is a conductor film. 5. The method according to claim 4, wherein the conductor film is a polycrystalline silicon film or a polycrystalline silicon-germanium alloy film. 6. The method for manufacturing a semiconductor device according to claim 1, wherein said material film is an amorphous silicon film or an amorphous silicon-germanium alloy film. 7. The method of manufacturing a semiconductor device according to claim 4, wherein said patterned material film is used as a floating gate electrode of a floating gate type transistor. 8. The method of manufacturing a semiconductor device according to claim 4, wherein said inorganic insulating film is formed of a silicon nitride film. 9. The method for manufacturing a semiconductor device according to claim 4, wherein said floating gate type transistor is a memory cell of a flash memory.