KR100442152B1 - Method for manufacturing floating gate of nonvolatile memory cell - Google Patents

Abstract

The present invention relates to a method of manufacturing a floating gate of a nonvolatile memory cell, and in particular, the method of manufacturing a tunnel oxide film on a semiconductor substrate, sequentially depositing a conductive film, a buffer oxide film, and a hard mask film on the tunnel oxide film, and a hard mask. Forming a first mask pattern defining the first and second surfaces of the floating gate on top of the film, patterning the hard mask film exposed by the first mask pattern by an inclined dry etching process, and then removing the first mask pattern, The buffer oxide layer and the conductive layer exposed by the patterned hard mask layer are patterned by an etching process, and a second mask pattern defining third and fourth surfaces of the floating gate is formed in the resultant, and the hard mask exposed by the second mask pattern is formed. After the film, the buffer oxide film, and the conductive film are patterned by a dry etching process, the second mask pattern is removed. Therefore, according to the present invention, the floating gate is etched inclined immediately without forming a spacer during the first patterning of the floating gate to secure a micro space, thereby eliminating the process of manufacturing the buffer oxide layer and the hard mask layer on the gate.

Description

Floating gate manufacturing method of nonvolatile memory cell {METHOD FOR MANUFACTURING FLOATING GATE OF NONVOLATILE MEMORY CELL}

The present invention relates to a method of manufacturing a nonvolatile memory, and more particularly to a method of manufacturing a floating gate of a nonvolatile memory cell.

In general, non-volatile memory has the advantage that the stored data is not lost even if the power is interrupted, so it is widely used for data storage such as PC Bios, Set-top Box, printer, and network server. It is used a lot.

Among such nonvolatile memories, an electrically erasable programmable read-only memory (EEPROM) type flash memory device that has a function of electrically erasing data of memory cells in a batch or sector-by-sector is a channel column electronic device on a drain side during programming. The threshold voltage of the cell transistor is increased by forming hot electrons to accumulate electrons in the floating gate. On the other hand, the erase operation of the flash memory device lowers the threshold voltage of the cell transistor by generating a high voltage between the source / substrate and the floating gate to release electrons accumulated in the floating gate.

On the other hand, the design rules are gradually reduced according to the high integration of the semiconductor device, which makes it difficult to implement the fine pattern of the device. Accordingly, even in the manufacturing process of the nonvolatile memory cell, it is difficult to secure the space margin between the floating gates due to the reduction of the design rule. If the space margin between the floating gate electrode is small, a spacer made of an insulating material is formed at the gate side position.

1 is a plan view illustrating a floating gate of a nonvolatile memory cell according to the prior art.

Referring to FIG. 1, spacers 40 made of an insulating material are formed on both sidewalls of the hard mask layer 34 ″ positioned above the floating gate patterned in a rectangular shape on the tunnel oxide layer 20. The spacer 40 is formed on the side of the hard mask film 34 '' to secure a narrow space between the floating gates.

In the conventional manufacturing process of the floating gate, the floating gate is patterned by a photo-etching process using two mask patterns (the length direction / the width direction of the gate) using the spacer 38 to secure a fine pattern. Detailed description thereof will be made with reference to the following drawings.

2A to 2E are process flowcharts for manufacturing a floating gate of a nonvolatile memory cell according to an exemplary embodiment of the prior art, and FIGS. 2A and 2B illustrate a structure of a gate cut by the line AA ′ of FIG. 1. 2C to 2E show a structural cross section of the gate cut by the line BB ′ of FIG. 1.

First, as shown in FIG. 2A, a tunnel oxide film 20 is formed over the silicon substrate as the semiconductor substrate 10. Then, a polysilicon film is formed as the conductive film 30 on the tunnel oxide film 20, and the buffer oxide film 32 and the hard mask film 34 are sequentially stacked thereon. Then, the first photolithography process is performed to define the first mask pattern 36 defining the first and second surfaces of the floating gate (for example, the surface corresponding to the width direction of the gate) on the hard mask layer 34. ).

As shown in FIG. 2B, after the hard mask layer 34 exposed by the first mask pattern 36 is patterned 34 ′ by a dry etching process, the first mask pattern 36 is removed. A silicon nitride film is formed as an insulating material on the entire surface of the resultant surface having the hard mask layer 34 'patterned on only the surface corresponding to the width direction of the floating gate, and the wafer is etched by dry etching to form spacers on both sides of the hard mask layer pattern 34'. (38) is formed.

Next, as shown in FIG. 2C, the buffer oxide film 32 and the conductive film at a position corresponding to the surface corresponding to the width direction of the floating gate using the hard mask pattern 34 ′ and the spacer 38 as a mask. 30 is sequentially patterned 32 'and 30' to provide a vertical space between floating gates as shown in FIG.

Subsequently, as shown in FIG. 2D, the resultant is subjected to the second photographic process again to correspond to the third and fourth surfaces of the floating gate (eg, in the longitudinal direction of the gate) on the hard mask layer 34 ′. The second mask pattern 39 is formed.

Then, as shown in FIG. 2E, the surface corresponding to the longitudinal direction of the floating gate after patterning 34 ″ the hard mask layer 34 ′ exposed by the second mask pattern 39 again by a dry etching process is performed. The buffer oxide film 32 'and the conductive film 30' under the patterned hard mask film 34 '' are etched by dry etching. As a result, the buffer oxide film 32 'and the conductive film 30' at positions corresponding to the lengthwise direction of the floating gate are sequentially patterned 32 " and 30 " Provide some space. Then, the second mask pattern 39 is removed.

In the conventional method of manufacturing a floating gate, a narrow pattern is formed between the gates, and the floating gate can be patterned precisely by performing two mask pattern processes, but the surface of the floating gate due to excessive dry etching during the spacer manufacturing process There was a problem that a small hole is formed in the property to deteriorate.

In addition, the conventional floating gate manufacturing method is a manufacturing process, such as forming a buffer oxide film, a hard mask film on the floating gate, and even a spacer.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the manufacturing process by obliquely patterning a hard mask film using a first mask pattern and forming a floating gate by the patterned hard mask film in order to solve the problems of the prior art. Disclosed is a method of manufacturing a floating gate of a volatile memory cell.

In order to achieve the above object, the present invention provides a method of manufacturing a floating gate of a nonvolatile memory cell, the method comprising: forming a tunnel oxide film on a semiconductor substrate, sequentially depositing a conductive film, a buffer oxide film, and a hard mask film on the tunnel oxide film; . Forming a first mask pattern defining first and second surfaces of the floating gate on the hard mask layer, and patterning the hard mask layer exposed by the first mask pattern by an inclined dry etching process Removing the first mask pattern, patterning the buffer oxide layer and the conductive layer exposed by the patterned hard mask layer by an etching process, and defining the third and fourth surfaces of the floating gate in the resultant product. Forming a second mask pattern, and removing the second mask pattern after patterning the hard mask layer, the buffer oxide layer, and the conductive layer by the dry etching process.

1 is a plan view illustrating a floating gate of a nonvolatile memory cell according to the prior art;

2A to 2E are process flowcharts for manufacturing a floating gate of a nonvolatile memory cell according to one embodiment of the prior art;

3 is a plan view showing a floating gate of a nonvolatile memory cell according to the present invention;

4A-4E are process flow diagrams for manufacturing a floating gate of a nonvolatile memory cell in accordance with one embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a plan view illustrating a floating gate of a nonvolatile memory cell according to the present invention. Referring to FIG. 3, the hard mask layer 108 ′ patterned in a rectangular shape on the buffer oxide layer 106 has a structural surface 108a inclined so that both sidewalls are widened downward in the longitudinal direction or the width direction. Therefore, according to the present invention, by narrowly etching the side surface (lengthwise or vertically) of the hard mask film 108 ', a narrow space between the floating gate patterns can be secured finely without forming a spacer.

4A to 4F are process flowcharts for manufacturing a floating gate of a nonvolatile memory cell according to an exemplary embodiment of the present invention, and FIGS. 4A and 4C are structures of a gate cut by line AA ′ of FIG. 3. 4D to 4F show the structural cross section of the gate cut by the line BB ′ of FIG. 3.

First, as shown in FIG. 4A, a tunnel oxide film 102 is formed over the silicon substrate as the semiconductor substrate 100. Then, a polysilicon film is formed as the conductive film 104 on the tunnel oxide film 102, and the buffer oxide film 106 and the hard mask film 108 are sequentially stacked thereon. Then, the first photolithography process is performed to define the first mask pattern 110 defining the first and second surfaces of the floating gate (eg, a surface corresponding to the width direction of the gate) on the hard mask layer 108. ).

As shown in FIG. 4B, after the hard mask layer 108 exposed by the first mask pattern 110 is patterned 108 ′ by an inclined dry etching process, the first mask pattern 110 is removed. In this case, the dry etching process of the hard mask layer 108 may be performed using HBr, Cl, HeO 2 (O 2) gas to form an inclined hard mask layer pattern 108 ′.

The inclination angle of the hard mask layer pattern 108 ′ may be adjusted by changing the conditions of the dry etching process of the hard mask layer 108. In the process described below using the inclination angle of the hard mask layer pattern 108 ′. The space between the floating gates may be adjusted.

Subsequently, as shown in FIG. 4C, the buffer oxide film 106 and the conductive film 104 are sequentially patterned at positions corresponding to the surface corresponding to the width direction of the floating gate, using the hard mask film pattern 108 ′ as a mask. (106 ', 104'). For this reason, the vertical space between the floating gates as shown in 105 in FIG. 3 is provided by the inclined hard mask film pattern 108 'in which the first and second surfaces of the floating gates are patterned.

Subsequently, as shown in FIG. 4D, the resultant is subjected to the second photographic process again, and the third and fourth surfaces of the floating gate (eg, in the longitudinal direction of the gate) are disposed on the hard mask layer pattern 108 ′. A second mask pattern 112 defining a corresponding surface) is formed.

Then, as shown in FIG. 4E, after the hard mask layer 108 ′ exposed by the second mask pattern 112 is patterned (108 ″) again by a dry etching process, a surface corresponding to the length direction of the floating gate is formed. The buffer oxide film 106 'and the conductive film 104' under the patterned hard mask film 108 " are etched by dry etching. As a result, the buffer oxide film 106 'and the conductive film 104' at positions corresponding to the longitudinal direction of the floating gate are sequentially patterned 106 " and 104 " Provide some space. Then, the floating gate manufacturing process according to the present invention is completed by removing the second mask pattern 112.

On the other hand, in the above-described embodiment of the present invention, the first and second surfaces are designated to correspond to the longitudinal direction of the floating gate, and the third and fourth surfaces are designated to correspond to the width direction of the floating gate. The process may be performed by changing the second surface in the width direction or the third and fourth surfaces in the longitudinal direction.

As described above, according to the present invention, a micromask is secured by inclining the hard mask layer without forming spacers during the primary patterning of the floating gate, and by floating the buffer oxide layer and the conductive layer on the gate using the inclined hard mask layer to float. By securing the gate, the spacer manufacturing step can be omitted.

Therefore, the present invention can implement a highly integrated nonvolatile memory cell and simplify the manufacturing process.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (4)

In the method of manufacturing a floating gate of a nonvolatile memory cell, Forming a tunnel oxide film on the semiconductor substrate; A conductive film, a buffer oxide film, and a hard mask film are sequentially deposited on the tunnel oxide film. Forming a first mask pattern on the hard mask layer, the first mask pattern defining first and second surfaces of the floating gate; Removing the first mask pattern after patterning the hard mask layer exposed by the first mask pattern by an inclined dry etching process; Patterning the buffer oxide layer and the conductive layer exposed by the patterned hard mask layer by an etching process; Forming a second mask pattern on the resultant to define third and fourth surfaces of the floating gate; And And removing the second mask pattern after patterning the hard mask layer, the buffer oxide layer, and the conductive layer exposed by the second mask pattern by a dry etching process. . The nonvolatile memory of claim 1, wherein the first and second surfaces are surfaces corresponding to the longitudinal direction of the floating gate, and the third and fourth surfaces are surfaces corresponding to the width direction of the floating gate. Method for manufacturing a floating gate of a cell. The nonvolatile memory of claim 1, wherein the first and second surfaces are surfaces corresponding to a width direction of the floating gate, and the third and fourth surfaces are surfaces corresponding to a length direction of the floating gate. Method for manufacturing a floating gate of a cell. The method of claim 1, wherein the inclined dry etching process is performed using HBr, Cl, and HeO 2 (O 2) gases.