JPH09283643A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, wherein the operating speed of the device can be increased and moreover, the microscopic formation of the device is easy by making thin a conductive layer, and a method of manufacturing the device. SOLUTION: A semiconductor device is provided with a memory cell 7, which is provided with a floating gate 14 and a control gate 17 provided on the gate 14, a select transistor 8 provided with a select gate 21, a high- breakdown strength transistor 9 and a logic transistor 10 and the gates 17 and 21 and moreover, the transistors 9 and 10 are formed in such a way that the surfaces of the gates 17 and 21 and the surfaces of gates of the transistors 9 and 10 are respectively silicified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a conductive layer having a multi-layer structure and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art In a non-volatile memory such as EPROM or EEPROM, a floating gate is used as a first layer,
The control gate has a multilayer structure including the second layer. The floating gate and the control gate have conductivity and are formed of polysilicon (polycrystalline silicon containing impurities). In addition to the above gates, these layers are also used for the gates of peripheral circuits such as select transistors, high voltage transistors, and logic transistors.

On the other hand, in a semiconductor device provided with a logic integrated circuit (ROGIC / IC) in which the line width and the circuit unit are miniaturized, the silicidation technique is adopted to increase the operating speed. For example, the resistance of gates and electrodes is reduced by silicide technology such as polycide and salicide to speed up the operation.

[0004]

The nonvolatile memory having the above-mentioned floating gate (memory having a FLOATOX structure) is not required to have a very high operation speed in the conventional method of use, and it is not so important to speed it up. However, in a logic-embedded memory or the like, it is desired to increase the operation speed of the logic circuit, the peripheral circuit, and the memory. Therefore, miniaturization of line width and cell unit is required.
Further, miniaturization is desirable for power consumption.

However, the gate of polysilicon used in the conventional semiconductor device having a multilayer structure has a larger specific resistance than metal or the like, and a certain thickness is required to reduce the resistance. That is, in order to reduce the resistance, polysilicon is doped with phosphorus or the like to increase the concentration, but if the gate is thin, punch-through occurs.

Therefore, conventionally, the thickness of the polysilicon gate layer needs to be set to about 4000 angstroms. Therefore, even if the line width is made finer, the operating speed of the peripheral circuit cannot be increased.

Further, since the step between the multilayer portion and the wafer surface is large, the interlayer film is not flat. Therefore, when connecting a thin aluminum wire, it is easy to break, and it is difficult to miniaturize. Particularly, in the case of a multi-layer structure, the step difference from the wafer surface is larger than that of a single layer, and miniaturization is more difficult.

Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can increase the operating speed and can be easily miniaturized by thinning the conductive layer.

[0009]

According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate provided on a surface of a semiconductor substrate; and a conductive layer having a multi-layered structure protruding from the surface of the semiconductor substrate. Is characterized in that it is configured with a silicided portion.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the surface of the conductive layer is silicidized.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the conductive layer is configured as a floating gate and a control gate located above the floating gate, and the surface of the control gate is silicidized. It is characterized by

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Forming a conductive layer having a multi-layered structure in a predetermined pattern on a semiconductor substrate, forming a metal film covering the conductive layer, silicidizing the surface of the conductive layer in contact with the metal film, And a step of removing the metal film.

[0013]

According to the semiconductor device of the first aspect,
The multi-layered conductive layer projecting from the surface of the semiconductor substrate has a silicided portion.

Therefore, the electric resistance of the conductive layer can be reduced, and the operating speed can be increased. Further, since the resistance is low, the conductive layer can be thinned.
Therefore, the gap between the surface of the semiconductor substrate and the surface becomes smooth, and it is easy to miniaturize the line width and the like.

In the semiconductor device according to the second aspect, the surface of the conductive layer is silicidized. Therefore, the electric resistance of the conductive layer can be reduced, and the operation speed can be increased. Further, since the resistance is low, the conductive layer can be thinned. Therefore, the gap between the surface of the semiconductor substrate and the surface becomes smooth, and it is easy to miniaturize the line width.

According to another aspect of the semiconductor device of the present invention, the conductive layer is formed as a floating gate and a control gate located thereabove. And
The surface of the control gate is silicided.

Therefore, the electric resistance of the control gate can be reduced, and the operating speed can be increased. Moreover, since the resistance is small, the floating gate and the control gate can be thinned.
Therefore, the gap between the surface of the semiconductor substrate and the surface becomes smooth, and it is easy to miniaturize the line width and the like.

In a method of manufacturing a semiconductor device according to a fourth aspect, a conductive layer having a multilayer structure is formed on a semiconductor substrate in a predetermined pattern, and a metal film is formed so as to cover the conductive layer. Then, the surface of the conductive layer in contact with the metal film is silicidized to remove the metal film.

Therefore, the electric resistance of the conductive layer can be reduced, and the operating speed can be increased. Further, since the resistance is low, the conductive layer can be thinned.
Therefore, the gap between the surface of the semiconductor substrate and the surface becomes smooth, and it is easy to miniaturize the line width and the like.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings. FIG.
2 is an enlarged cross-sectional view schematically showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a process drawing showing the manufacturing process thereof. In the following embodiments, the case where it is applied to a non-volatile memory embedded with logic is described.
The present invention is not limited to these and can be applied to other semiconductor devices.

In FIG. 1, reference numeral 1 is a base material made of single crystal p-type silicon, which is generally a silicon wafer. A field oxide film 2 formed by a known LOCOS method or the like is provided on the surface of the base material 1 as a separation region. The element formation regions 3, 4 between the isolation regions,
A gate oxide film 6 is provided on the surface of 5.

In the element forming region 3 at the left end in FIG.
A memory cell 7 and a select transistor 8 for the memory cell are formed. A high breakdown voltage transistor 9 is formed in the element formation region 4 at the center, and a logic transistor 10 is formed in the element formation region 5 at the right end (lower stage in FIG. 1).

The gate oxide film 6 of the memory cell 7 is provided with a tunnel oxide film 11 having a reduced thickness. An n ⁻ first memory cell diffusion layer 12 is provided on the back surface side in a predetermined range including the tunnel oxide film 11, that is, on the inner side of the base material 1. Further, a second memory cell diffusion layer 13 is provided at a predetermined distance from the memory cell diffusion layer 12.

On the other hand, on the surface side of the gate oxide film 6, a floating gate 14 made of a polysilicon layer formed in a predetermined range including the tunnel oxide film 11 is provided. Further, an ONO film 15 for insulation is formed on the surface of the floating gate 14. The ONO film 15 is also formed on the side surface of the floating gate 14.
A control gate 17 made of polysilicon is formed on the surface and side surfaces of the ONO film 15. Surrounding the control gate 17 is a sidewall 19
Is provided.

Further, a silicide layer 20, which is a feature of this semiconductor device, is provided on the upper surface of the control gate 17. That is, the control gate 17 as a whole has a laminated structure of polysilicon and silicide, that is, a polycide structure. This silicide layer 20
The metal component of can be selected according to the purpose of the semiconductor device and the composition of the underlying polysilicon. Examples of the metal component include titanium (Ti), tungsten (W), molybdenum (Mo), platinum (Pt) and the like. Note that titanium is preferable for silicide for increasing the operation speed of the nonvolatile memory.

The silicide layer 20 has a function of lowering the resistance of the control gate 17. Therefore, the operating speed of the control gate 17, and eventually the operating speed of the floating gate 14 is also increased. Further, since the resistance is lowered, the thickness of the floating gate 14 and the control gate 17, which is normally required to be about 4000 angstroms, can be set to about 2000 angstroms.

As described above, by making the floating gate 14 and the control gate 17 thin, the step difference with the base material 1 becomes small. This facilitates the flattening of the interlayer film in a later step, and thus facilitates the formation and miniaturization of aluminum wires and the like.

The select transistor 8 provided adjacent to the above-mentioned memory cell includes a select gate 21 of the first polysilicon layer and a silicide layer 22 thereon. That is, the select transistor 8 also has a polycide structure. The gate oxide film 6 is removed between the select transistor 8 and the memory cell 7, and an n ^{+ type} source 23 is formed in the substrate 1 between them. The gate oxide film 6 is also removed between the select transistor 8 and the isolation region (field oxide film 2) on the right side, and an n ^{+ type} drain 24 is formed.

The high breakdown voltage transistor 9 in the central element formation region 4 described above includes a gate 25 made of polysilicon formed on the gate oxide film 6 and a silicide layer 26 formed on the surface of the gate. That is, it also has a polycide structure. Further, the same source 27 and drain 28 as those described above are provided.

Further, the logic transistor 10 provided in the element forming region 5 at the right end is provided with a gate 29 made of polysilicon formed on the gate oxide film 6 and a silicide layer 30 formed thereon. Source 31
And a drain 32 are provided.

The titanium silicide layer 33 is formed not only on the elements of the memories and transistors described above but also on the substrate surface in the element formation region. The silicide layers 22, 26, 30 provided on the surface of each of the above transistors are
Each has the function of lowering the resistance of each gate. Therefore, the thickness of the gate, which is normally required to be about 4000 angstroms, can be set to about 2000 angstroms. Therefore, the step difference with the base material 1 becomes small, and the interlayer film can be easily flattened in a later step, so that the aluminum wire and the like can be easily formed and miniaturized.

Next, the method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG. First, p of single crystal
A separation step (step S1) of forming a field oxide film 2 serving as a separation region on the surface of a base material (wafer) 1 made of shaped silicon by a known LOCOS method is performed.
An element formation region 3 in which an element is formed is provided between the isolation regions,
4 and 5.

Next, the surface of each element formation region is oxidized at a high temperature to form the gate oxide film 6. Since the memory cell is formed in the element forming region 3 at the left end, the tunnel oxide film 11 having a reduced thickness is provided by partial etching.
Further, ions are implanted into the inside of the base material 1 to generate a channel, and the first and second memory cell diffusion layers 1 are converted into n ^−.
2 and 13 are formed (step S2).

Next, CVD is performed on the surface of the field oxide film 2.
A polysilicon layer is grown by a method or the like. Further, masking is performed with a predetermined resist pattern and etching is performed to provide a first polysilicon layer having a predetermined pattern. The first polysilicon layer forms the floating gate 14 of the memory cell 7 described above. Further, the select gate 21 of the select transistor 8 and the gate 25 of the high breakdown voltage transistor 9 are simultaneously formed (step S
3).

After that, the gate oxide film 6 at an unnecessary portion between the gates is removed by etching. Then, an ONO film 15 for insulation is formed on the surface of the floating gate 14. The ONO film 15 is also formed on the side surface of the floating gate 14. Subsequently, a polysilicon layer is grown by a CVD method or the like, masked with a resist pattern,
The second polysilicon layer is provided by etching. The second polysilicon layer forms the control gate 17 of the memory cell 7 and the gate 29 of the logic transistor 10. After forming the second layer of polysilicon, the side wall of each gate is anisotropically etched to form sidewalls 19 (step S4).

Next, the control gate 1 of the memory cell 7
A silicide layer is formed on the upper surface of 7 and the upper surfaces of the gates of the transistors 8, 9 and 10 by the silicide method as follows. That is, first, a metal film of titanium or the like is formed on the entire surface by sputtering, and annealed at about 800 to 1000 ° C. for about several tens of seconds. Then, metal atoms are diffused into the polysilicon layer to a depth of about 500 to 1500 angstroms. At this time, only the portion where the polysilicon is exposed and is in contact with the metal film is silicidized. Then, when the entire metal film is removed by wet etching, a silicide layer is formed on each of the above gates (step S5). The range of silicide may be controlled by further annealing at a predetermined temperature. As a result, the logic embedded type non-volatile memory shown in FIG. 1 is obtained.

[Brief description of drawings]

FIG. 1 is an enlarged sectional view schematically showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a process drawing showing an embodiment of a manufacturing process of the semiconductor device shown in FIG.

[Explanation of symbols]

 1 ... Base material 2 ... Field oxide film 5 ... Gate oxide film 7 ... Memory cell 8 ... Select transistor 9 ... High breakdown voltage Transistor 10-Logic transistor 14-Floating gate 17-Control gate 20-Silicide layer 21-Select gate 22-Silicide layer 25・ ・ ・ Gate 26 ・ ・ ・ Silicide layer 29 ・ ・ ・ Gate 30 ・ ・ ・ ・ ・ Silicide layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/78

Claims (4)

[Claims] 1. A conductive layer having a multi-layered structure, which is provided on the surface of a semiconductor substrate and is projected from the surface of the semiconductor substrate.
A semiconductor device having: a semiconductor device, wherein the conductive layer is configured to include a silicided portion. 2. The semiconductor device according to claim 1, wherein the surface of the conductive layer is silicidized. 3. The semiconductor device according to claim 2, wherein the conductive layer is configured as a floating gate and a control gate located above the floating gate, and the surface of the control gate is silicided. Semiconductor device. 4. A step of forming a conductive layer having a multi-layer structure in a predetermined pattern on a semiconductor substrate, a step of forming a metal film covering the conductive layer, and a step of forming a surface of the conductive layer in contact with the metal film. A method of manufacturing a semiconductor device, comprising: a step of silicidation; and a step of removing the metal film.