JPH022684A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a device consisting of a single-layer structured memory cell having good holding characteristics of electric charge by a method wherein a protection electrode is provided on a surface of a floating gate via an insulation film, and the protection electrode is connected to the lowest electric potential. CONSTITUTION:In a nonvolatile semiconductor memory device having a floating gate 2 whose surface is not covered with a control gate, a protection electrode 1 is provided on the surface of said floating gate 2 via an insulation film 9 and the protection electrode 1 is connected to the lowest electric potential. For example, the protection electrode 1 is formed on the floating gate 2 of an electrically erasing type single layer gate nonvolatile semiconductor memory device which consists of a word line 3 made of an impurity diffusion layer, the floating gate 2, a source line 5 and a digit line 4. The protection electrode 1 is furthermore connected to the lowest electric potential. This enables cations to be accumulated in the protection electrode, preventing the cations from influencing the floating gate against entry of alkari cations into a chip due to secular change. This therefore remarkably improves reliability for long-term holding of memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and particularly to a nonvolatile semiconductor memory device having a floating gate whose surface is not covered with a control gate.

[Conventional technology]

Conventionally, in this type of nonvolatile semiconductor memory device, especially in a nonvolatile semiconductor memory device with a single layer gate electrode structure in which the control gate is formed of a single impurity diffusion layer, there is a difference between the gate electrode structure in which the control gate is stacked in two layers, and , the surface of the floating gate is not covered by the control gate, and the surface of the floating gate is a general M
Similar to the O3 type transistor, only the glabella insulating film and the passivation film are formed.

[Problem to be solved by the invention]

The above-described conventional nonvolatile semiconductor device having a single-layer gate electrode structure has the following drawbacks because the floating gate is not covered with a control gate. In other words, a nonvolatile semiconductor memory device obtains nonvolatility by retaining charge (electrons) in a floating gate in a state that is excessive or small compared to a steady state, and the retention characteristics of this charge are as follows. It is determined by (1) emission due to the self-electric field accumulated in the floating gate, (2) emission due to thermal excitation, and (3) the middle phase of the accumulated charge due to mobile ions gathering at the floating gate. By the way, (1) and (2) above occur similarly in the case of a non-volatile semiconductor device with a two-layer stacked gate structure, but regarding (3), it occurs similarly in the case of a non-volatile semiconductor device with a single-layer gate electrode structure. In the case of a gate structure in which the floating gate is not covered with a control gate and mobile ions (especially alkaline cations such as Na+) enter the chip and collect on the surface of the floating gate due to aging, the accumulated charge (electrons) and As a result, the charge in the floating gate is equivalent to disappearing, and the memory retention characteristics are significantly inferior.In this way, in a conventional nonvolatile semiconductor device with a single-layer gate electrode structure, , the charge retention characteristic is 2
It has the disadvantage of being significantly inferior to the laminated R structure type.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a nonvolatile semiconductor device comprising a single-layer gate electrode structure memory cell with extremely good charge retention characteristics.

[Means to solve the problem]

According to the present invention, in a nonvolatile semiconductor memory device having a floating gate whose surface is not covered with a control gate, a protective electrode is provided on the surface of the floating gate via an insulating film, and the protective electrode is connected to the lowest potential. It consists of:

〔Example〕 The present invention will be described in detail below with reference to the drawings.

1(a) and (b) are a partial plan view and a sectional view taken along the line AA' of a nonvolatile semiconductor memory device showing one embodiment of the present invention. According to this embodiment, the protective electrode 1
The word line is made of an impurity diffusion layer, and the floating gate 2. It is formed on the floating gate 2 of an electrically erasable single-layer gate nonvolatile semiconductor memory element consisting of a source line 5 and a digit line 4, and the protective electrode 1 is connected to the lowest electrode. The device structure of the above embodiment was formed as follows.

Referring to FIG. 1(b), for example, a P-type semiconductor substrate 10
A field oxide film is formed thereon, and then a word line impurity layer 3. Source region 11 and drain region 1 of the memory cell
The second impurity layer is formed by, for example, photolithography technology,
Formed by ion implantation technology, heat treatment, etc. Next, the first
A gate oxide film 7 is formed, an opening for a tunnel window 6 and a second gate oxide film 8 are formed, and then a floating gate 2 is formed by introducing impurities into a polycrystalline silicon layer formed by, for example, LPCVD. After that, it is formed using photolithography technology. After this, the interlayer insulating film 9 is formed to a thickness of 1
000 to 8,000 using the atmospheric pressure CVD method, then, for example, form a polycrystalline silicon layer by the LPCCVD method and introduce impurities, and furthermore, the protective electrode 1 is formed using photolithography technology and etching technology. It was formed. In this way, by forming the protective electrode 1 on the uncovered floating gate 2 of the control gate and further connecting it to the lowest potential, positive ions that have entered the chip due to changes over time can be collected in the protective electrode 1. Therefore, it is possible to eliminate the influence on the floating gate 2.

FIG. 2 is a partial plan view of a nonvolatile memory device showing another embodiment of the present invention. According to this embodiment, the first gate electrode 25. Floating gate 23. Second gate electrode 26. A protective electrode 24 is formed on a floating gate 23 of a three-layer polycrystalline silicon type nonvolatile semiconductor memory element consisting of a source region 21 and a drain region 27, and further this protective electrode 24 is connected to the lowest potential. The device structure of the above embodiment can be manufactured by a method similar to that of the previous embodiment, and the protective electrode 24 can be easily formed. According to this embodiment, as in the previous embodiment, cations that have entered the chip due to changes over time can be collected on the protective electrode, and their influence on the floating gate can be eliminated, so long-term reliability can be achieved. can.

〔Effect of the invention〕

As explained above, according to the present invention, a protection gate is formed in a nonvolatile semiconductor memory element having a floating gate not covered with a control gate via an interlayer insulating film, and further connected to the lowest potential of the chip. This makes it possible to collect cations on the protective electrode and eliminate the influence of cations on the floating gate against alkaline cations entering the chip due to changes over time. It is possible to eliminate the apparent loss of charge due to

In other words, it is possible to significantly improve the reliability of long-term memory retention6.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a partial plan view and an AA' cross-sectional view of a nonvolatile semiconductor memory device showing one embodiment of the present invention, respectively, and FIG. 2 shows another embodiment of the present invention. FIG. 2 is a partial plan view of the nonvolatile semiconductor memory device shown in FIG. 1.24... Protective electrode, 2.23... Floating gate,
3... Word line impurity layer, 4, 22... Digit line, 5... Source line, 6... Tunnel window, 7...
First gate oxide film, 8... Second gate oxide film, 9
...Interlayer insulating film, 10...Semiconductor substrate, 11.21
...Source, 12.27...Drain, 25...
first gate electrode, 26... second gate electrode;

Claims (1)

[Claims] A nonvolatile semiconductor memory device having a floating gate whose surface is not covered with a control gate, characterized in that a protective electrode is provided on the surface of the floating gate via an insulating film, and the protective electrode is connected to a lowest potential. semiconductor memory device.