JPH01278781A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable the writing with a low voltage without enlarging an element forming region and prevent a memory holding time from decreasing due to movable ions by a method wherein a metal conductive layer is formed on the whole area of a thin interlaminar insulating film to connect the metal conductive layer with a control gate. CONSTITUTION:An interlaminar insulating film 12 of a region corresponding to a floating gate 4 formed of a polycrystalline silicon layer and a control gate formed of a diffusion layer is formed of a film whose thickness is smaller than that of an interlaminar insulating film 5 of other regions, and a metal conductive layer 11 formed on the whole area of a thin interlaminar insulating film 12 and the control gate are connected with each other. An aluminum plate 11 is provided onto the floating gate 4 through the intermediary of a thin oxide film. By these processes, a capacitance can be increased without enlarging an element forming region, whereby the writing can be executed with a low voltage. And, the aluminum plate serves as a barrier against movable ions and charges stored at the floating gate are not neutralized, so that a memory holding time does not decrease.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and particularly to a nonvolatile semiconductor memory device having a floating gate formed of a single layer of polycrystalline silicon.

[Conventional technology]

Conventionally, this type of nonvolatile memory has memory elements each composed of a single transistor arranged in a matrix, and information is written and stored by accumulating charge in the addressed memory elements. Further, there are two methods for erasing the electric charge, which is stored information: an electrical erasing method and a method using ultraviolet light.

FIG. 4 is a plan view showing a conventional electrically erasable EPROM element, and FIG. 5 is a sectional view taken along line A--A in FIG. This EPROM is electrically erasable so-called EEP.
ROM (Electrica, lIy, EPROM
(hereinafter referred to as EEPROM). This EEPR, OM consists of floating gates 1 to 4 and a contact 1 made of a single polycrystalline silicon layer on a P-type silicon substrate 1.
~ Controlled diffusion layer 2 and N+ type scattering layer 9 that become roll gates
It is composed of a memory 1 to transistor region consisting of a drain region to be formed and a tunnel oxide film for injecting charge, and a region for a selection transistor 10 for selecting reading, writing, and erasing. The region of the transistor 10 includes a source region and a drain region formed by an N+ type scattered layer connected to the source line 6 or bit line 7 via a contact, and a floating gate 1 connected to the word line 8 and connected to the memory transistor. -4. The memory transistor region consists of a drain region which also serves as a source region of transistors 1 to 10, a floating gate h4 formed on the gate oxide film 3, and a structure sandwiching the floating gate 1-4 and the gate oxide film 3. A tunnel is formed by forming a controlled diffusion layer 2 disposed on a P-type silicon substrate 1 and a part of the gate oxide film 3 located between the drain region of the memory transistor and the controlled diffusion layer 2 to be thin. The oxide film 14 is formed. When writing to this EEPROM, a high potential is applied to the control diffusion layer 2,
Due to the tunnel effect, electrons are injected into the floating gate 4 from the drain region through the tunnel oxide film t4 and accumulated therein. During this writing, the tunnel oxide film 14
The voltage ■ applied to is expressed by the following formula.

v=voxC2/Ct ■o: Voltage applied to control I roll gate (control diffusion layer).

C2: Floating gate and control game I
(controlled diffusion layer) capacitance.

CT: Total capacitance between the floating gate and other layers, including C2.

For this reason, in order to make writing easier, the design is designed to increase the voltage applied to the 1-channel oxide film as much as possible, increase C2, and reduce the capacitance between the floating gate 1- and other layers other than C2. ing. Further, although not shown, as an example of increasing the capacitance of C2, there is a two-layer polycrystalline silicon electrode structure. In this device, a control gate made of a polycrystalline silicon layer is provided on a floating gate made of a polycrystalline silicon layer, and the area where the control gate and the floating gate overlap is increased to further increase the capacitance.

[Problem to be solved by the invention]

In the above-mentioned conventional EEPROM, floating game 1
Since a large overlap area between ~ and the control diffusion layer cannot be obtained, the capacitance is small, and the voltage applied to the tunnel oxide film cannot be increased with a small applied voltage. It is also possible to increase the area of the floating gate 1- in order to increase the capacitance, but compared to a two-layer polycrystalline silicon electrode structure, the area of the active region is required to be two to three times larger, and the element formation area becomes extremely large. The problem is that it gets bigger.

Furthermore, since the floating gate of these EEPROMs is covered only with a glabella insulating film and a passivation film, in the case of a normal resin mold,
There is a problem in that sodium compounds in the resin are decomposed into Na + ions by absorbing moisture after resin sealing, and these Na mobile ions are focused on the floating gate 1 and neutralize the accumulated electrons.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device that allows writing at a lower voltage without enlarging the element formation area and that does not reduce memory retention time due to mobile ions.

[Means to solve the problem]

A nonvolatile semiconductor memory device of the present invention has a control gate and a floating gate formed of a single polycrystalline silicon layer, in which a floating gate formed of the polycrystalline silicon layer and a diffusion layer are provided. An interlayer insulating film in a region corresponding to the control I and the roll gate is formed to have a thinner film thickness than the interlayer insulating film in other regions, a metal conductive layer is formed over the entire area of the thin glabellar insulating film, and a metal conductive layer is formed over the entire area of the thin eyebrow insulating film, The structure includes a layer and the control gate connected to each other.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a partial plan view of a semiconductor chip for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA in FIG. This example is FLOTOX type E
This is an example applied to an EP ROM. As in the conventional example, the region of the selection transistor 10 includes a source region of an N+ type scattering layer 9 connected via a contact to a source line 6 formed by aluminum evaporation, and a bit region also formed by aluminum evaporation. It is formed of a drain region made of an N+ type scattered layer 9 that is continuous with the line 7 via a contact, and a goo 1- region that is continuous with the word line 8 formed of a polycrystalline silicon layer. Next, in the memory transistor area,
There is a control diffusion layer 2, which is a control diffusion layer 1, formed by diffusing N-type impurities on a P-type silicon substrate 1, and a gate oxide layer 11%3 is formed thereon. On the gate oxide film 3 there is a floating gate 4 of a polycrystalline silicon layer for selection and integrally formed with the gate of the transistor. Furthermore, the floating gate 4 is covered with an interlayer insulating film, and the region corresponding to the control diffusion layer 2 and the floating gate 4 is a thin region 12 of the glabellar insulating film.
Other regions are formed with a thick interlayer insulating film 5. Also,
The thin region 12 of the interlayer insulating film is formed to have the same thickness and modification as the Glue oxide film 3. Aluminum plates 1 and 11 are formed on these interlayer insulating films, and these aluminum plates 1 and 11 are connected to the control diffusion layer 2 by penetrating the thick region of the interlayer insulating film 5 through contacts 1-13. Further, as in the conventional example, there is a channel oxide film 14 between the drain region of the memory 1 transistor region which also serves as the source region of the transistor 10 and the floating gate 4.

Next, to explain the manufacturing method of this storage device, first,
A field oxide film is formed on the surface of the P-type silicon substrate 1 by the LOCO3 method to isolate element forming regions. next,
By implanting N-type impurities, a control diffusion rl1 layer 2 of the memory transistor is formed. Next, a gate oxide film 3 and an I channel oxide film 14 are formed on the gate I oxide film and the control diffusion layer 2 of the transistor 10. next,
1 to the gate of the transistor 10 and the floating gate 4 are formed by growing a polycrystalline silicon layer. Next, C
A silicon oxide film is grown by the VD method, and a glabellar insulating film 5 is formed to cover the gate of the transistor 1 and the floating gate 4. The floating gate 4 and the N+ type scattering layer are grown by photolithography and dry etching. A portion of the interlayer insulating film 5 corresponding to 2 is selectively removed to expose the floating gate 4. next,
The surface of the interlayer insulating film 5 is smoothed by heat treatment in an oxidizing atmosphere, and a silicon oxide film is formed on the exposed floating gate 4 to the same thickness as the oxide film 3 to form the interlayer insulating film. A thin region 12 is formed.

Next, a contact hole 13 is formed, and a metal vapor deposition method is used to form the contact hole 13.
depositing aluminum to form an aluminum metal layer;
The aluminum metal layer is selectively removed to form aluminum plate 11, source line 6 and bit line 7.

By the way, when I made an EEPROM with this structure,
1 compared to the conventional EEPROM write voltage of 19V.
I was able to write with a voltage as low as 3.5V.

FIG. 3 is a partial plan view of a semiconductor chip for explaining a second embodiment of the present invention. This embodiment is an example applied to EPR, OM that can be erased with ultraviolet rays. This EP
The ROM is connected to the source line 6 via the contact l-.
For selection, it consists of a source region formed by a + type diffused layer, a drain region formed by an N+ type D diffused layer via the focus line 7 and contact I, and a gate region formed by a polycrystalline silicon layer. 1 to transistor 10 are configured. The area of the memory transistor adjacent to this transistor 10 is
1 to a floating gate 4 made of a polycrystalline silicon layer formed integrally with the gate of the transistor 10, a drain region which also serves as a source region formed with an N+ type scattering layer, and a control gate made of a control diffusion layer 2; , a thin interlayer insulating film 12 made of a thin silicon oxide film is provided in a portion corresponding to the floating gate 4 and the controlled diffusion layer 2.
and aluminum plates 1 to 11 formed thereon. Of course, the aluminum plate 11 is connected to the control diffusion layer 2 by a contact I 13 that penetrates the interlayer insulating film 5 in the thick region.

Note that in the drawings for explaining the above embodiments, the thin region 12 of the interlayer insulating film is drawn slightly smaller so that the floating gate 4 and the thin region 12 of the glabellar insulating film can be easily distinguished. , may be the same size as the square floating gate 4 part.

〔Effect of the invention〕

As explained above, in the present invention, the aluminum plate I~ is provided on the floating gate I~ of the EPROM through a thin oxide film. Compared to
If the design is comparable to the conventional capacitance, the area of the charge storage region can be halved. This has the effect that the capacity can be increased without increasing the element formation area, and writing can be performed at a lower voltage. Also,
By providing an aluminum plate on the floating gate, the aluminum plate acts as a barrier to mobile ions and does not neutralize the charge accumulated on the floating gate, thereby reducing memory retention time. There is also the effect of not having one.

[Brief explanation of the drawing]

FIG. 1 is a partial plan view of a semiconductor chip for explaining a first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line A-A in FIG. 1, and FIG. FIG. 4 is a plan view showing a conventional electrically erasable EPROM element; FIG.
The figure is a sectional view taken along the line AA in FIG. 3. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Controlled diffusion layer, 3...
...Gate oxide film, 4...Floating gate, 5
・・・Interlayer insulating film, 6... Source line, 7... Pit 1
~ line, 8... word line, 9... N+ diffusion layer, 10.
...Transistor, 11...Aluminum plate,
12... Thin region of interlayer insulating film, 13... Contact, 14... I/channel oxide film.

Claims (1)

[Claims] In a nonvolatile semiconductor memory device having a control gate and a floating gate formed of a single polycrystalline silicon layer, an interlayer insulating film in a region corresponding to the floating gate formed of the polycrystalline silicon layer and the control gate formed of a diffusion layer is A metal conductive layer is formed to have a thickness thinner than that of the interlayer insulating film in other regions, and a metal conductive layer is formed over the entire area of the thin interlayer insulating film, and the metal conductive layer and the control gate are connected. Non-volatile semiconductor memory device.