JPH0258267A - Manufacture of mis type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a mask ROM, prevent latchup, and improve the reliability of an integrated circuit by forming an MISFET having a second threshold value by implanting oxygen in the source region, the drain region, etc., of the MISFET having a first threshold voltage. CONSTITUTION:When a semiconductor integrated circuit provided with a non- volatile storage function composed of an MISFET is manufactured, an MISFET having a first threshold voltage and an MISFET having a second threshold voltage are arranged. The first MISFET is consti//tued of the following; a source.drain region 105 of high impurity concentration, and a semiconductor region 103 which is formed between the source.drain region 105 and a channel forming region and has the same conductivity type as the source.drain region 105 and a concentration lower than the region 105. The second MISFET is formed by implanting oxygen in the source region, the drain region or the low concentration semiconductor region 103 of the above MISFET. For example, the semiconductor region 103 is turned into a state 107 where silicon and silicon oxide are mixed, by performing annealing after oxygen 106 is introduced in the semiconductor region 103 in order to write data.

Description

DETAILED DESCRIPTION OF THE INVENTION In particular, the present invention relates to a semiconductor integrated circuit device (hereinafter referred to as a mask ROM) having a read-only nonvolatile memory function.

[Prior Art] A mask ROM has memory cells made up of MISFETs. 2'011'1' of memory cell.

The information can be obtained by changing the threshold voltage of the MISFET in the I information writing process.

Let us give an overview of a method of manufacturing a conventional MIS type semiconductor device and an MO8 type semiconductor device as an example.

First, L D D (Light
A MISFET having a doped drain structure is formed. After that, an interlayer insulating film covering the MISFET is formed, and a data line and source #I (aluminum film) connected to the MISFET are formed. After this, a photoresist mask is formed which has an opening above the channel formation region of the MISFET where information is to be written. Then, using this photoresist mask, an impurity (boron or impurity) is introduced into the channel forming region through the interlayer insulating film and the gate electrode. By introducing this impurity, a MISFET having a second threshold voltage different from the first threshold voltage is formed, and an information writing process is performed. Thereafter, the mask ROM manufacturing process is completed by forming a surface protection film.

[Problems to be Solved by the Invention] However, in the manufacturing process of the mask ROM according to the prior art described above, in the process of writing information, the impurity passes through the gate electrode layer and the gate insulating film, and the impurity penetrates the channel of the MISI-Run sister. Impurities are introduced into the region, and the acceleration energy at the time of impurity implantation is as high as about 250 to 350 KeV. Therefore, crystal defects occur in the gate insulating film and in the channel region of the MIS transistor. These crystal defects cannot be sufficiently recovered because heat treatment at only about 450° C. can be performed to prevent the wiring layer made of the aluminum film from deforming or melting. Crystal defects in the transistor channel region are caused by MIS) when the channel length of the transistor is 1.2.
When miniaturized to micrometers or less, hot carriers generated by the strong electric field in the drain region during transistor operation are captured, and the captured electrons recombine with holes.1. Since the leakage current flows to the semiconductor substrate side, problems such as increased power consumption and latch-up due to the parasitic thyristor occur.

In addition, as device miniaturization progresses and the channel length of a Runsistor (MIS) becomes less than 1 μm, impurities different from those in the source and drain regions are introduced into the transistor channel region through ion implantation to increase the threshold voltage. As a result, the withstand voltage between the source and drain is significantly lowered, and during transistor operation, secondary breakdown is likely to occur due to the high electric field in the drain region, making stable operation difficult.

The present invention is intended to solve such problems, and its purpose is to reduce power consumption in mask ROM,
The object of the present invention is to provide a technology that contributes to preventing latch-up and further improving the reliability of integrated circuits.

[Means for Solving the Problems] The method for manufacturing an MIS type semiconductor integrated circuit device of the present invention includes
In a method of manufacturing a semiconductor integrated circuit having a non-volatile memory function consisting of an ISFET, a drain with a high impurity concentration,
A first threshold comprising a source region and a semiconductor region of the same conductivity type as the drain and source region and with a lower concentration than the drain and source region provided between the drain and source region and the channel and formation region. A MISFET with a voltage is configured, and the MISFET has a second threshold voltage by injecting oxygen into the source region, drain region, or low concentration semiconductor region of the MISFET.

[Embodiment] FIG. 1 is a cross-sectional view of the main steps of an embodiment of the MIS type semiconductor device of the present invention, and an example in which the device is applied to a mask ROM will be specifically shown below with reference to this figure.

P-type, specific resistance 8-12 (9 cm) silicon substrate 10
0 (or well region) as a gate oxide film in a 1000℃○2 atmosphere.
After forming a film with a thickness of 200 to 400, polycrystalline silicon JfJ102 is deposited as the gate electrode material 102 by CVD method, and then 5xl of ionized phosphorus (P+) is deposited at an acceleration energy of about 50 KeV.
Gate electrode material 102 injected with approximately OI5 (cm-2)
As a single layer of high melting point silicide (MOS i 2
, T i S il T a S i2. WS
i2) II, refractory metal (Mo.

It may be composed of a Ti, Ta, W) film, or a composite film (polycide film) in which polycrystalline silicon is provided as a layer below these films.

Next, desired patterning was performed by photolithography, and polycrystalline silicon layer 102 was etched by dry etching.

At this time, the etching conditions for the polycrystalline silicon layer 102 are SFa, CClF5 gas, 150W, pressure 0.6To
Etched with rr for about 60 seconds.

Next, in order to form a semiconductor region 103 (also called an offset region) with a low impurity concentration, desired patterning is performed by photolithography, and then, for example, ionized phosphorus (P) is irradiated with 8×10 12 at an acceleration energy of 30 KeV. (pieces/cm2) ions were implanted. This low concentration semiconductor region is LDD (Lightly
(doped drain) section.

Next, the insulating film remains on the side wall of the polycrystalline silicon layer 102, which is the so-called side wall.
5,000 layers of first silicon oxide layer 104 are deposited by the CVD method to form all layers 104. The deposition conditions at this time were N20+CH in a 780°C atmosphere.
, by heat treatment at 200 Pa for 30 minutes.

Next, the first silicon oxide layer is subjected to RIE (Reactive
DRY etching was performed in the ion etching) mode. Through this process, the sidewall (Si
104 is formed.

Next, ionized phosphorus was implanted into the portion 105 that would become the source and drain of the transistor in a self-aligned manner at an acceleration energy of T5X101' (pieces/Cm2) of 60 keys. (Figure 1 (a)) After this, silicon oxide is deposited to insulate the gate electrode layer and the wiring material (for example, aluminum), and a hole is made to make contact with the gate electrode material, and the wiring material is It was deposited and buttered.

After this, in order to write data in the mask ROM, oxygen ions 106 are applied to the low concentration semiconductor region 103 on the drain and source sides with an acceleration energy of 160 KeV.
(individuals//) introduced. (Figure 1(b)) Next, 450″
Low concentration semiconductor regions 10 on the drain and source sides were annealed for 40 minutes in an argon-hydrogen (3%) atmosphere.
By forming a state 107 in which silicon and silicon oxide are mixed in 3 to increase the resistance value of the drain and source regions, the threshold of the MISI-Run Sister is made higher than that of the M-S transistor without oxygen implantation. (FIG. 1(C)) That is, the transistor is made inoperative even when it is in the selected state. In addition, because there is no need to implant impurities of a conductivity type different from that of the source and drain regions into the channel region, the breakdown voltage between the source and drain can be made to the same level as the breakdown voltage of a transistor that does not write. In the above example, oxygen ions were implanted into the drain and source sides, but the oxygen ions were implanted into the source region, drain region, low concentration semiconductor region on the source side, low concentration semiconductor region on the drain side, or a combination of these. The effect is the same.

The process involved depositing a protective film on the element surface, and finally drilling holes for contacting the wiring material with the external terminals.

The embodiments of the present invention have been specifically shown above. However, this embodiment is just one example, and the effect is the same even if it is applied to, for example, a p-channel MISFET.

[Effects of the Invention] According to the present invention, by injecting oxygen, MOS
By making the offset region of the transistor rich in silicon oxide, we were able to increase the resistance and write data, while also making the withstand voltage between the source and drain the same level as a transistor that does not write data.

Furthermore, since the silicon oxide in the drain region prevents the depletion layer from expanding, the generation of hot carriers can be suppressed and leakage current can also be reduced. In addition, 4
The M-bit MASKR○M was able to increase yield by 20% compared to conventional semiconductor devices.

[Brief explanation of the drawing]

FIGS. 1A to 1C are process cross-sectional views of an embodiment of the MO3 type semiconductor device of the present invention. 100...Silicon substrate 101 containing first conductivity type impurity...Gate oxide film 102...Gate electrode material 103...Semiconductor region 104 with low impurity concentration of second conductivity type...First silicon oxide Layer, sidewall 105...Second conductivity type semiconductor region with high impurity concentration Source, drain region/oxygen implantation layer silicon, silicon oxide mixed layer or higher

Claims (1)

[Claims] In a method of manufacturing a semiconductor integrated circuit having a non-volatile memory function consisting of a MISFET, a drain and source region having a high impurity concentration and a conductivity same as that of the drain and source region provided between the drain and source region and a channel forming region are used. A MISFET having a first threshold voltage is constructed of a semiconductor region of a type and a lower concentration than the semiconductor region, and the source region, the drain region of the MISFET, or the semiconductor region of a lower concentration is provided with oxygen. 1. A method of manufacturing an MIS type semiconductor integrated circuit device, characterized in that it has a MISFET with a second threshold value by implanting.