JPH05218355A - Mis semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To improve controllability of ON current value in a mask ROM by implanting a particular element or atom or compound of elements in the particular amount into a region where at least MIS FET forms an inverted layer. CONSTITUTION:A group 7B element or oxygen atom or nitrogen atom or compound of these elements is included in the amount of 1X10<19>[pcs/cm<3>] into a region where at least MIS FET forms an inverted layer. That is, after a gate insulating film 109 is formed on a semiconductor substrate 100, helium, neon, argon, crypton, xenon, nitrogen or oxygen or ion 114 mainly consisting of a substance including such an impurity is implanted to a channel region 105 of at least MIS FET and this MIS FET is then heat-treated. Thereby, dielectric strength between source and drain 112, 113 of a transistor may be improved, large element margin and manufacturing margin can be obtained and the yield of electric characteristic of mask ROM can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MIS type semiconductor device.

In particular, the present invention relates to a semiconductor integrated circuit device having a non-volatile memory function.

[0003]

2. Description of the Related Art A mask ROM is one of semiconductor devices having a nonvolatile memory function. This mask ROM normally constitutes a memory cell with a MISFET, and the information of "0" and "1" of the memory cell is the so-called ON current value of the MISFET (source, drain, MIS transistor, It is obtained by changing the value of the current flowing in the drain when the voltage applied to the gate and the substrate is kept constant.

An outline of a conventional MIS type semiconductor device will be described by taking a manufacturing method of a MOS type semiconductor device as an example. (FIG. 2) First, for example, an N-type MIS field effect transistor (FET) having a first ON current value on a P-type semiconductor substrate 100.
101 is formed. After that, an interlayer insulating film 102 that covers this MISFET is formed. (FIG. 2A) Next, a photoresist pattern 103 having an opening on the channel region of the MISFET in which information is written is formed. Then, using this photoresist as a mask, the interlayer insulating film 10 is formed.
2 and the gate electrode 104 through the channel forming region 10
An impurity (for example, boron) 115 is introduced into 5. (Fig. 2
(B) After that, the implanted impurities are electrically activated by annealing in nitrogen gas at 800 ° C., and the first on-current value in which the introduction of the additional impurities is not performed by the introduction of the impurities. The MISFET 106 having the second on-current value to which the ion implantation has been performed is formed, and the information writing step is performed. Next, a wiring layer 107 such as a data line and a source line connected to the MISFET is formed. Finally, the surface protection film 108 is formed to complete the mask ROM manufacturing process. (Fig. 2 (c))

[0005]

In the case of the mask ROM,
As shown in the conventional example, the on-current value of the transistor is controlled by controlling the amount of impurities in the gate channel region. However, as the device becomes finer, it is necessary to increase the amount of impurities introduced for controlling the on-current value.
For example, when B (boron) is introduced to lower the on-current value of the N-type transistor and the threshold voltage of the MOS transistor is increased, a channel for realizing the threshold voltage of about 0.7 volt. The amount of impurities is 1 × 10 ¹⁷
The number of channel impurities for realizing a threshold voltage of about 5 V is 5 while the number of [channels / cm ³ ] is about 5.
It reaches about x10 ¹⁸ [pieces / cm ³ ]. The withstand voltage between the source and drain of this transistor is normally about 12 volts, but only about 3.5 volts can be obtained.
With this breakdown voltage, it is not possible to realize a drain breakdown voltage of 5.5 V or higher, which is necessary to realize a TTL level interface. As described above, in the method of introducing acceptor ions, the breakdown voltage between the source and drain of the transistor is lowered, which is one of the factors that hinder the miniaturization of the device.

The present invention solves such a problem, and its object is to turn on in a mask ROM.
It proposes a new method of controlling the current value.

[0007]

The semiconductor device of the present invention comprises:
In an integrated semiconductor device mainly composed of MIS-type FETs, at least a region of the MIS-type FETs forming an inversion layer contains a Group 7B element, an oxygen atom, a nitrogen atom, or a composite of the elements of 1 × 10. ¹⁹ [pcs / c
m ³ ] or more are included.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device mainly formed of a MIS type FET formed on a semiconductor substrate, wherein helium is provided at least in a channel region of the MISFET after the gate insulating film is formed. ,
The method is characterized by including a step of implanting ions containing neon, argon, krypton, xenon, nitrogen, oxygen, or an ion containing a substance containing the above impurities as a main component and a heat treatment.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cross-sectional view of the main steps of an embodiment of a MIS type semiconductor device according to the present invention, and an example applied to a mask ROM will be specifically shown below with reference to this drawing. A silicon oxide film 109 as a gate oxide film is formed on a silicon substrate 100 (or a well region) having a P type and a specific resistance of 8 to 12 (Ωcm) at 1000 ° C. and dry oxygen (O
₂ ) A film having a thickness of about 10 to 40 nm is formed in the atmosphere, and then, for example, a polycrystalline silicon layer 104 is deposited as the gate electrode layer 104 by the CVD method to a thickness of about 400 nm. The formation conditions are 620 by thermal decomposition of silane.
Perform in a moderate atmosphere. Next, ionized phosphorus (P +) is added at 5 × 10 ¹⁵ (c) at an acceleration energy of about 50 KeV.
About m ⁻² ) was implanted to introduce n-type impurities into the polycrystalline silicon.

Then, desired patterning was performed by photolithography, and the polycrystalline silicon layer 104 was etched by dry etching. At this time, the etching conditions for the polycrystalline silicon layer 104 are SF ₆ , C ₂
Etching was performed for 60 seconds with ClF ₅ gas and a pressure of 150 W at 0.6 Torr.

After oxidizing for 45 minutes in dry oxygen at 900 ° C., ionized arsenic is self-aligned with the source / drain portion 111 of the transistor at 60K.
5 × 10 ¹⁵ (pieces / cm ² ) ions were implanted with an acceleration energy of eV. (FIG. 1A) After that, silicon oxide 102 for insulating the gate electrode layer from the wiring material (for example, aluminum) is deposited. The deposition conditions for the silicon oxide 102 are SiH ₂ Cl ₂ and N.
₂ O was pyrolyzed in an atmosphere of 820 ° C. Then, the channel region 105 and the source region 11 of the transistor for which data writing is required by photolithography
2. After opening the drain region 113, nitrogen ion 1
14 was introduced at an acceleration energy of 160 KeV at 1 × 10 ¹⁵ (pieces / cm ² ). The mask pattern was set so that nitrogen ions were mainly implanted into the channel region of the MOS transistor. (FIG. 1 (b)) Next, in an inert gas atmosphere, for example, a nitrogen gas atmosphere, annealing treatment was performed at 850 ° C. to remove the damaged layer due to ion implantation.

The nitrogen introduced into the channel by this step scatters the electrons flowing when the MOS transistor is turned on, and reduces the on-current. This amount of decrease increases in accordance with the amount of nitrogen to be introduced, and when nitrogen is introduced 20% with respect to silicon, the on-current value of the MOS transistor decreases by about 50%. Further, the withstand voltage of the element at this time is about 8 V, and TT
The withstand voltage of 7V required for maintaining L interface compatibility can be sufficiently satisfied.

After this, a contact hole is opened by using photolithography and etching technique for making contact with the gate electrode material, and the wiring material (for example, aluminum) 10
7 was deposited using a magnetron sputtering method, and patterned using a holographic lithography method and an etching method. After that, an oxide film 108 is deposited to protect the device, and external terminal lead-out holes are formed by using photolithography and etching techniques.

(FIG. 1 (c)) The embodiment of the present invention is specifically described above. However, this embodiment is merely one embodiment, and for example, even if oxygen, helium, neon, argon, krypton, or xenon is used as the impurity species to be introduced into the channel region of the MOS transistor, in addition to the nitrogen, the effect is not obtained. Is the same.

[0015]

As described above, according to the present invention, nitrogen ions are
By injecting into the channel region of the S-transistor and then performing annealing treatment, the withstand voltage between the source and drain of the transistor can be improved by about 4.5 V compared to the conventional method, and the data write condition can be set without worrying about deterioration of withstand voltage. As a result, the element margin can be widened, and the manufacturing margin can be widened. Therefore, the yield of the electrical characteristics of the mask ROM using the transistor to which this method is applied is improved by about 10%. It was possible to reduce the cost.

[Brief description of drawings]

FIG. 1 is a process sectional view of an example of a method for manufacturing a MOS semiconductor device of the present invention.

FIG. 2 is a process sectional view of a conventional method for manufacturing a MOS semiconductor device.

[Explanation of symbols]

100 ... Silicon substrate containing impurities of the first conductivity type 101 ... MI of the second conductivity type having the first on-current
SFET 102 ... Interlayer insulating film 103 ... Photoresist 104 ... Gate electrode layer 105 ... Channel region 106 of second conductivity type MISFET ... Second conductivity type MI having second on-current
SFET 107 ・ ・ ・ Wiring layer 108 ・ ・ ・ Element protection insulating film 109 ・ ・ ・ Gate insulating film 110 ・ ・ ・ Silicon oxide film 111 ・ ・ ・ Second conductivity type impurity layer 112 ・ ・ ・ Source region of MISFET 113 ・ ・・ Drain region of MISFET 114 ・ ・ ・ Nitrogen ion 115 ・ ・ ・ Ionization boro 116 ・ ・ ・

Claims (2)

[Claims] 1. An integrated semiconductor device mainly composed of a MIS-type FET, wherein at least a region of the MIS-type FET forming an inversion layer has a Group 7B element, or an oxygen atom,
Alternatively, a nitrogen atom or a complex of the above elements is 1 × 1.
A MIS-type semiconductor device characterized by being contained in an amount of 0 ¹⁹ [pieces / cm ³ ] or more. 2. A method of manufacturing a semiconductor device mainly composed of a MIS type FET formed on a semiconductor substrate, comprising: after forming a gate insulating film, helium, neon, argon, krypton, at least in a channel region of the MISFET,
A step of implanting ions containing xenon, nitrogen, oxygen, or a substance containing the impurities as a main component;
And a step of performing heat treatment.