JP2833389B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art FIGS. 3A and 3B are plan views of memory cells of a nonvolatile semiconductor memory device, FIGS. 3B and 3A are cross-sectional views taken along line XX of FIG. 3A. Referring to FIG. 3C, which is a cross-sectional view taken along the line YY, the floating gate electrode 4c of the conventional nonvolatile semiconductor memory device is formed of a polycrystalline silicon film having a flat surface. A method for forming a memory cell of this nonvolatile semiconductor memory device is as follows.

[0003] First, a field oxide film 2 and a tunnel oxide film 3 are selectively formed on the surface of a P-type silicon substrate 1. A polycrystalline silicon film having a flat surface is deposited on the entire surface by low pressure chemical vapor deposition at 550 ° C. to 750 ° C. Next, in a predetermined region on field oxide film 2 covered by the same control gate electrode formed later, patterning is performed so that this polycrystalline silicon film is divided.

Then, a silicon oxide film 5c is formed on the exposed surface of the patterned polycrystalline silicon film by thermal oxidation. Further, a silicon nitride film 6c is deposited on the entire surface, and a silicon oxide film 7c is formed on the surface of the silicon nitride film 6c by thermal oxidation. Next, a second polycrystalline silicon film is formed on the entire surface. Next, using the photoresist film having the same pattern as the control gate electrode as a mask, the second polycrystalline silicon film and the silicon oxide film 7 are formed.
c, the silicon nitride film 6c, the silicon oxide film 5c, and the patterned polycrystalline silicon film are sequentially etched. By this etching, tunnel oxide film 3 is removed, and control gate electrode 8 made of the second polycrystalline silicon film and floating gate electrode 4c made of the polycrystalline silicon film are formed.

After the photoresist film is removed, a silicon oxide film 9 is formed on the exposed surfaces of silicon substrate 1, floating gate electrode 4c and control gate electrode 8 by thermal oxidation. Next, an N-type source diffusion layer 10 and a drain diffusion layer 11 are formed on the surface of the silicon substrate 1 by ion implantation using the control gate electrode 8 as a mask. An interlayer insulating film 12 is deposited on the entire surface, and a contact hole 13 reaching the drain diffusion layer 11 is formed. Next, aluminum wiring 14 (bit line) connected to drain diffusion layer 11 through contact hole 13 is formed.

Writing in the memory cell of the nonvolatile semiconductor memory device having the above-described structure is performed as follows. The silicon substrate 1 and the source diffusion layer 10 are grounded,
When a positive bias is applied to the drain diffusion layer 11 and the control gate electrode 8, hot electrons (electrons in a high energy state) are generated in a channel region near the drain diffusion layer 11. By injecting the hot electrons into the floating gate electrode 4c, the memory cell enters a written state. On the other hand, erasing in this memory cell is performed as follows. The silicon substrate 1 is grounded, the drain diffusion layer 11 is electrically floated, the control gate electrode 8 is applied with a negative bias, and the source diffusion layer 10 is applied with a positive bias. Thereby, the electrons accumulated in the floating gate electrode 4c are field-emitted.

[0007]

In the above-mentioned memory cell of the nonvolatile semiconductor memory device, when erasing, the tunnel oxide film 3 between the floating gate electrode 4c and the source diffusion layer 10 has a thickness of about 7 to 9 MV / cm. Is applied. Due to this electric field, the electrons accumulated in the floating gate electrode 4c become a tunnel current and are emitted to the source diffusion layer 10. The electric field applied to the tunnel oxide film 3 is controlled by the control gate electrode 8
(Erase voltage) between the gate electrode 8 and the source diffusion layer 11 is determined by capacitance division by the capacitance value between the control gate electrode 8 and the floating gate electrode 4c and the capacitance value between the floating gate electrode 4c and the silicon substrate 1.

The reduction of the occupied area of the memory cell and the reduction of (the absolute value of) the erasing voltage are both one of the development goals of the nonvolatile semiconductor device. In order to lower the erase voltage, the capacitance value between the control gate electrode 8 and the floating gate electrode 4c may be larger than the capacitance value between the floating gate electrode 4c and the silicon substrate 1. The capacitance between the control gate electrode 8 and the floating gate electrode 4c is increased without increasing the area occupied by the floating gate electrode 4c relative to the area of the channel region (this increase is accompanied by an increase in the area occupied by the memory cell). To do this, the silicon oxide film 7c, the silicon nitride film 6c,
And the relative thickness of the dielectric film composed of the silicon oxide film 5c may be reduced.
The electrostatic breakdown voltage between the gate electrode and the floating gate electrode 4c decreases, the leakage current between them decreases, and the holding characteristics deteriorate. That is, it is difficult to lower the erase voltage without increasing the area occupied by the memory cells.

[0009]

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the floating gate electrode is formed of an amorphous silicon film, and the amorphous silicon film is heat-treated in a vacuum. Therefore, irregularities are formed at least on the upper surface of the floating gate electrode.

[0010]

1A is a plan view of a memory cell of a nonvolatile semiconductor memory device, FIG. 1B is a sectional view taken along line XX of FIG. 1A, and FIG. Referring to FIG. 1C, which is a cross-sectional view taken along line YY, the floating gate electrode 4a of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
Is formed of an amorphous silicon film having an uneven upper surface. A method for forming a memory cell of this nonvolatile semiconductor memory device is as follows.

First, a field oxide film 2 is selectively formed on the surface of a P-type silicon substrate 1, and a tunnel oxide film 3 having a thickness of about 9 nm is formed by dilution oxidation. 4
An amorphous silicon film having a thickness of about 250 nm is deposited on the entire surface by a low pressure chemical vapor deposition method using a silane (SiH ₄ ) diluent gas at about 00 ° C. Next, when the oxygen partial pressure is 2 × 10
^When a heat treatment is performed at 550 ° C. for about 15 minutes in a vacuum of ⁻⁶ Torr or less, fine silicon crystal grains grow on the surface of the amorphous silicon film, so that the amorphous silicon film having an uneven surface is formed. Is formed. Next, in a predetermined region on field oxide film 2 covered by the same control gate electrode formed later, patterning is performed so that this amorphous silicon film is divided.

Subsequently, a silicon oxide film 5a having a thickness of about 12 nm is formed on the exposed surface of the patterned amorphous silicon film by thermal oxidation. Further, a silicon nitride film 6a having a thickness of about 10 nm is deposited on the entire surface by low pressure chemical vapor deposition, and a silicon oxide film 7a is formed on the surface of the silicon nitride film 6a by thermal oxidation. Next, a polycrystalline silicon film having a thickness of about 400 nm is deposited on the entire surface by low pressure chemical vapor deposition. Next, using the photoresist film having the same pattern as the control gate electrode as a mask, the above-mentioned polycrystalline silicon film, silicon oxide film 7a, silicon nitride film 6a, silicon oxide film 5a, and patterned amorphous silicon film Are sequentially etched.
By this etching, the tunnel oxide film 3 is removed,
A control gate electrode 8 made of this polycrystalline silicon film and a floating gate electrode 4a made of this amorphous silicon film are formed.

After the photoresist film is removed, 9
The thickness of the silicon substrate 1, the floating gate electrode 4a, and the exposed surface of the control gate electrode 8 is reduced to 1
A silicon oxide film 9 of about 5 nm is formed. Next, an energy of 70 keV using the control gate electrode 8 as a mask,
Arsenic ions are implanted at a dose of about 7 × 10 ¹⁵ cm ⁻² , and the ion implantation is performed in a mixed atmosphere of oxygen and an inert gas.
Heat treatment is performed at 000 ° C. for about 20 minutes to form an N-type source diffusion layer 10 and a drain diffusion layer 11 on the surface of the silicon substrate 1. PSG film or BP on the whole surface
An interlayer insulating film 12 made of an SG film is deposited, and a contact hole 13 reaching the drain diffusion layer 11 is formed. Next, the drain diffusion layer 11 is formed through the contact hole 13.
Aluminum wiring 14 (bit line) connected to the substrate is formed.

According to the first embodiment, since the upper surface of the floating gate electrode 4a has irregularities, even if the area occupied by the floating gate electrode 4a (ie, the area occupied by the memory cell) is not increased, the control can be performed. The effective facing area between the gate electrode 8 and the floating gate electrode 4a increases. For this reason, the thickness of the dielectric film including the silicon oxide film 7a, the silicon nitride film 6a, and the silicon oxide film 5a is made relatively thin (reduction of the electrostatic breakdown voltage between the control gate electrode 8 and the floating gate electrode 4a, Without deteriorating the holding characteristics), it is possible to increase the capacitance value between the control gate electrode 8 and the floating gate electrode 4a, and to lower the erase voltage. Referring to FIG. 2 which is a cross-sectional view of the floating gate electrode 4b of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.
Is formed of an amorphous silicon film having uneven top and side surfaces. A method for forming a memory cell of this nonvolatile semiconductor memory device is as follows.

First, after the tunnel oxide film 3 is formed by the same method as in the first embodiment, a film thickness of 25
An amorphous silicon film of about 0 nm is deposited. Next, in a predetermined region on field oxide film 2 covered by the same control gate electrode formed later, patterning is performed so that this amorphous silicon film is divided. Subsequently, after the natural oxide film on the surface of the patterned amorphous silicon film is removed, the upper surface and the side surface of the patterned amorphous silicon film are uneven by the same method as in the first embodiment. become. Next, a silicon oxide film 5b having a thickness of about 12 nm is formed on the exposed surface of the patterned amorphous silicon film by thermal oxidation. Further, a silicon nitride film 6b having a thickness of about 10 nm is deposited on the entire surface by low pressure chemical vapor deposition, and a silicon oxide film 7b is formed on the surface of the silicon nitride film 6b by thermal oxidation. The subsequent steps are the same as in the first embodiment.

The floating gate electrode 4b of the second embodiment described above
Is different from the floating gate electrode 4a of the first embodiment.
The side is also uneven. For this reason, the second embodiment can reduce the occupied area of the memory cell or lower the erase voltage as compared with the first embodiment.

[0017]

As described above, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the area occupied by the memory cell is increased, the holding characteristic between the floating gate electrode and the control gate electrode is degraded, and Without this, which causes a decrease in withstand voltage,
The erasing voltage can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view of a second embodiment of the present invention.

FIG. 3 is a plan view and a cross-sectional view of a conventional method for manufacturing a nonvolatile semiconductor memory device.

[Explanation of symbols]

Reference Signs List 1 P-type silicon substrate 2 Field oxide film 3 Tunnel oxide film 4a, 4b, 4c Floating gate electrode 5a, 5b, 5c, 7a, 7b, 7c, 9 Silicon oxide film 6a, 6b, 6c Silicon nitride film 8 Control gate electrode Reference Signs List 10 N-type source diffusion layer 11 N-type drain diffusion layer 12 Interlayer insulating film 13 Contact hole 14 Aluminum wiring

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-98173 (JP, A) JP-A-1-239957 (JP, A) JP-A-64-37876 (JP, A) JP-A-62-1987 145872 (JP, A) JP-A-4-74477 (JP, A) JP-A-60-167472 (JP, A) JP-A-60-18968 (JP, A) JP-A-63-43378 (JP, A) JP-A-1-133372 (JP, A) JP-A-63-306672 (JP, A) JP-A-3-263370 (JP, A) JP-A-3-272165 (JP, A) JP-A-5-129204 (JP, A) JP-A-6-5805 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A step of selectively forming a field oxide film on a surface of a P-type silicon substrate to form a tunnel oxide film, a step of forming an amorphous silicon film over the entire surface, and a heat treatment in a vacuum Forming irregularities on the surface of the amorphous silicon film by the step of: patterning the amorphous silicon film having irregularities on the surface into a predetermined shape; and at least exposing the exposed surface of the patterned amorphous silicon film. Forming a covering dielectric film, forming a conductive film over the entire surface, etching the conductive film using a photoresist film having a predetermined pattern as a mask to form a control gate electrode, and forming the control gate electrode; Forming a floating gate electrode by etching the amorphous silicon film patterned; and forming N-type source and drain diffusion layers. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 2. A step of selectively forming a field oxide film on a surface of a P-type silicon substrate to form a tunnel oxide film; a step of forming an amorphous silicon film over the entire surface; Patterning the film into a predetermined shape; forming irregularities on the exposed surface of the amorphous silicon film patterned by heat treatment in a vacuum; and forming at least an exposed surface of the patterned amorphous silicon film. Forming a covering dielectric film, forming a conductive film over the entire surface, etching the conductive film using a photoresist film having a predetermined pattern as a mask to form a control gate electrode, and forming the control gate electrode; Forming a floating gate electrode by etching the patterned amorphous silicon film; and forming N-type source and drain diffusion layers. A method for manufacturing a nonvolatile semiconductor memory device, comprising: