KR100489530B1 - Method for manufacturing flash device by using high capacitor - Google Patents
Method for manufacturing flash device by using high capacitor Download PDFInfo
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- KR100489530B1 KR100489530B1 KR10-2002-0054015A KR20020054015A KR100489530B1 KR 100489530 B1 KR100489530 B1 KR 100489530B1 KR 20020054015 A KR20020054015 A KR 20020054015A KR 100489530 B1 KR100489530 B1 KR 100489530B1
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- control gate
- polysilicon
- gate
- flash
- floating gate
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- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000003990 capacitor Substances 0.000 title claims description 16
- 238000000034 method Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 239000007943 implant Substances 0.000 claims abstract description 6
- 210000004027 cell Anatomy 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 8
- 210000004692 intercellular junction Anatomy 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims 2
- 230000008878 coupling Effects 0.000 abstract description 7
- 238000010168 coupling process Methods 0.000 abstract description 7
- 238000005859 coupling reaction Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract 1
- 238000002513 implantation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
본 발명은 플로팅 게이트와 컨트롤 게이트 간의 접촉 면적을 증가시켜 커패시티브 커플링 비율을 증가시켜 낮은 전압에도 각종 프로그램을 구동시키기 위한 것으로, 이를 위한 작용은 실리콘 기판 상에 아이솔레이션을 위한 플래쉬 터널 산화막을 형성하며, 그 위에 폴리 실리콘을 증착하여 플로팅 게이트를 형성하는 단계와, 형성된 플로팅 게이트 상에 ONO 계층을 증착한 다음, 그 위에 컨트롤 게이트로 사용할 폴리 실리콘을 증착하는 단계와, 컨트롤 게이트를 패터닝 및 식각하여 S/D 임플란트를 실시하여 S/D를 형성하는 단계와, 패터닝된 컨트롤 게이트 상에 포트 레지스트를 스트립시켜 적층형 플래쉬 셀을 형성하는 단계를 포함한다. 따라서, 플로팅 게이트와 컨트롤 게이트 간의 접촉 면적을 증가시켜 커패시티브 커플링 비율을 증가시켜 낮은 전압에도 각종 프로그램을 구동시킬 수 있어 그 성능 향상에 바탕이 되는 효과가 있다. The present invention is to drive a variety of programs even at low voltage by increasing the capacitive coupling ratio by increasing the contact area between the floating gate and the control gate, the purpose is to form a flash tunnel oxide for isolation on the silicon substrate Depositing polysilicon thereon to form a floating gate; depositing an ONO layer on the formed floating gate; depositing polysilicon thereon to be used as a control gate; patterning and etching the control gate; Performing an S / D implant to form an S / D, and stripping the port resist onto the patterned control gate to form a stacked flash cell. Therefore, by increasing the contact area between the floating gate and the control gate to increase the capacitive coupling ratio, it is possible to drive a variety of programs even at a low voltage, which has the effect of improving the performance.
Description
본 발명은 하이 커패시터(high capacitor)를 이용한 플래쉬 소자 제조방법에 관한 것으로, 특히 비휘발성 플래쉬 메모리 셀 소자 제조에 있어서, 플로팅 게이트(Floating gate)와 컨트롤 게이트(control gate) 간의 접촉 면적을 증가시켜 커패시티브 커플링 비율(capacitive coupling ratio)을 증가시켜 낮은 전압에도 각종 프로그램을 구동시킬 수 있도록 하는 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash device using a high capacitor, and more particularly, to manufacturing a nonvolatile flash memory cell device by increasing the contact area between a floating gate and a control gate. The present invention relates to a manufacturing method for increasing various capacitive coupling ratios to drive various programs even at low voltages.
통상적으로, 비휘발성 플래쉬 메모리 셀 소자 제조에서의 대표적인 셀 구조는 단순 적층 구조의 이톡스(etox) 셀과 1셀당 2트랜지스터 구조의 채널분리(split gate)형 셀(cell)로 구분된다.Typically, typical cell structures in nonvolatile flash memory cell device fabrication are divided into etox cells having simple stacked structures and split gate type cells having two transistor structures per cell.
이러한, 셀 구조는 모두 플로팅 게이트에 프로그램을 구동하기 위해 플로팅 게이트와 컨트롤 게이트간의 커패시턴스를 증가시켜 사용하는 것이다.These cell structures are all used to increase the capacitance between the floating gate and the control gate to drive a program to the floating gate.
도 1을 참조하면, 종래 플래쉬 셀중 단순 적층 구조의 이톡스 셀 단면 구조를 도시한 도면으로, 실리콘 기판(10) 상에 소스/드레인(Source/Drain : S/D) 임플란트를 실시하여 S/D 에리어(20)를 형성한다.Referring to FIG. 1, a cross-sectional view of a simple stack structure of an ITOX cell is shown. FIG. 1 shows a source / drain (S / D) implant on a silicon substrate 10 to provide S / D. The area 20 is formed.
S/D 에리어(20)가 형성된 상태에서, 그 위에 플래쉬 터널 산화막(30)을 증착하며, 플래쉬 터널 산화막(30)상에 플로팅 게이트(40)를 형성한다.In the state where the S / D area 20 is formed, the flash tunnel oxide film 30 is deposited thereon, and the floating gate 40 is formed on the flash tunnel oxide film 30.
플로팅 게이트(40)를 형성한 상태에서 ONO 계층(50)을 증착하고, 그 위에 컨트롤 게이트(60)를 형성한다.The ONO layer 50 is deposited in a state where the floating gate 40 is formed, and a control gate 60 is formed thereon.
이와 같이, S/D 에리어(20)와 플로팅 게이트(40) 사이에 유도되는 커패시턴스 밸유와, 플로팅 게이트(40)와 컨트롤 게이트(60) 사이에 유도되는 커패시턴스 밸유를 이용하여 커패시티브 커플링 비율을 구하게 될 경우, 각각의 밸유 접촉 면적이 작아 커패시티브 커플링 비율이 감소하게 되어 낮은 전압에서 프로그램이 구동되지 않게 되는 문제점이 있다. As described above, the capacitive coupling ratio is obtained by using the capacitance value induced between the S / D area 20 and the floating gate 40 and the capacitance value induced between the floating gate 40 and the control gate 60. In this case, each value contact area is small so that the capacitive coupling ratio is reduced, thereby preventing the program from being driven at a low voltage.
따라서, 본 발명은 상술한 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 플로팅 게이트와 컨트롤 게이트 간의 접촉 면적을 증가시켜 커패시티브 커플링 비율을 증가시켜 낮은 전압에도 각종 프로그램을 구동시킬 수 있도록 하는 하이 커패시터를 이용한 플래쉬 소자 제조방법을 제공함에 있다. Accordingly, the present invention has been made to solve the above-described problems, the object of which is to increase the contact area between the floating gate and the control gate to increase the capacitive coupling ratio to drive various programs at low voltage A flash device manufacturing method using a high capacitor is provided.
이러한 목적을 달성하기 위한 본 발명의 일 실시 예에 따른 하이 커패시터를 이용한 플래쉬 소자 제조방법은 실리콘 기판 상에 아이솔레이션을 위한 플래쉬 터널 산화막을 형성하며, 그 위에 폴리 실리콘을 증착하여 플로팅 게이트를 형성하는 단계와, 형성된 플로팅 게이트 상에 ONO 계층을 증착한 다음, 그 위에 컨트롤 게이트로 사용할 폴리 실리콘을 증착하는 단계와, 컨트롤 게이트를 패터닝 및 식각하여 S/D 임플란트를 실시하여 S/D를 형성하는 단계와, 패터닝된 컨트롤 게이트 상에 포트 레지스트를 스트립시켜 적층형 플래쉬 셀을 형성하는 단계를 포함하는 것을 특징으로 한다.또한, 상술한 목적을 달성하기 위한 본 발명의 다른 실시 예에 따른 하이 커패시터를 이용한 플래쉬 소자 제조방법은 실리콘 기판 상에 아이솔레이션을 위한 플래쉬 터널 산화막을 형성하며, 그 위에 폴리 실리콘을 증착하여 플로팅 게이트를 형성하는 단계와, 형성된 플로팅 게이트를 식각하여 S/D 임플란트를 실시하여 S/D를 형성하며, 포트 레지스트 식각을 실시하여 셀 정션을 구성하는 단계와, 플로팅 게이트 상에 ONO 계층을 증착하고, 그 위에 컨트롤 게이트로 사용할 폴리 실리콘을 증착한 다음에 컨트롤 게이트 상에 컨트롤 게이트 페터닝을 형성하는 단계를 포함하는 것을 특징으로 한다.A flash device manufacturing method using a high capacitor according to an embodiment of the present invention for achieving this purpose is to form a flash tunnel oxide film for isolation on a silicon substrate, by depositing polysilicon thereon to form a floating gate And depositing an ONO layer on the formed floating gate, and then depositing polysilicon to be used as a control gate thereon, and patterning and etching the control gate to perform S / D implantation to form S / D; And forming a stacked flash cell by stripping the port resist on the patterned control gate. In addition, a flash device using a high capacitor according to another embodiment of the present invention for achieving the above object. The fabrication method is a flash tunnel for isolation on a silicon substrate. Forming a film, depositing polysilicon thereon to form a floating gate; etching the formed floating gate to perform S / D implantation to form S / D; and forming a cell junction by performing port resist etching. And depositing an ONO layer on the floating gate, depositing polysilicon for use as a control gate thereon, and then forming control gate patterning on the control gate.
삭제delete
이하, 첨부된 도면을 참조하여 본 발명의 구성 및 동작에 대하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.
도 2a 내지 도 2c는 본 발명에 따른 하이 커패시터를 이용한 플래쉬 소자 제조방법을 도시한 도면에 대하여 설명한다. 2A to 2C are views illustrating a flash device manufacturing method using a high capacitor according to the present invention.
즉, 도 2a를 참조하면, 실리콘 기판(10) 상에 아이솔레이션을 위한 플래쉬 터널 산화막(30)을 형성하며, 그 위에 폴리 실리콘을 증착하여 플로팅 게이트(40)를 형성한다. That is, referring to FIG. 2A, a flash tunnel oxide layer 30 for isolation is formed on the silicon substrate 10, and polysilicon is deposited thereon to form the floating gate 40.
이때, 증착되는 폴리 실리콘은 증착 초기에는 터널 산화막과의 접촉을 위해 하드한 폴리 실리콘을 증착하고, 단계적으로 증착 온도를 변화시켜 최종적으로 컨트롤한 게이트와 접촉이 일어나는 부분은 러지드 폴리-실리콘(rugged poly-silicon)이 형성되는 구조를 가지고 있다. 여기서, 러지드 폴리-실리콘은 향후 증착되는 컨트롤 게이트와의 접촉면적을 증대시키는 역할을 한다.At this time, the deposited polysilicon deposits hard polysilicon for contact with the tunnel oxide film at the initial stage of deposition, and changes the deposition temperature step by step, so that the contact with the finally controlled gate is rugged polysilicon (rugged). poly-silicon) is formed. Here, the rugged poly-silicon serves to increase the contact area with the control gate to be deposited in the future.
이후, 도 2b를 참조하면, 플로팅 게이트(40)를 형성한 상태에서, 그 위에 ONO 계층(50)을 증착한 다음, 그 위에 컨트롤 게이트(60)로 사용할 폴리 실리콘을 증착한다.2B, in the state where the floating gate 40 is formed, the ONO layer 50 is deposited thereon, and then polysilicon is deposited thereon to be used as the control gate 60.
다음으로, 도 2c에 도시된 바와 같이, 컨트롤 게이트(60)를 패터닝하고, 이어서 식각하여 S/D 임플란트를 실시하여 S/D(20)를 형성하며, 패터닝된 컨트롤 게이트(60) 상에 포트 레지스트(Photo Resist : PR)(70)를 스트립시켜 적층형 플래쉬 셀을 형성한다.Next, as shown in FIG. 2C, the control gate 60 is patterned and subsequently etched to perform an S / D implant to form the S / D 20, and to form a port on the patterned control gate 60. A resist (Photo Resist: PR) 70 is stripped to form a stacked flash cell.
한편, 도 3a 내지 도 3c를 참조하면, 본 발명의 다른 실시 예에 따른 하이 커패시터를 이용한 플래쉬 소자 제조방법에 대하여 도시한 도면이다.Meanwhile, referring to FIGS. 3A to 3C, a method of manufacturing a flash device using a high capacitor according to another embodiment of the present invention is illustrated.
즉, 도 3a를 참조하면, 실리콘 기판(10) 상에 아이솔레이션을 위한 플래쉬 터널 산화막(30)을 형성하며, 그 위에 폴리 실리콘을 증착하여 플로팅 게이트(40)를 형성한다. That is, referring to FIG. 3A, the flash tunnel oxide layer 30 for isolation is formed on the silicon substrate 10, and polysilicon is deposited thereon to form the floating gate 40.
이때, 증착되는 폴리 실리콘은 증착 초기에는 터널 산화막과의 접촉을 위해 하드한 폴리 실리콘을 증착하고, 단계적으로 증착 온도를 변화시킴으로 최종적으로 컨트롤한 게이트와 접촉이 일어나는 부분은 러지드 폴리-실리콘이 형성되는 구조를 가지고 있다. 여기서, 러지드 폴리-실리콘은 향후 증착되는 컨트롤 게이트와의 접촉면적을 증대시키는 역할을 한다.At this time, the deposited polysilicon deposits hard polysilicon for contact with the tunnel oxide film at the initial stage of deposition and changes the deposition temperature step by step so that the part where contact with the finally controlled gate is formed is formed of the rugged polysilicon. It has a structure. Here, the rugged poly-silicon serves to increase the contact area with the control gate to be deposited in the future.
이후, 도 3b를 참조하면, 플로팅 게이트(40)를 형성한 상태에서, 식각하여 S/D 임플란트를 실시하여 S/D(20)를 형성하며, PR 식각을 실시하여 셀 정션을 구성한다.Subsequently, referring to FIG. 3B, in the state in which the floating gate 40 is formed, the S / D 20 is formed by etching the S / D implant to form the cell junction by performing the PR etching.
다음으로, 도 3c에 도시된 바와 같이, 셀 정션이 구성된 상태에서, 플로팅 게이트(40) 상에 ONO 계층(50)을 증착하고, 그 위에 컨트롤 게이트(60)로 사용할 폴리 실리콘을 증착하며, 최종적으로 컨트롤 게이트(60) 상에 컨트롤 게이트 패터닝(80)을 형성한다. 여기서, 컨트롤 게이트(60)는 S/D(20)와 직교하는 방향으로 형성하는 셀 구조로 이루어지며, 셀 정션을 컨트롤 게이트 형성 이전에 구성해야한다. Next, as shown in FIG. 3C, in a state where the cell junction is configured, the ONO layer 50 is deposited on the floating gate 40, and the polysilicon is deposited thereon to be used as the control gate 60. As a result, control gate patterning 80 is formed on the control gate 60. Here, the control gate 60 is formed of a cell structure formed in a direction orthogonal to the S / D 20, and the cell junction must be configured before forming the control gate.
상기와 같이 설명한 본 발명은 플로팅 게이트와 컨트롤 게이트 간의 접촉 면적을 증가시켜 커패시티브 커플링 비율을 증가시켜 낮은 전압에도 각종 프로그램을 구동시킬 수 있어 그 성능 향상에 바탕이 되는 효과가 있다. As described above, the present invention can increase the capacitive coupling ratio by increasing the contact area between the floating gate and the control gate, thereby driving various programs even at low voltage, thereby improving the performance.
도 1은 종래 플래쉬 셀중 단순 적층 구조의 이톡스 셀 단면 구조를 도시한 도면이고, 1 is a view showing a cross-sectional structure of the ITOX cell of a simple stacked structure of a conventional flash cell,
도 2는 본 발명에 따른 하이 커패시터를 이용한 플래쉬 소자 제조방법에 대하여 도시한 도면이며,2 is a view showing a flash device manufacturing method using a high capacitor according to the present invention,
도 3은 본 발명의 다른 실시 예에 따른 하이 커패시터를 이용한 플래쉬 소자 제조방법에 대하여 도시한 도면이다.3 is a view showing a flash device manufacturing method using a high capacitor according to another embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 실리콘 기판 20 : S/D 에리어10: silicon substrate 20: S / D area
30 : 플래쉬 터널 산화막 40 : 플로팅 게이트30 flash tunnel oxide film 40 floating gate
50 : ONO 계층 60 : 컨트롤 게이트50: ONO layer 60: control gate
70 : 포트 레지스트 80 : 컨트롤 게이트 페터닝70: Port Resist 80: Control Gate Patterning
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089867A (en) * | 1991-05-06 | 1992-02-18 | Micron Technology, Inc. | High control gate/floating gate coupling for EPROMs, E2 PROMs, and Flash E2 PROMs |
| JPH05110107A (en) * | 1991-10-14 | 1993-04-30 | Sony Corp | Semiconductor device having floating gate |
| JPH06177396A (en) * | 1992-12-09 | 1994-06-24 | Nec Corp | Manufacture of nonvolatile semiconductor storage device |
| US6069382A (en) * | 1998-02-11 | 2000-05-30 | Cypress Semiconductor Corp. | Non-volatile memory cell having a high coupling ratio |
| US6162684A (en) * | 1999-03-11 | 2000-12-19 | Advanced Micro Devices, Inc. | Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices |
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2002
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089867A (en) * | 1991-05-06 | 1992-02-18 | Micron Technology, Inc. | High control gate/floating gate coupling for EPROMs, E2 PROMs, and Flash E2 PROMs |
| JPH05110107A (en) * | 1991-10-14 | 1993-04-30 | Sony Corp | Semiconductor device having floating gate |
| JPH06177396A (en) * | 1992-12-09 | 1994-06-24 | Nec Corp | Manufacture of nonvolatile semiconductor storage device |
| US6069382A (en) * | 1998-02-11 | 2000-05-30 | Cypress Semiconductor Corp. | Non-volatile memory cell having a high coupling ratio |
| US6162684A (en) * | 1999-03-11 | 2000-12-19 | Advanced Micro Devices, Inc. | Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices |
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