KR20040022491A - Method for manufacturing flash memory cell device by using high capacitor - Google Patents
Method for manufacturing flash memory cell device by using high capacitor Download PDFInfo
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- KR20040022491A KR20040022491A KR1020020054018A KR20020054018A KR20040022491A KR 20040022491 A KR20040022491 A KR 20040022491A KR 1020020054018 A KR1020020054018 A KR 1020020054018A KR 20020054018 A KR20020054018 A KR 20020054018A KR 20040022491 A KR20040022491 A KR 20040022491A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims abstract 6
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 239000007943 implant Substances 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 210000004027 cell Anatomy 0.000 claims description 29
- 238000000151 deposition Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 6
- 210000004692 intercellular junction Anatomy 0.000 claims description 2
- 230000008878 coupling Effects 0.000 abstract description 6
- 238000010168 coupling process Methods 0.000 abstract description 6
- 238000005859 coupling reaction Methods 0.000 abstract description 6
- 238000002513 implantation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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Abstract
Description
본 발명은 하이 커패시터를 이용한 플래쉬 메모리 셀 소자 제조방법에 관한 것으로, 특히 플로팅 게이트(Floating gate)와 컨트롤 게이트(control gate) 간의 접촉 면적을 증가시키고 이로 인해 유발되는 커패시티브 커플링 비율(capacitive coupling ratio)이 증가되어 낮은 전압에서도 프로그램을 구동시킬 수 있도록 하는 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell device using a high capacitor, and in particular, to increase the contact area between a floating gate and a control gate and to thereby cause a capacitive coupling ratio. The present invention relates to a manufacturing method for increasing a ratio so that a program can be driven even at a low voltage.
통상적으로, 반도체의 비휘발성 플래쉬 메모리 셀 소자 제조에서의 대표적인 셀 구조는 단순 적층 구조의 이톡스(etox) 셀과 1셀당 2트랜지스터 구조의 채널분리(split gate)형 셀(cell)로 구분된다.Typically, typical cell structures in the fabrication of nonvolatile flash memory cell devices of semiconductors are divided into etox cells having simple stacked structures and split gate type cells having two transistor structures per cell.
이러한, 셀 구조는 모두 플로팅 게이트(floating gate)에 프로그램을 구동하기 위해 플로팅 게이트와 컨트롤 게이트간의 커패시턴스를 증가시켜 사용하는 것이다.All of these cell structures are used to increase the capacitance between the floating gate and the control gate to drive a program to the floating gate.
도 1을 참조하면, 종래 플래쉬 셀중 단순 적층 구조의 이톡스 셀 단면 구조를 도시한 도면으로, 실리콘 기판(Si-substrate)(1) 상에 소스/드레인(Source/Drain : S/D) 임플란트(implant)를 실시하여 S/D 에리어(area)(2)를 형성한다.Referring to FIG. 1, a cross-sectional view of an ITOX cell cross-sectional structure of a simple stacked structure of a conventional flash cell is provided. A source / drain (S / D) implant (Si / substrate) on a silicon substrate implant) to form an S / D area (2).
S/D 에리어(2)가 형성된 상태에서, 그 위에 플래쉬 터널 산화막(flash tunnel oxide)(3)을 증착하며, 플래쉬 터널 산화막(3)상에 플로팅 게이트(floating gate)(4)를 형성한다.With the S / D area 2 formed, a flash tunnel oxide 3 is deposited thereon, and a floating gate 4 is formed on the flash tunnel oxide 3.
플로팅 게이트(4)를 형성한 상태에서 ONO 계층(layer)(5)을 증착하고, 그 위에 컨트롤 게이트(6)를 형성한다.The ONO layer 5 is deposited in a state where the floating gate 4 is formed, and the control gate 6 is formed thereon.
이와 같이, S/D 에리어(2)와 플로팅 게이트(4) 사이에 유도되는 커패시턴스 밸유(capacitance value)(Cd)와, 플로팅 게이트(4)와 컨트롤 게이트(6) 사이에 유도되는 커패시턴스 밸유(capacitance value)(Cfc)를 이용하여 커패시티브 커플링 비율(capacitive coupling ratio)을 구한다.In this way, the capacitance value Cd induced between the S / D area 2 and the floating gate 4 and the capacitance value induced between the floating gate 4 and the control gate 6 are as follows. The capacitive coupling ratio is obtained using value) (Cfc).
즉, 비율 공식(F) = Cd(Drain Capacitance) / Cfc(Floating/Control Gate Capacitance)로서, 각각의 밸유 접촉 면적이 작아질 경우, 커패시티브 커플링 비율(capacitive coupling ratio)이 감소하게 되어 낮은 전압에서 프로그램이 구동되지 않게 되는 문제점이 있다.That is, ratio formula (F) = Cd (Drain Capacitance) / Cfc (Floating / Control Gate Capacitance), and when each valuation contact area becomes small, the capacitive coupling ratio decreases and thus There is a problem that the program is not driven at the voltage.
따라서, 본 발명은 상술한 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 플로팅 게이트(Floating gate)와 컨트롤 게이트(control gate) 간의 접촉 면적을 증가시키고 이로 인해 유발되는 커패시티브 커플링 비율(capacitive coupling ratio)이 증가되어 낮은 전압에서 각종 프로그램을 구동시킬 수 있도록 하는 하이 커패시터를 이용한 플래쉬 메모리 셀 소자 제조방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-described problems, the object of which is to increase the contact area between the floating gate and the control gate (capacitive) capacitive caused by this The present invention provides a method of manufacturing a flash memory cell device using a high capacitor to increase a coupling ratio and to drive various programs at low voltage.
이러한 목적을 달성하기 위한 본 발명에서 하이 커패시터를 이용한 플래쉬 메모리 셀 소자 제조방법은 실리콘 기판(Si-Substrate) 상에 아이솔레이션(isolation)을 위한 플래쉬 터널 산화막(flash tunnel oxide)을 형성하며, 그 위에 플로팅 게이트(floating gate)로 사용할 폴리 실리콘(poly silicon)을 증착하는 단계; 플로팅 게이트 상에 버퍼 산화막(buffer oxide)을 증착하고, 패턴 식각(pattern etch)을 실시하여 포트 레지스트(Photo Resist : PR)를스트립(strip)하는 단계; 버퍼 산화막을 EPD(Etch Pit Density)를 이용하여 식각을 수행하며, 산화막을 증착하고 열처리를 실시하여 플로팅 게이트 상에 LOCOS(local oxidation of silicon)를 형성하는 단계; 패턴 식각(patten etch)을 실시한 상태에서 평면 질화막 상에 존재하는 폴리 실리콘(poly silicon)을 제거한 후, LOCOS로 형성된 산화막을 제거하여 요철이 있는 플로팅 게이트(floating gate)를 형성하는 단계; 형성된 플로팅 게이트(floating gate) 상에 ONO 계층을 증착하고 컨트롤 게이트(control gate)로 사용할 폴리 실리콘을 증착하는 단계; 폴리 실리콘을 증착한 상태에서 소스/드레인(Source/Drain : S/D) 임플란트(implant)를 실시하여 S/D를 형성하고, 컨트롤 게이트(control gate)를 패터닝(patterning) 및 식각(etch)하여 적층형 플래쉬 셀(flash cell)을 형성하는 단계를 포함하는 것을 특징으로 한다.In the present invention, a method of manufacturing a flash memory cell device using a high capacitor to form a flash tunnel oxide for isolation on a silicon substrate (Si-Substrate), and floating thereon Depositing poly silicon for use as a floating gate; Depositing a buffer oxide layer on the floating gate and performing a pattern etch to strip a photo resist (PR); Etching the buffer oxide film using an etching pitch density (EPD), depositing an oxide film, and performing a heat treatment to form a local oxidation of silicon (LOCOS) on the floating gate; Removing poly silicon existing on the planar nitride film in a pattern etched state, and then removing an oxide film formed of LOCOS to form a floating gate having irregularities; Depositing an ONO layer on the formed floating gate and depositing polysilicon for use as a control gate; S / D is formed by source / drain (S / D) implantation while polysilicon is deposited, and the control gate is patterned and etched. Forming a stacked flash cell (flash cell) is characterized in that it comprises.
또한, 상술한 목적을 달성하기 위한 본 발명의 다른 실시 예에 따른 하이 커패시터를 이용한 플래쉬 메모리 셀 소자 제조방법은 실리콘 기판 상에 아이솔레이션(isolation)을 위한 플래쉬 터널 산화막(flash tunnel oxide)을 형성하며, 그 위에 플로팅 게이트(floating gate)로 사용할 폴리 실리콘(poly silicon)을 증착하는 단계; 플로팅 게이트 상에 버퍼 산화막(buffer oxide)을 증착하고, 패턴 식각(pattern etch)을 실시하여 PR을 스트립(strip)하는 단계; 버퍼 산화막을 EPD를 이용하여 식각을 수행하며, 산화막을 증착하고 열처리를 실시하여 플로팅 게이트 상에 LOCOS를 형성하는 단계; PR을 스트립한 상태에서, 패턴 식각(pattern etch)하여 S/D 임플란트(implant)를 실시하여 S/D를 형성하며, 패턴 식각을 실시한 패턴에서 평면 질화막 상에 존재하는 폴리 실리콘(poly silicon)을 제거한 후,LOCOS로 형성된 산화막을 제거하여 요철이 있는 플로팅 게이트(floating gate)를 형성하는 단계; 형성된 플로팅 게이트(floating gate) 상에 ONO 계층을 증착하고 컨트롤 게이트(control gate)로 사용할 폴리 실리콘을 증착하는 단계를 포함하는 것을 특징으로 한다.In addition, the flash memory cell device manufacturing method using a high capacitor according to another embodiment of the present invention for achieving the above object to form a flash tunnel oxide (flash tunnel oxide) for isolation (isolation) on a silicon substrate, Depositing poly silicon thereon for use as a floating gate; Depositing a buffer oxide on a floating gate and performing a pattern etch to strip the PR; Etching the buffer oxide film using EPD, depositing an oxide film, and performing a heat treatment to form a LOCOS on the floating gate; In the stripped state of the PR, pattern etching is performed to form S / D by S / D implantation, and polysilicon on the planar nitride film is formed in the pattern etched pattern. Removing the oxide film formed of LOCOS to form a floating gate having irregularities; Depositing an ONO layer on the formed floating gate and depositing polysilicon for use as a control gate.
도 1은 종래 플래쉬 셀중 단순 적층 구조의 이톡스 셀 단면 구조를 도시한 도면이며,1 is a view showing a cross-sectional structure of the ITOX cell of a simple stacked structure of a conventional flash cell,
도 2는 본 발명에 따른 하이 커패시터를 이용한 플래쉬 메모리 셀 소자 제조방법에 대하여 도시한 도면이며,2 is a view illustrating a method of manufacturing a flash memory cell device using a high capacitor according to the present invention.
도 3은 본 발명의 다른 실시 예에 따른 하이 커패시터를 이용한 플래쉬 메모리 셀 소자 제조방법에 대하여 도시한 도면이다.3 is a view illustrating a method of manufacturing a flash memory cell device using a high capacitor according to another embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 실리콘 기판 20 : S/D10: silicon substrate 20: S / D
30 : 플래쉬 터널 산화막 40 : 플로팅 게이트30 flash tunnel oxide film 40 floating gate
50 : 버퍼 산화막 60 : 포트 레지스트50: buffer oxide film 60: port resist
70 : LOCOS 80 : ONO 계층70: LOCOS 80: ONO Layer
90 : 컨트롤 게이트90: control gate
이하, 첨부된 도면을 참조하여 본 발명의 구성 및 동작에 대하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.
도 2a 내지 도 2c는 본 발명에 따른 하이 커패시터를 이용한 플래쉬 메모리 셀 소자 제조방법에 대하여 도시한 도면을 보다 상세하게 설명한다.2A to 2C will be described in more detail with reference to the drawings illustrating a method of manufacturing a flash memory cell device using a high capacitor according to the present invention.
즉, 도 2a를 참조하면, 실리콘 기판(Si-Substrate)(10) 상에 아이솔레이션(isolation)을 위한 플래쉬 터널 산화막(flash tunnel oxide)(30)을 형성하며, 그 위에 플로팅 게이트(floating gate)(40)로 사용할 폴리 실리콘(poly silicon)을 증착한다.That is, referring to FIG. 2A, a flash tunnel oxide 30 for isolation may be formed on a silicon substrate 10, and a floating gate may be formed thereon. 40) to deposit poly silicon (poly silicon) to be used.
이후, 플로팅 게이트(40) 상에 버퍼 산화막(buffer oxide) 또는 질화막(50)을 증착하고, 패턴 식각(pattern etch)을 실시하여 포트 레지스트(Photo Resist : PR)(60)를 스트립(strip)한다. 이때, 버퍼 산화막 또는 질화막(50)을 EPD(Etch Pit Density)를 이용하여 식각을 수행하며, 산화막을 증착하고 열처리를 실시하여 플로팅 게이트(40) 상에 LOCOS(local oxidation of silicon)(70)를 형성한다.Subsequently, a buffer oxide film or a nitride film 50 is deposited on the floating gate 40, and a pattern etch is performed to strip the photo resist 60. . In this case, the buffer oxide film or the nitride film 50 is etched using an etching pitch density (EPD), and the oxide film is deposited and subjected to a heat treatment to form a LOCOS 70 on the floating gate 40. Form.
다음으로, 도 2b에 도시된 바와 같이, 패턴 식각(patten etch)을 실시한 상태에서 평면 질화막 상에 존재하는 폴리 실리콘(poly silicon)을 제거한 후, LOCOS로 형성된 산화막을 제거하여 최종적으로 요철이 있는 플로팅 게이트(floating gate)(40)를 형성한다.Next, as shown in Figure 2b, after removing the polysilicon (poly silicon) present on the planar nitride film in a pattern etching (pattten etch), the oxide film formed of LOCOS is removed to finally float with irregularities A floating gate 40 is formed.
이후, 형성된 플로팅 게이트(floating gate)(40) 상에 ONO 계층(80)을 증착하고 컨트롤 게이트(control gate)(90)로 사용할 폴리 실리콘을 증착한다. 여기서, LOCOS로 형성된 산화막을 제거하면서 생성된 요철이 있는 플로팅 게이트(floating gate) 형성은 플로팅 게이트와 컨트롤 게이트와의 접촉 면적을 증대시키는 효과를 발생시킨다.Thereafter, the ONO layer 80 is deposited on the formed floating gate 40 and polysilicon is deposited to be used as the control gate 90. Here, the formation of the uneven floating gate formed while removing the oxide film formed of LOCOS has an effect of increasing the contact area between the floating gate and the control gate.
다음으로, 도 2c를 참조하면, 소스/드레인(Source/Drain : S/D) 임플란트(implant)를 실시하여 S/D(20)를 형성하고, 컨트롤 게이트(control gate)(90)를 패터닝(patterning)하고, 이어서 식각(etch)하여 적층형 플래쉬 셀(flash cell)을 형성한다.Next, referring to FIG. 2C, a source / drain (S / D) implant is performed to form the S / D 20, and the control gate 90 is patterned. patterning) and then etch to form stacked flash cells.
한편, 도 3a 내지 도 3c를 참조하면, 본 발명의 다른 실시 예에 따른 하이 커패시터를 이용한 플래쉬 메모리 셀 소자 제조방법에 대하여 도시한 도면을 보다 상세하게 설명한다.Meanwhile, referring to FIGS. 3A to 3C, a diagram illustrating a method of manufacturing a flash memory cell device using a high capacitor according to another embodiment of the present invention will be described in detail.
즉, 도 3a를 참조하면, 실리콘 기판(Si-Substrate)(10) 상에 아이솔레이션(isolation)을 위한 플래쉬 터널 산화막(flash tunnel oxide)(30)을 형성하며, 그 위에 플로팅 게이트(floating gate)(40)로 사용할 폴리 실리콘(poly silicon)을 증착한다.That is, referring to FIG. 3A, a flash tunnel oxide 30 for isolation may be formed on a silicon substrate 10, and a floating gate may be formed thereon. 40) to deposit poly silicon (poly silicon) to be used.
이후, 플로팅 게이트(40) 상에 버퍼 산화막(buffer oxide) 또는 질화막(50)을 증착하고, 패턴 식각(pattern etch)을 실시하여 포트 레지스트(Photo Resist :PR)(60)를 스트립(strip)한다. 이때, 버퍼 산화막 또는 질화막(50)을 EPD(Etch Pit Density)를 이용하여 식각을 수행하며, 산화막을 증착하고 열처리를 실시하여 플로팅 게이트(40) 상에 LOCOS(local oxidation of silicon)(70)를 형성한다.Subsequently, a buffer oxide film or a nitride film 50 is deposited on the floating gate 40, and a pattern etch is performed to strip the photo resist 60 (PR) 60. . In this case, the buffer oxide film or the nitride film 50 is etched using an etching pitch density (EPD), and the oxide film is deposited and subjected to a heat treatment to form a LOCOS 70 on the floating gate 40. Form.
다음으로, 도 3b에 도시된 바와 같이, PR(60)을 스트립한 상태에서, 패턴 식각(pattern etch)하여 소스/드레인(Source/Drain : S/D) 임플란트(implant)를 실시하여 S/D(20)를 형성하며, 패턴 식각을 실시한 패턴에서 평면 질화막 상에 존재하는 폴리 실리콘(poly silicon)을 제거한 후, LOCOS로 형성된 산화막을 제거하여 최종적으로 요철이 있는 플로팅 게이트(floating gate)(40)를 형성한다. 여기서, LOCOS로 형성된 산화막을 제거하면서 생성된 요철이 있는 플로팅 게이트(floating gate) 형성은 플로팅 게이트와 컨트롤 게이트와의 접촉 면적을 증대시키는 효과를 발생시킨다.Next, as shown in FIG. 3B, in a state in which the PR 60 is stripped, pattern etching is performed to perform source / drain (S / D) implantation to perform S / D implantation. (20), and after removing the polysilicon (poly silicon) present on the planar nitride film in the pattern-etched pattern, the oxide film formed of LOCOS is removed to finally the floating gate (40) with irregularities To form. Here, the formation of the uneven floating gate formed while removing the oxide film formed of LOCOS has an effect of increasing the contact area between the floating gate and the control gate.
이후, 도 3c에 도시된 바와 같이, 형성된 플로팅 게이트(floating gate) 상에 ONO 계층(80)을 증착하고 컨트롤 게이트(control gate)(90)로 사용할 폴리 실리콘을 증착한다. 여기서, 컨트롤 게이트(control gate)(90)는 S/D(20)와 직교하는 방향으로 형성하는 셀 구조로 이루어지며, 셀 정션(cell junction)을 컨트롤 게이트 형성 이전에 구성해야한다.Thereafter, as shown in FIG. 3C, an ONO layer 80 is deposited on the formed floating gate and polysilicon is deposited to be used as a control gate 90. Herein, the control gate 90 has a cell structure formed in a direction orthogonal to the S / D 20, and a cell junction must be formed before the control gate is formed.
상기와 같이 설명한 본 발명은 플로팅 게이트(Floating gate)와 컨트롤 게이트(control gate) 간의 접촉 면적을 증가시켜 커패시티브 커플링 비율(capacitive coupling ratio)을 증가시킴으로써, 낮은 전압에도 각종 프로그램을 구동시킬 수있어 플래쉬 셀의 프로그램 효율을 증가시킬 수 있는 효과가 있다.As described above, the present invention can increase the capacitive coupling ratio by increasing the contact area between the floating gate and the control gate, thereby driving various programs at low voltages. There is an effect that can increase the program efficiency of the flash cell.
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| US9202819B2 (en) | 2012-04-16 | 2015-12-01 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices and methods of fabricating the same |
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