KR20070062017A - Method for fabricating flash memory device - Google Patents

Method for fabricating flash memory device Download PDF

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KR20070062017A
KR20070062017A KR1020050121673A KR20050121673A KR20070062017A KR 20070062017 A KR20070062017 A KR 20070062017A KR 1020050121673 A KR1020050121673 A KR 1020050121673A KR 20050121673 A KR20050121673 A KR 20050121673A KR 20070062017 A KR20070062017 A KR 20070062017A
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layer
polysilicon
film
floating gate
flash memory
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KR1020050121673A
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Korean (ko)
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박석광
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A method for fabricating a flash memory device is provided to prevent an attack to an isolation layer in a process for etching a second polysilicon layer for floating gate. A tunnel oxide layer(21) and a first polysilicon layer(22) for floating gate are formed on a semiconductor substrate(20). A trench is formed on the semiconductor substrate. An isolation layer(23) is formed within the trench. An etch-stop layer(24) is formed on the isolation layer. A second polysilicon layer(25) for floating gate is formed on the entire structure. A floating gate including the first and second polysilicon layers is formed by removing the second polysilicon layer from an upper part of the isolation layer by performing a photo-lithography process.

Description

플래쉬 메모리 소자의 제조방법{Method for fabricating flash memory device}Manufacturing method of flash memory device {Method for fabricating flash memory device}

도 1은 종래 기술에 따른 플래쉬 메모리 소자의 단면도1 is a cross-sectional view of a flash memory device according to the prior art

도 2a 내지 도 2d는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조공정 단면도2A to 2D are cross-sectional views illustrating a manufacturing process of a flash memory device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

20 : 반도체 기판 21 : 터널 산화막20 semiconductor substrate 21 tunnel oxide film

22 : 제 1 폴리실리콘막 23 : 소자분리막22: first polysilicon film 23: device isolation film

24 : 식각 정지막 25 : 제 2 폴리실리콘막24: etching stop film 25: second polysilicon film

26 : ONO막 27: 컨트롤 게이트26: ONO film 27: control gate

본 발명은 플래쉬 메모리 소자의 제조방법에 관한 것으로, 특히 셀프 얼라인 쉘로우 트렌치 아이솔레이션 스킴(Self Aligned Shallow Trench Isolation scheme) 을 적용하는 플래쉬 메모리 소자에서 누설 전류를 방지하고 간섭 효과를 줄이기 위한 플래쉬 메모리 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a flash memory device using a self-aligned shallow trench isolation scheme to prevent leakage current and to reduce interference effects. It relates to a manufacturing method.

소자의 집적도가 향상됨에 따라서 이웃하는 플로팅 게이트간 기생 커패시턴스(parasitic capacitance)가 점점 증가되고 있다. 그 결과, 커플링 비(cell coupling ratio)가 감소되어 프로그램 스피드(program speed)가 저하되고, 간섭 효과(interference effect)가 증가되었다.As the integration of devices increases, parasitic capacitances between neighboring floating gates increase. As a result, the cell coupling ratio is reduced, the program speed is lowered, and the interference effect is increased.

간섭 효과란, 리딩(reading)하려는 셀(cell)의 바로 인접 셀을 프로그램(program)하게 되면 인접 셀의 플로팅 게이트의 전하(charge) 변화로 인해 바로 옆의 셀의 리드 동작시 인접 프로그램된 셀(programed cell)의 커패시턴스 작용으로 실제 셀의 문턱전압보다 높은 문턱전압이 리딩되는 현상을 일컫는 것으로, 간섭 효과가 증가되면 데이터 저장 및 유지 특성이 저하되게 되므로 간섭 효과를 줄일 필요가 있다.An interference effect means that when a cell immediately adjacent to a cell to be read is programmed, the adjacent programmed cell (a read operation of the next cell due to the charge change of the floating gate of the adjacent cell) It refers to a phenomenon in which the threshold voltage higher than the actual cell threshold is read due to the capacitance of the programmed cell. When the interference effect is increased, the data storage and retention characteristics are deteriorated, so it is necessary to reduce the interference effect.

이하, 첨부된 도면을 참조하여 종래 기술의 문제점을 설명하면 다음과 같다.Hereinafter, the problems of the prior art will be described with reference to the accompanying drawings.

도 1은 종래 기술에 따른 플래쉬 메모리 소자의 단면도로, 10은 반도체 기판, 11은 반도체 기판(10)을 활성영역과 필드 영역으로 구분하며 상기 반도체 기판(10) 표면위로 EFH(Effective Field Height)만큼 돌출된 소자분리막, 12는 활성영역의 반도체 기판(10)상에 형성되는 터널 산화막, 13은 터널 산화막(12)상에 형성되며 반도체 기판(10) 표면위로 돌출된 소자분리막(11)들 사이에 위치하는 플로팅 게이트용 제 1 폴리실리콘막, 14는 상기 소자분리막(11) 및 제 1 폴리실리콘막(13)상에 폴리실리콘막을 형성하고 소자분리막(11) 상부의 폴리실리콘막을 제거하여 형 성되는 플로팅 게이트용 제 2 폴리실리콘막, 15는 ONO막, 16은 컨트롤 게이트를 각각 나타낸다.1 is a cross-sectional view of a flash memory device according to the prior art, wherein 10 is a semiconductor substrate, and 11 is a semiconductor substrate 10 divided into an active region and a field region, and an EFH (Effective Field Height) is placed on the surface of the semiconductor substrate 10. Protruding device isolation film, 12 is a tunnel oxide film formed on the semiconductor substrate 10 in the active region, 13 is formed on the tunnel oxide film 12 between the device isolation film 11 protruding on the surface of the semiconductor substrate 10 The first polysilicon film 14 for the floating gate positioned is formed by forming a polysilicon film on the device isolation layer 11 and the first polysilicon film 13 and removing the polysilicon film on the device isolation film 11. A second polysilicon film for floating gate, 15 represents an ONO film, and 16 represents a control gate, respectively.

간섭 효과를 줄이기 위해서는 인접 셀간 기생 커패시턴스(parasitic capacitance)가 작아져야 하므로 EFH를 낮추면 되나, EFH를 낮추면 컨트롤 게이트(16)와 반도체 기판(10)간 거리가 가까워져 누설 전류가 발생되게 된다.In order to reduce the interference effect, parasitic capacitance between adjacent cells needs to be reduced, so the EFH can be lowered. However, if the EFH is lowered, the distance between the control gate 16 and the semiconductor substrate 10 is close, so that leakage current is generated.

이론적으로는 EFH를 적당히 낮출 경우 누설 전류가 발생되는 문제없이 간섭 효과를 줄일 수 있을 것으로 판단되지만, 실제로는 공정 마진이 부족한 일부 셀에서 플로팅 게이트용 제 2 폴리실리콘막(14) 식각 공정시 그 하부의 소자분리막(11)이 어택되게 되어 컨트롤 게이트(16)와 반도체 기판(10)간에 누설 전류가 발생되게 된다(A 참조).Theoretically, if the EFH is appropriately lowered, the interference effect can be reduced without causing a leakage current. However, in some cells where the process margin is insufficient, the lower part of the second polysilicon film 14 for the floating gate is etched during the etching process. The device isolation film 11 is attacked to generate a leakage current between the control gate 16 and the semiconductor substrate 10 (see A).

따라서, 본 발명은 전술한 종래 기술의 문제점을 해결하기 위하여 안출한 것으로써, 공정 마진을 향상시키어 누설 전류를 방지할 수 있는 플래쉬 메모리 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device capable of improving the process margin and preventing leakage current by devising to solve the above problems of the prior art.

본 발명의 다른 목적은 간섭 효과를 줄일 수 있는 플래쉬 메모리 소자의 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing a flash memory device that can reduce the interference effect.

본 발명에 따른 플래쉬 메모리 소자의 제조방법은 터널 산화막과 플로팅 게 이트용 제 1 폴리실리콘막이 형성된 반도체 기판에 트렌치를 형성하고 상기 트렌치내에 소자분리막을 형성하는 단계와, 상기 소자분리막상에 식각 정지막을 형성하는 단계와, 상기 전체 구조물상에 플로팅 게이트용 제 2 폴리실리콘막을 형성하는 단계와, 사진 식각 공정으로 상기 소자분리막 상부의 제 2 폴리실리콘막을 제거하여 상기 제 1 폴리실리콘막과 제 2 폴리실리콘막으로 구성되는 플로팅 게이트를 형성하는 단계를 포함한다.A method of manufacturing a flash memory device according to the present invention includes forming a trench in a semiconductor substrate on which a tunnel oxide film and a first polysilicon film for floating gates are formed, and forming an isolation layer in the trench, and forming an etch stop layer on the isolation layer. Forming a second polysilicon film for the floating gate on the entire structure, and removing the second polysilicon film on the device isolation layer by a photolithography process to remove the first polysilicon film and the second polysilicon film. Forming a floating gate consisting of a film.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허 청구 범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조공정 단면도이다. 2A to 2D are cross-sectional views illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.

SA-STI(Self Aligned Shallow Trench Isolation) 스킴의 플래쉬 메모리 소자 제조를 위해서는 먼저, 도 2a에 도시하는 바와 같이 반도체 기판(20)상에 터널 산화막(21)과 플로팅 게이트용 제 1 폴리실리콘막(22)을 차례로 형성하고 사진 식각 공정으로 필드 영역의 제 1 폴리실리콘막(22)과 터널 산화막(21)과 반도체 기판(20)을 일정 깊이 식각하여 소자분리용 트렌치(미도시)를 형성한다.In order to fabricate a flash memory device having a self-aligned shallow trench isolation (SA-STI) scheme, first, as shown in FIG. 2A, a tunnel oxide film 21 and a first polysilicon film 22 for floating gate are formed on a semiconductor substrate 20. ) Is sequentially formed, and a trench for removing an element is formed by etching the first polysilicon layer 22, the tunnel oxide layer 21, and the semiconductor substrate 20 in a field region by a photolithography process.

상기 제 1 폴리실리콘막(22)의 두께에 따라서 EFH가 결정되게 되므로 상기 제 1 폴리실리콘막(22)의 두께를 적절히 조절하는 것이 중요하다.Since the EFH is determined according to the thickness of the first polysilicon film 22, it is important to appropriately adjust the thickness of the first polysilicon film 22.

전술한 바와 같이 EFH가 작으면 누설 전류가 발생되고 EFH가 커지면 간섭 효과가 증가되게 되는 바, 이러한 점들을 고려하여 상기 제 1 폴리실리콘막(22)의 두께를 적절히 조절한다.As described above, when the EFH is small, leakage current is generated, and when the EFH is large, the interference effect is increased. In consideration of these points, the thickness of the first polysilicon film 22 is appropriately adjusted.

이어, 상기 소자분리용 트렌치가 매립되도록 전면에 HDP(High Density Plasma) 산화막을 증착하고 상기 제 1 폴리실리콘막(22)이 노출되도록 상기 HDP 산화막을 CMP(Chemical Mechanical Polishing)하여 상기 소자분리용 트렌치내에 소자분리막(23)을 형성한다.Subsequently, an HDP (High Density Plasma) oxide film is deposited on the entire surface of the device isolation trench to be buried, and the HDP oxide film is chemically mechanical polished (CMP) to expose the first polysilicon layer 22. An element isolation film 23 is formed in the film.

그런 다음, 전체 구조물상에 식각 정지막(24)을 형성한다.Then, an etch stop film 24 is formed on the entire structure.

상기 식각 정지막(24)으로는 폴리실리콘막 및 산화막과 식각 선택비가 상이한 물질 예를 들어, 질화막을 이용하여 형성한다.The etch stop layer 24 is formed using a material having a different etching selectivity from the polysilicon layer and the oxide layer, for example, a nitride layer.

이어, 도 2b에 도시하는 바와 같이, 사진 식각 공정으로 상기 제 1 폴리실리콘막(22) 위에 형성된 식각 정지막(24)을 제거하여 상기 식각 정지막(24)이 소자분리막(23)상에만 남도록 한다.2B, the etch stop layer 24 formed on the first polysilicon layer 22 is removed by a photolithography process so that the etch stop layer 24 remains only on the device isolation layer 23. do.

그리고, 상기 전체 구조물상에 플로팅 게이트용 제 2 폴리실리콘막(25)을 형성하고, 도 2c에 도시하는 바와 같이 사진 식각 공정으로 상기 소자분리막(23) 상부의 제 2 폴리실리콘막(25)을 제거한다. A second polysilicon film 25 for floating gate is formed on the entire structure, and the second polysilicon film 25 on the device isolation layer 23 is formed by a photolithography process as shown in FIG. 2C. Remove

상기 소자분리막(23) 위의 식각 정지막(24)에 의해서 상기 식각 공정이 멈춰지게 되므로 소자분리막(23)이 어택(attack)되지 않는다. 따라서, 상기 반도체 기판(20)과 이후에 형성되는 컨트롤 게이트간 누설 전류를 방지할 수 있다.Since the etching process is stopped by the etch stop layer 24 on the device isolation layer 23, the device isolation layer 23 is not attacked. Therefore, leakage current between the semiconductor substrate 20 and the control gate formed thereafter can be prevented.

이후, 도 2d에 도시하는 바와 같이 상기 제 2 폴리실리콘막(25)상에 ONO막(26)과 컨트롤 게이트(27)를 형성한다.Thereafter, as shown in FIG. 2D, an ONO film 26 and a control gate 27 are formed on the second polysilicon film 25.

본 발명에서는 소자분리막(23)상에 식각 정지막(24)을 형성하여 이후 플로팅 게이트용 제 2 폴리실리콘막(25) 식각 공정시 소자분리막(23)이 어택되는 현상을 방지할 수 있으므로 반도체 기판(20)과 컨트롤 게이트(27)간 거리를 일정하게 유지시킬 수 있다.In the present invention, since the etch stop layer 24 is formed on the device isolation layer 23, the phenomenon in which the device isolation layer 23 is attacked during the subsequent etching process of the second polysilicon layer 25 for the floating gate may be prevented. The distance between the 20 and the control gate 27 can be kept constant.

따라서, 누설 전류가 발생되지 않는 범위에서 EFH를 최대한 낮추는 것이 가능하므로 기생 커패시턴스를 줄일 수 있다. 그러므로, 누설 전류를 방지함과 동시에 간섭 현상을 최소화시킬 수 있다.Therefore, the parasitic capacitance can be reduced because the EFH can be lowered as much as possible in the range where no leakage current is generated. Therefore, the interference phenomenon can be minimized while preventing leakage current.

상술한 바와 같이, 본 발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.

첫째, 플로팅 게이트용 제 2 폴리실리콘막 식각 공정시 소자분리막의 어택을 방지할 수 있다. First, an attack of the device isolation layer may be prevented during the second polysilicon layer etching process for the floating gate.

둘째, 컨트롤 게이트와 반도체 기판간 거리를 일정하게 유지시킬 수 있으므로 누설 전류를 방지할 수 있다.Second, since the distance between the control gate and the semiconductor substrate can be kept constant, leakage current can be prevented.

셋째, 누설 전류가 발생되지 않는 범위에서 EFH를 최대한 낮출 수 있으므로 기생 커패시턴스를 줄일 수 있다. 따라서, 셀간 간섭 효과를 감소시킬 수 있다.Third, parasitic capacitance can be reduced because the EFH can be lowered as much as possible in the range where no leakage current is generated. Therefore, the intercell interference effect can be reduced.

Claims (3)

터널 산화막과 플로팅 게이트용 제 1 폴리실리콘막이 형성된 반도체 기판에 트렌치를 형성하고 상기 트렌치내에 소자분리막을 형성하는 단계;Forming a trench in the semiconductor substrate on which the tunnel oxide film and the first polysilicon film for the floating gate are formed, and forming a device isolation film in the trench; 상기 소자분리막상에 식각 정지막을 형성하는 단계;Forming an etch stop layer on the device isolation layer; 상기 전체 구조물상에 플로팅 게이트용 제 2 폴리실리콘막을 형성하는 단계; 및Forming a second polysilicon film for the floating gate on the entire structure; And 사진 식각 공정으로 상기 소자분리막 상부의 제 2 폴리실리콘막을 제거하여 상기 제 1 폴리실리콘막과 제 2 폴리실리콘막으로 구성되는 플로팅 게이트를 형성하는 단계를 포함하는 플래쉬 메모리 소자의 제조방법.Removing the second polysilicon layer on the device isolation layer by a photolithography process to form a floating gate including the first polysilicon layer and the second polysilicon layer. 제 1항에 있어서,The method of claim 1, 상기 소자분리막 상부의 제 2 폴리실리콘막을 제거한 이후에 ONO막과 컨트롤 게이트를 형성하는 단계를 더 포함하는 플래쉬 메모리 소자의 제조방법.And removing the second polysilicon layer on the device isolation layer to form an ONO layer and a control gate. 제 1항에 있어서,The method of claim 1, 상기 식각 정지막은 질화막을 이용하여 형성하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.The etch stop layer is formed using a nitride film.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100880322B1 (en) * 2006-09-29 2009-01-28 주식회사 하이닉스반도체 Flash memory device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100880322B1 (en) * 2006-09-29 2009-01-28 주식회사 하이닉스반도체 Flash memory device and its manufacturing method

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