CN109524407B - Memory and manufacturing method thereof - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
Abstract
The invention discloses a memory and a manufacturing method thereof, wherein the manufacturing method of the memory comprises the following steps: providing a substrate, wherein the substrate comprises a peripheral area and a device area, a grid electrode lamination is formed on the device area, a first control grid film is formed on the peripheral area and the device area, and the first control grid film covers the grid electrode lamination; forming an etching stop layer on the first control gate film; removing the etching stop layer on the device region; forming a second control gate film on the peripheral region and the device region; etching the gate stack, the first control gate film and the second control gate film on the device region to form a floating gate, an inter-gate dielectric layer and a control gate which are sequentially stacked on the device region; removing the second control gate film and the etching stop layer on the peripheral region; and etching the first control gate film to form a selection gate on the peripheral region, wherein the height of the selection gate is smaller than that of the control gate. The invention can improve the grid control capability of the selection grid and ensure the storage capability and the reliability of the device.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a memory and a manufacturing method thereof.
Background
With the increasing performance requirements of electronic devices, MTP (Multi-Time Programmable) memories are increasingly widely used as memory devices of various electronic devices. The MTP memory can perform the actions of storing, reading, erasing and the like of data for many times, can store the data without continuously applying electric energy, can not disappear after power failure, and can erase the data by applying certain voltage.
The substrate of an MTP memory is generally divided into an edge (peripheral) region and a device (cell) region. A gate stack including a tunnel Oxide (OX), a floating gate for storing charges, an Oxide-Nitride-Oxide (ONO) inter-gate dielectric layer, and a control gate for controlling data access is formed on the device region (also referred to as a cell region). A logic transistor is formed in the edge region (also referred to as a peripheral region), and a gate of the logic transistor is a selection gate which is used for logically controlling the opening and closing of a switching device (such as a MOS transistor) in the device region. Generally, before forming the selection gate in the edge region, a gate oxide layer is formed on the surface of the region substrate, and then the selection gate is formed on the gate oxide layer, wherein the gate oxide layer is made of silicon dioxide material. The performance of a MOS transistor depends on the thickness of the gate oxide layer. The reduction of the thickness of the gate oxide layer enhances the current driving capability of the transistor and improves the speed and power characteristics. Therefore, reducing the gate oxide thickness during process scaling can effectively improve transistor performance, while the thin oxide layer can exacerbate the tunneling effect and reduce the reliability of the oxide layer.
Researches find that the height of the selection gate on the edge region directly influences the gate control capability of the selection gate, and under the condition that the thickness of the gate oxide layer is not changed, the higher the height of the selection gate is, the higher the leakage current of the logic transistor is, the harder the device is to be started, and the response efficiency of the device is influenced. In order to solve this problem, it is a common practice to directly reduce the deposition amount of the polysilicon layer on the substrate for forming the select gate to reduce the height of the select gate, thereby improving the gate control capability of the select gate on the edge region. Although the process is simple, the height of the control gate of the device region is correspondingly reduced, when ions are implanted into the device region, the ions easily penetrate through the control gate with too low height to damage the ONO inter-gate dielectric layer and the tunneling oxide layer, and the storage capacity and the reliability of the device region are reduced.
Disclosure of Invention
The invention aims to provide a memory and a manufacturing method thereof so as to improve the gating capacity of a device.
In order to achieve the above purpose, the invention is realized by the following technical scheme:
a method of manufacturing a memory, comprising: providing a substrate, wherein the substrate comprises a peripheral region and a device region, a gate stack is formed on the device region, the gate stack comprises a floating gate film and an inter-gate dielectric film which are sequentially stacked on the device region, a first control gate film is formed on the peripheral region and the device region, and the first control gate film covers the gate stack; forming an etching stop layer on the first control gate film; removing the etching stop layer on the device region; forming a second control gate film on the peripheral region and the device region; etching the grid laminated layer, the first control grid film and the second control grid film on the device region to form a floating grid, an inter-grid dielectric layer and a control grid which are sequentially stacked on the device region; removing the second control gate film and the etching stop layer on the peripheral region; and etching the first control gate film on the peripheral region to form a selection gate on the peripheral region, wherein the height of the selection gate is less than that of the control gate.
Optionally, the gate stack further comprises a tunnel oxide film between the surface of the device region and the floating gate film.
Optionally, the material of the first control gate film and the material of the second control gate film are the same.
Optionally, the material of the first control gate film and the material of the second control gate film are both doped polysilicon.
Optionally, the material of the etch stop layer is silicon dioxide.
Optionally, the step of removing the etch stop layer on the device region includes: forming a first mask layer on the etching stop layer on the peripheral area; etching and removing the etching stop layer on the device region by taking the first mask layer as a mask; and removing the first mask layer.
Optionally, the step of forming the floating gate, the intergate dielectric layer and the control gate comprises: forming a second mask layer on the second control gate film on the device region and the peripheral region; etching the gate stack, the first control gate film and the second control gate film on the device region by taking the second mask layer as a mask to form a floating gate, an inter-gate dielectric layer and a control gate; and removing the second mask layer.
Optionally, the step of removing the second control gate film and the etch stop layer on the peripheral region includes: forming a third mask layer on the device region; etching and removing the second control gate film and the etching stop layer on the peripheral region by taking the third mask layer as a mask; and removing the third mask layer.
Optionally, the step of forming a select gate on the peripheral region includes: forming a fourth mask layer on the device region and the peripheral region; etching the first control gate film on the peripheral region by taking the fourth mask layer as a mask so as to form a selection gate on the peripheral region; and removing the fourth mask layer.
In another aspect, a memory formed using the method as described above, the memory comprising: the memory device comprises a substrate, a plurality of memory cell areas and a plurality of control circuits, wherein each memory cell area comprises a peripheral area and a device area; a floating gate on the device region; an inter-gate dielectric layer on the floating gate; a control gate on the inter-gate dielectric layer; a select gate on the peripheral region; wherein the height of the selection gate is smaller than that of the control gate.
The method comprises the steps of depositing a first control gate film and a second control gate film step by step, namely forming an etching stop layer on the first control gate film; removing the etching stop layer on the device region; forming a second control gate film on the peripheral region and the device region; etching the grid laminated layer, the first control grid film and the second control grid film on the device region to form a floating grid, an inter-grid dielectric layer and a control grid which are sequentially stacked on the device region; removing the second control gate film and the etching stop layer on the peripheral region; and etching the first control gate film on the peripheral region to form a selection gate on the peripheral region, wherein the height of the finally formed selection gate is smaller than that of the control gate, so that the purpose of reducing the height of the selection gate in the peripheral region is achieved under the condition that the height of the control gate in the device region is unchanged.
Through the process steps, the height of the selection gate in the peripheral area is reduced, the depletion of polycrystalline silicon of the selection gate is reduced, the gate control capability of the selection gate in the peripheral area is further improved, and the response rate of the device is increased. Furthermore, because the height of the selection gate is smaller than that of the control gate, when ions are injected into the device region, the ions cannot penetrate through the control gate, the ONO and the tunneling oxide layer are protected from being damaged by the ions, and the storage capacity and the reliability of the device region are improved.
Drawings
FIG. 1 is a flow chart illustrating a method for fabricating a memory device according to an embodiment of the invention;
fig. 2a to 2h are schematic cross-sectional views corresponding to steps in a manufacturing process of a memory according to an embodiment of the invention.
Detailed Description
A memory and method of manufacturing the same according to the present invention will now be described in detail with reference to the accompanying drawings, in which a preferred embodiment of the invention is shown, it being understood that those skilled in the art may modify the invention herein described while still achieving the advantageous results of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
It is to be noted that the drawings are in a very simplified form and employ non-precise ratios for the purpose of facilitating and distinctly facilitating the description of one embodiment of the present invention.
As shown in fig. 1, the present embodiment provides a method for manufacturing a memory, the method including the steps of:
step S1, providing a substrate, wherein the substrate comprises a peripheral region and a device region, a grid stack is formed on the device region, the grid stack comprises a floating grid film and an inter-grid dielectric film which are sequentially stacked on the device region, a first control grid film is formed on the peripheral region and the device region, and the first control grid film covers the grid stack.
And step S2, forming an etching stop layer on the first control gate film.
And step S3, removing the etching stop layer on the device area.
Step S4, forming a second control gate film on the peripheral region and the device region.
And step S5, etching the gate stack, the first control gate film and the second control gate film on the device region to form a floating gate, an inter-gate dielectric layer and a control gate which are sequentially stacked on the device region.
And step S6, removing the second control gate film and the etching stop layer on the peripheral region. In this embodiment, the second control gate film in the peripheral region may be removed by a dry etching process. The etch stop layer located in the peripheral region may be removed by a wet etch process.
And step S7, etching the first control gate film on the peripheral region to form a selection gate on the peripheral region, wherein the height of the selection gate is less than that of the control gate.
In this embodiment, the first control gate film and the second control gate film are deposited step by the above-mentioned manufacturing method of the memory, so as to achieve the purpose of reducing the height of the select gate in the peripheral region under the condition that the height of the control gate in the device region is not changed, and further achieve the purpose of improving the gate control capability of the select gate in the peripheral region.
Referring to fig. 2a to 2h, schematic cross-sectional structures corresponding to steps in a method for manufacturing a memory according to an embodiment of the invention are shown.
As shown in fig. 2a, a substrate is provided, which may be made of silicon, germanium, silicon carbide, or the like, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials, such as iii and v compounds such as gallium arsenide, or the like. In other embodiments, the substrate may include various doped regions depending on the design requirements of the memory. Isolation structures (e.g., shallow trench isolation, STI) may be included in the substrate to isolate regions and/or semiconductor devices formed on the substrate. The substrate in this embodiment is a silicon substrate, and further, it may be an undoped or lightly P-type doped silicon substrate.
The substrate includes a peripheral region (also referred to as an edge region) 10 and a device region (also referred to as a cell region) 20. A gate stack 30 is formed over the device region 20. The gate stack 30 includes, for example, a tunnel oxide film 31, a floating gate film 32, and an inter-gate dielectric film 33 sequentially stacked on the device region 20 from bottom to top, and the tunnel oxide film 31, the floating gate film 32, and the inter-gate dielectric film 33 can be modified and added according to actual device requirements and manufacturing processes.
The tunneling oxide film 31 is used to form a tunneling oxide layer, and may adopt a silicon oxide single layer structure or a silicon oxide-silicon nitride-silicon oxide (ONO) structure. The formation method of the tunnel oxide film 31 includes suitable processes such as Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), thermal oxidation, and the like. In the present embodiment, the tunnel oxide film 31 has a single-layer structure of silicon oxide, which can be formed by a thermal oxidation method and has a thickness of, for example, about several tens of angstroms.
The inter-gate dielectric film 33 is used to form a gate dielectric layer for isolating the floating gate from the control gate. The inter-gate dielectric film 33 may employ a silicon oxide-silicon nitride-silicon oxide (ONO) structure. The inter-gate dielectric film 33 may be formed by a suitable process such as Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), thermal oxidation, or the like. In this embodiment, a silicon oxide layer may be formed on the floating gate film 32 by a low pressure chemical vapor deposition process, a silicon nitride layer may be formed on the silicon oxide layer by a low pressure chemical vapor deposition process, and then another silicon oxide layer may be formed on the silicon nitride layer by a low pressure chemical vapor deposition process, wherein the total thickness of the inter-gate dielectric film 33 is, for example, several tens of angstroms to several hundreds of angstroms.
A first control gate film 40 is formed on the peripheral region 10 and the device region 20, and the first control gate film 40 covers the peripheral region 10 and the device region 20A gate stack 30. The first control gate film 40 is formed by a suitable process such as Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like. The first control gate film 40 is typically formed using a low pressure chemical vapor deposition process. Since the gate stack 30 is already formed on the device region 20, after this step, the top surface of the first control gate film 40 on the device region 20 is higher than the top surface of the first control gate film 40 on the peripheral region 10, so that a step is formed at the boundary between the device region 20 and the peripheral region 10. In this embodiment, the thickness of the first control gate film is in the range of
Next, as shown in fig. 2b, an etching stop layer 50 is formed on the surface of the first control gate film 40, that is, the etching stop layer 50 covers the first control gate film 40 on the peripheral region 10 and the first control gate film 40 on the device region 20. The method for forming the etch stop layer 50 includes a suitable process such as Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like. In the present embodiment, the material for forming the etch stop layer 50 is preferably silicon dioxide.
Then, a first mask layer (not shown) is formed on the etching stop layer 50 located on the peripheral region 10, wherein the first mask layer is, for example, a patterned photoresist layer, and a spin coating method may be used to coat a photoresist on the etching stop layer 50 and pattern the photoresist by using processes known to those skilled in the art, such as exposure and development, to obtain the patterned photoresist layer. Then, the first mask layer is used as a mask to etch and remove the etch stop layer 50 in the device region 20, and the first mask layer can protect the etch stop layer 50 in the peripheral region 10 from being etched, so that the etch stop layer 50 in the peripheral region 10 is retained (as shown in fig. 2 c). The first mask layer may then be removed by plasma ashing or the like.
As shown in the figure2d, forming a second control gate film 41, wherein the second control gate film 41 covers the etching stop layer 50 on the peripheral region 10 and covers the first control gate film 40 on the device region 20. The second control gate film 41 is formed by a suitable process such as Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like. The second control gate film 41 is typically formed using a low pressure chemical vapor deposition process. In this embodiment, the thickness range of the second control gate film 41 is, for example
Next, a second mask layer (not shown) is formed on the second control gate film 41, and the second mask layer is, for example, a patterned photoresist layer, and the photoresist layer is formed by coating a photoresist on the etching stop layer 50 by using a spin coating method and patterning the photoresist by using a process known to those skilled in the art, such as exposure and development. Next, with the second mask layer as a mask, the second control gate film 41, the first control gate film 40 and the gate stack 30 on the device region 20 are etched, and a floating gate 32 'and a control gate 34' located above the floating gate are formed on the device region 20, as shown in fig. 2 e. The second mask layer may then be removed by plasma ashing or the like. Specifically, the second control gate film 41, the first control gate film 40, and the gate stack 30 on the device region 20 may be sequentially etched by using a dry etching process to form a gate structure on the device region 20, where the gate structure includes a tunnel oxide layer 31 '(obtained by etching the tunnel oxide film 31), a floating gate 32' (obtained by etching the floating gate film 32), an inter-gate dielectric layer 33 '(obtained by etching the gate stack 30), and a control gate 34' (obtained by etching the second control gate film 41 and the first control gate film 40) that are sequentially stacked on the device region 20.
Next, a third mask layer (not shown in the figure) is formed on the device region 20, and the third mask layer is, for example, a patterned photoresist layer, and the photoresist layer is obtained by coating a photoresist on the device region 20 and the peripheral region 10 by using a spin coating method and patterning the photoresist by using processes such as exposure and development, which are well known to those skilled in the art. And then, as shown by combining 2f to 2g, removing the second control gate film 41 and the etching stop layer 50 on the peripheral region 10 by using the third mask layer as a mask through an etching process. As a non-limiting example, the second control gate film 41 may be removed using a plasma dry etching process, and then the etch stop layer 50 may be removed using a wet etching process. Subsequently, the third mask layer may be removed by plasma ashing or the like.
Then, a fourth mask layer (not shown in the figure) is formed on the peripheral region 10 and the device region 20, and the fourth mask layer is, for example, a patterned photoresist layer, and the fourth mask layer is obtained by coating a photoresist on the device region 20 and the peripheral region 10 by using a spin coating method and patterning the photoresist by using processes such as exposure and development, which are well known to those skilled in the art. Next, using the fourth mask layer as a mask, the first control gate film 40 on the peripheral region 10 is etched, so as to form a select gate 40' on the peripheral region 10, as shown in fig. 2 h. Finally, the third mask layer and the fourth mask layer can be removed by plasma ashing and the like. The resulting select gate 40 'has a height less than the height of the control gate 34'. And the material of the first control gate film is the same as that of the second control gate film. In this embodiment, the first control gate film 40 and the second control gate film 41 are both made of doped polysilicon.
According to another aspect of the present invention, there is also provided a memory structure, which can be formed using the above method. As shown in fig. 2a to 2h, the memory structure includes: a substrate including a device region 20 and a peripheral region 10; a tunneling oxide layer 31 ', a floating gate 32', an inter-gate dielectric layer 33 'and a control gate 34' which are located on the device region 20 and stacked in sequence; and the selection gate 40 ' is positioned on the peripheral region 10, and the height of the selection gate 40 ' is smaller than that of the control gate 34 '. The height range of the select gate 40' is, for exampleIs composed of
The control gate 34' has a height in the range of, for example
Further, the memory structure further includes a source/drain (not shown) located in the substrate at two sides of the floating gate 32'. After the formation of the source and drain, the source and drain are formed by sequentially stacking the tunnel oxide layer 31 ', the floating gate 32 ', the inter-gate dielectric layer 33 ' and the control gate 34 ' of the select gate 40 ' and the device region in the peripheral region 10, and performing a source and drain ion implantation process on the device region 20.
The memory is, for example, a floating gate type memory, such as a flash memory (flash), an electrically erasable programmable read-only memory (EEPROM), or the like.
In summary, the invention optimizes the process sequence and combines a certain etching process to manufacture the select gate and the control gate from the viewpoint of process integration. The depletion of polycrystalline silicon is reduced by reducing the height of the selection gate of the peripheral region on the premise of ensuring that the height of the control gate in the device region is unchanged, and the gate control capability of the selection gate of the peripheral region is improved. Furthermore, because the height of the selection gate is smaller than that of the control gate, when source and drain ions are injected into the device region, the ions cannot penetrate through the control gate, and the ONO and the tunneling oxide layer are protected from being damaged by the ions.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the description is not to be construed as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (9)
1. A method of manufacturing a memory, comprising:
providing a substrate, wherein the substrate comprises a peripheral region and a device region, a gate stack is formed on the device region, the gate stack comprises a floating gate film and an inter-gate dielectric film which are sequentially stacked on the device region, a first control gate film is formed on the peripheral region and the device region, and the first control gate film covers the gate stack;
forming an etching stop layer on the first control gate film;
removing the etching stop layer on the device region;
forming a second control gate film on the peripheral region and the device region;
etching the grid laminated layer, the first control grid film and the second control grid film on the device region to form a floating grid, an inter-grid dielectric layer and a control grid which are sequentially stacked on the device region;
removing the second control gate film and the etching stop layer on the peripheral region; and the number of the first and second groups,
and etching the first control gate film on the peripheral region to form a selection gate on the peripheral region, wherein the thickness of the selection gate is smaller than that of the control gate.
2. The method of manufacturing a memory of claim 1, wherein the gate stack further comprises a tunnel oxide film between the surface of the device region and the floating gate film.
3. The method of manufacturing a memory according to claim 1, wherein a material of the first control gate film and a material of the second control gate film are the same.
4. The method of manufacturing a memory according to claim 3, wherein the material of the first control gate film and the material of the second control gate film are both doped polysilicon.
5. The method of manufacturing a memory according to claim 1, wherein the material of the etch stop layer is silicon dioxide.
6. The method of manufacturing the memory of any one of claims 1 to 5, wherein the step of removing the etch stop layer on the device region comprises:
forming a first mask layer on the etching stop layer on the peripheral area;
etching and removing the etching stop layer on the device region by taking the first mask layer as a mask; and removing the first mask layer.
7. The method of manufacturing a memory as claimed in any one of claims 1 to 5, wherein the step of forming the floating gate, the intergate dielectric layer and the control gate comprises:
forming a second mask layer on the second control gate film on the device region and the peripheral region;
etching the gate stack, the first control gate film and the second control gate film on the device region by taking the second mask layer as a mask to form a floating gate, an inter-gate dielectric layer and a control gate; and
and removing the second mask layer.
8. The method for manufacturing a memory according to any one of claims 1 to 5, wherein the step of removing the second control gate film and the etch stop layer located on the peripheral region includes:
forming a third mask layer on the device region;
etching and removing the second control gate film and the etching stop layer on the peripheral region by taking the third mask layer as a mask; and
and removing the third mask layer.
9. The method of any of claims 1 to 5, wherein forming a select gate over the peripheral region comprises:
forming a fourth mask layer on the device region and the peripheral region;
etching the first control gate film on the peripheral region by taking the fourth mask layer as a mask so as to form a selection gate on the peripheral region; and
and removing the fourth mask layer.
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| CN105097954B (en) * | 2014-05-23 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method and electronic device of semiconductor devices |
| CN105575784B (en) * | 2014-10-09 | 2018-09-18 | 中芯国际集成电路制造(上海)有限公司 | The production method and separate grid type flash memory of separate grid type flash memory |
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