JP2009170719A - Nonvolatile semiconductor memory device and method of fabricating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a leak current flowing through a second gate insulating film provided between a charge storage layer and a control gate electrode layer. <P>SOLUTION: An intergate insulating film 7 has a multilayer structure of a silicon nitride film 7aa, a high dielectric insulating film 7ab, a silicon oxide film 7ac, a high dielectric insulating film 7b, a silicon oxide film 7ca, and a silicon nitride film 7cb between a floating gate electrode FG and a control gate electrode CG from the side of the floating gate electrode FG to the side of the control gate electrode CG, so that the leak current can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device including a memory cell in which a charge storage layer and a control gate electrode layer are formed with an insulating film interposed therebetween, and a manufacturing method thereof.

  In the nonvolatile semiconductor memory device, a large number of memory cells are arranged in the word line direction and the bit line direction, thereby achieving high integration. With the trend toward higher integration in recent years, the width and length dimensions of memory cells and the spacing between adjacent memory cells have been reduced, increasing adjacent cell interference. When interference between adjacent cells increases, problems such as device malfunctions and a decrease in write / erase operation speed occur.

  In order to reduce the interference effect of adjacent cells, it is necessary to reduce the parasitic capacitance between adjacent cells, to reduce the facing area between adjacent cells, and to reduce the height of the charge storage layer. When the height of the charge storage layer is lowered, the value of the coupling ratio, which is an index of memory cell characteristics, is also lowered. For this reason, it is necessary to reduce the electrical film thickness of the inter-gate insulating film (corresponding to the second gate insulating film) while adjusting the charge storage layer to a low and appropriate height. If the electrical film thickness of the inter-gate insulating film is reduced, the capacitance value between the charge storage layer and the control gate electrode layer can be increased, and the coupling ratio can be ensured to a desired value (for example, Patent Document 1). reference).

However, since the electric field applied to the inter-gate insulating film increases as the inter-gate insulating film becomes thinner, the leakage current of the inter-gate insulating film is increased when a high electric field is applied during writing or / and erasing. The leakage current of the tunnel insulating film (corresponding to the first gate insulating film) increases to almost the same level, and there is a possibility that a high desired threshold voltage required for writing or / and erasing cannot be applied. .
JP 2003-289114 A

  The present invention provides a nonvolatile semiconductor memory device and a method for manufacturing the same, which can suppress a leakage current flowing through a second gate insulating film provided between a charge storage layer and a control gate electrode layer.

  According to one embodiment of the present invention, a semiconductor substrate, a first gate insulating film formed over the semiconductor substrate, a charge storage layer formed over the first gate insulating film, and the charge storage layer A second gate insulating film formed; and a control gate electrode layer formed on the second gate insulating film, wherein the second gate insulating film includes the charge storage layer and the control gate electrode layer. Between the charge storage layer and the control gate electrode layer, a silicon oxide film, a first high dielectric insulating film having a relative dielectric constant higher than that of the silicon nitride film, and silicon A structure having a layer structure with a second high dielectric insulating film having a relative dielectric constant higher than that of the nitride film, and the first and second high dielectric insulating films sandwiching the silicon oxide film It is characterized by that.

  Another aspect of the present invention includes a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, and the charge storage layer A second gate insulating film formed on the second gate insulating film and a control gate electrode layer formed on the second gate insulating film, wherein the second gate insulating film includes the charge storage layer and the control gate electrode. The relative dielectric constant of the first silicon nitride film, the first silicon oxide film, and the dielectric constant higher than that of the silicon nitride film from the charge storage layer side to the control gate electrode layer side between the layers A laminated structure of a first high-dielectric insulating film, a second silicon oxide film, and a second silicon nitride film, and between the first silicon nitride film and the first silicon oxide film, or second Silicon nitride film and second silicon oxide film Of it is characterized in that at least either one relative dielectric constant with a second high-dielectric insulating film having a dielectric constant higher than the dielectric constant of the silicon nitride film.

  Another aspect of the present invention includes a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, and the charge storage layer And a control gate electrode layer formed on the second gate insulating film, wherein the second gate insulating film includes the charge storage layer and the control electrode layer. A three-layer silicon oxide film structure of first to third silicon oxide films between the charge storage layer side and the control gate electrode layer, and a relative dielectric constant of the three-layer silicon oxide film structure and silicon A first high-dielectric insulating film having a relative dielectric constant higher than that of the nitride film; and a second high-dielectric insulating film having a relative dielectric constant higher than that of the silicon nitride film. And the first high-dielectric insulating film is 3 The second high dielectric insulating film is formed on one of the two layers interposed between the silicon oxide film structures, and the second high dielectric insulating film is formed on the other of the two layers interposed between the three-layer silicon oxide film structures. It is characterized by being formed.

  Another aspect of the present invention includes a step of forming a first gate insulating film on a semiconductor substrate, a step of forming a charge storage layer on the first gate insulating film, and a first on the charge storage layer. A step of forming a silicon nitride film, a step of forming a first silicon oxide film on the first silicon nitride film, and a relative dielectric constant of the silicon nitride film on the first silicon oxide film Forming a first high dielectric insulating film having a relative dielectric constant higher than a dielectric constant; forming a second silicon oxide film on the first high dielectric insulating film; and Forming a second high dielectric insulating film having a relative dielectric constant higher than that of the silicon nitride film on the silicon oxide film; and forming a second high dielectric insulating film on the second high dielectric insulating film. Forming a second silicon nitride film, and a control gate on the second silicon nitride film. It is characterized by comprising a step of forming an electrode layer.

  According to the present invention, the leakage current flowing through the second gate insulating film provided between the charge storage layer and the control gate electrode layer can be suppressed.

  Hereinafter, an embodiment of a nonvolatile semiconductor memory device of the present invention will be described with reference to the drawings. In the following description in the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  FIG. 1 is a plan view of a memory cell region of a nonvolatile semiconductor memory device. As shown in FIG. 1, in the memory cell region M, a large number of memory cell transistors Trm are arranged in a matrix in the word line direction and the bit line direction, and peripheral circuits (not shown) are stored in the memory cell transistors Trm. The read data can be read, written and erased. Examples of the nonvolatile semiconductor memory device having such a memory cell structure include a NAND flash memory device having a cell unit structure in which a plurality of memory cell transistors are connected in series between two select gate transistors.

  2A shows a cross-sectional view (cross-sectional view along the line AA in FIG. 1) along the word line direction (channel width direction) of each memory cell, and FIG. 2B is an enlarged cross-section of a portion B in FIG. 2A. The figure is shown. FIG. 2C shows a cross-sectional view (cross-sectional view along the line CC in FIG. 1) along the bit line direction (channel length direction) of each memory cell. As shown in FIG. 2A, an N well 2a is formed on the p-type silicon substrate 2, and a P well 2b is formed on the surface layer of the N well 2a. A plurality of element isolation grooves 3 are formed in the surface layer of the P well 2 b of the silicon substrate 2. These element isolation trenches 3 isolate a plurality of active regions Sa in the word line direction of FIG. 2A.

  An element isolation insulating film 4 is formed in the element isolation trench 3 to constitute an element isolation region Sb. This element isolation insulating film 4 is composed of a lower part embedded in the element isolation trench 3 and an upper part protruding upward from the surface of the silicon substrate 2. The element isolation insulating film 4 is formed with its upper end positioned near the surface of the silicon substrate 2 (above the surface of the silicon substrate 2). The element isolation insulating film 4 may be configured such that its upper end is located below the surface of the silicon substrate 2.

  On the other hand, a gate insulating film 5 (corresponding to a first gate insulating film) is formed on each of the plurality of active regions Sa of the silicon substrate 2 partitioned by the element isolation region Sb. The gate insulating film 5 is made of, for example, a silicon oxide film. The gate insulating film 5 is configured such that an end thereof is in contact with a part of the upper side surface of the element isolation insulating film 4. A floating gate electrode FG is formed on these gate insulating films 5 as a charge storage layer.

  The floating gate electrode FG is composed of a polycrystalline silicon layer 6 (conductive layer, semiconductor layer) doped with an impurity such as phosphorus. The polycrystalline silicon layer 6 has a lower side surface serving as a contact surface in contact with the upper side surface of the element isolation insulating film 4 and an upper side surface protruding upward from the upper surface 4 a of the element isolation insulating film 4. The upper side surface of the element isolation insulating film 4 protruding upward from the surface of the silicon substrate 2 is formed flush with the side surface of the gate insulating film 5 and the lower side surface of the polycrystalline silicon layer 6. The element isolation insulating film 4 is formed of, for example, a silicon oxide film.

  The inter-gate insulating film 7 is formed along the upper surface of the element isolation insulating film 4, the upper side surface of the floating gate electrode FG, and the upper surface of the floating gate electrode FG, and includes an interpoly insulating film, a conductive interlayer insulating film, and an electrode. Functions as an inter-insulating film.

  As shown in the enlarged view of FIG. 2B, the inter-gate insulating film 7 is formed of a lower insulating film from the lower layer side (the upper surface side of the element isolation insulating film 4, the side surface side and the upper surface side of the floating gate electrode FG) to the upper layer side. 7a / high dielectric insulating film 7b / upper insulating film 7c. Lower insulating film 7a has a laminated structure of lower silicon nitride film 7aa / high dielectric insulating film 7ab / lower silicon oxide film 7ac from the lower layer side to the upper layer side. The upper insulating film 7c has a laminated structure of an upper silicon oxide film 7ca / upper silicon nitride film 7cb from the lower layer side to the upper layer side.

The high dielectric insulating film 7b is configured as an intermediate insulating film by an aluminum oxide (Al ₂ O ₃ ) film. This aluminum oxide film has a relative dielectric constant larger than that of the ONO film (relative dielectric constant: about 5). When such an oxide of a metal other than a transition metal such as aluminum (Al) is applied, re-release of trapped charges can be prevented and threshold fluctuation can be suppressed.

  Further, since the lower silicon nitride film 7aa is provided, the metal element contained in the high dielectric insulating film 7b, the oxidant at the time of forming the silicon oxide films 7ac and 7ca, and the like are used for the gate insulating film 5 and the element isolation insulating film 4. Can be effectively prevented from diffusing. Further, since the upper silicon nitride film 7cb is provided, it is possible to effectively prevent the metal element contained in the high dielectric insulating film 7b from diffusing upward.

  A conductive layer 8 is formed on the inter-gate insulating film 7 along the word line direction. The conductive layer 8 functions as a word line WL that connects the control gate electrodes CG of the individual memory cell transistors Trm. The conductive layer 8 is composed of, for example, a polycrystalline silicon layer and a silicide layer formed by siliciding any metal such as tungsten, cobalt, nickel, etc., formed immediately above the polycrystalline silicon layer. In this way, the gate electrode MG of the memory cell transistor Trm is formed on the gate insulating film 5 by a stacked gate structure of the floating gate electrode FG, the intergate insulating film 7 and the control gate electrode CG.

  As shown in FIG. 2C, the gate electrodes MG of the memory cell transistors Trm are juxtaposed in the bit line direction, and each gate electrode MG is electrically divided in the dividing region GV. Although not shown, an interlayer insulating film or the like is formed in the dividing region GV.

  Diffusion layers (source / drain regions) 2c are formed on both sides of the gate electrode MG of the memory cell transistor Trm so as to be located on the surface layer of the silicon substrate 2. The memory cell transistor Trm includes the gate insulating film 5, the gate electrode MG, and the source / drain region 2c.

  The nonvolatile semiconductor memory device 1 applies a high electric field between a word line WL and a P well 2b from a peripheral circuit (not shown) and applies an appropriate predetermined voltage to each electrical element (source / drain) to The data can be erased / written. A multi-value storage technique for storing multi-value information in one memory cell has been developed in accordance with recent demands. Multi-level storage is performed by controlling the threshold value of each memory cell transistor Trm to a plurality of distributions of, for example, 3 or 4 or more. Here, for simplicity of explanation, the case of binary storage will be described.

  At the time of writing, the peripheral circuit applies a high voltage (for example, 20 V) to the word line WL selected for writing, and applies a low voltage (for example, 0 V to an intermediate voltage of 10 V) to the P well 2b and the like. Then, since the FN tunnel current flows through the gate insulating film 5, electrons are injected into the floating gate electrode (charge storage layer) FG, and the threshold voltage of the memory cell transistor Trm shifts in the positive direction.

  At the time of erasing, the peripheral circuit applies a low voltage (for example, 0 V to 2.5 V) to the word line WL to be erased and applies a high voltage to the P well 2b. Then, electrons escape from the floating gate electrode FG to the P well 2b, so that the threshold voltage of the memory cell transistor Trm shifts in the negative direction. As a result, the data can be erased.

  In particular, when a positive high electric field is applied to the word line WL at the time of writing, a leakage current is generated due to electrons being discharged from the floating gate electrode FG to the word line WL side through the inter-gate insulating film 7. Then, the accumulated amount of electrons in the floating gate electrode FG is saturated, and the threshold voltage at the time of writing in the memory cell transistor Trm is saturated. Therefore, in this embodiment, the structure of the inter-gate insulating film 7 described above is employed.

  FIG. 3 shows the time dependence of the threshold voltage during writing. As shown in FIG. 3, the threshold voltage of each memory cell transistor Trm increases as the write time increases. The inventors have adopted a laminated structure of a silicon nitride film 7aa / silicon oxide film 7ac as the lower insulating film 7a of the inter-gate insulating film 7 without providing the high dielectric insulating film 7ab, and a silicon nitride film 7aa / silicon. Comparison is made with the case where a laminated structure in which a high dielectric insulating film 7ab is provided between the oxide films 7ac is employed.

  As shown in FIG. 3, in the case where the high dielectric insulating film 7ab is not provided, the threshold voltage is saturated even if the writing time is increased, but the case where the high dielectric insulating film 7ab is provided. Has found that increasing the writing time can suppress the saturation state of the threshold voltage and increase the saturation voltage.

  The threshold voltage is saturated because electrons are injected into the floating gate electrode FG through the gate insulating film 5 when a positive high voltage at the time of writing is applied to the control gate electrode CG. This is because electrons escape to the control gate electrode CG side through the inter-gate insulating film 7 and the tunnel current flowing through the gate insulating film 5 and the leak current flowing through the inter-gate insulating film 7 are balanced. The tunneling probability of electrons passing from the gate electrode FG to the control gate electrode CG increases, and the threshold voltage is saturated.

  When the high dielectric insulating film 7ab is provided, the saturation phenomenon of the threshold voltage cannot be confirmed even if the writing time is increased. The reason for this is presumed that by inserting the high dielectric insulating film 7ab, the electric field when a high electric field is applied is relaxed in the region of the high dielectric insulating film 7ab as the dielectric constant increases. In this case, the electron tunneling distance can be increased as compared with the conventional structure, the electron tunneling probability can be lowered, and the leakage current when a high electric field is applied can be reduced.

  FIG. 4 shows the applied electric field dependence of the leakage current flowing in the inter-gate insulating film. As shown in FIG. 4, it has been found that the leakage current value that is substantially the same in the low electric field region has a difference in the leakage current from the middle electric field region to the higher electric field region.

  This is because the physical film thickness is increased by providing the high dielectric insulating film 7ab having a high relative dielectric constant closer to the floating gate electrode FG than the intermediate insulating film 7b, and the distance through which electrons directly tunnel is increased. is there. It has been confirmed that this effect appears more prominently when the high dielectric insulating film 7ab is made of a material having a higher relative dielectric constant and a higher barrier height.

  FIG. 5 shows the film thickness dependence of the leakage current value when an electric field of 10 [MV / cm] is applied to the inter-gate insulating film. As shown in FIG. 5, the leak current value is set when the thickness of the high dielectric insulating film 7ab is set to a thickness exceeding 0 [nm] and not exceeding 3 [nm]. Leakage current is reduced. On the other hand, when the high dielectric insulating film 7ab is set to a film thickness of 5 [nm], the leakage current rises conversely. Therefore, from the data shown in FIG. 5, in order to reduce the leakage current, it is preferable to form the high dielectric insulating film 7ab with a predetermined film thickness of several nm of 3 [nm] or less.

Thus, it is estimated that the reason why the leakage current value obtains the lower limit value depending on the film thickness of the high dielectric insulating film 7ab is as follows. FIG. 6 schematically shows a band structure near the forbidden band and the conductive band when a high electric field is applied. An inter-gate insulating film 7 is formed from the floating gate electrode FG to the control gate electrode CG side, such as SiN (silicon nitride film 7aa), Al ₂ O ₃ film (high dielectric insulating film 7ab), SiO ₂ (silicon oxide film 7ac), When formed in this order, the height of the barrier height is higher in the silicon oxide film than in the aluminum oxide (Al ₂ O ₃ ) film, and as shown in FIG. When the film 7ab is set to an appropriate film thickness (for example, 3 to 4 nm), the silicon oxide film 7ac formed on the high dielectric insulating film 7ab also functions as a tunnel insulating film. Therefore, the inter-gate insulating film 7 can obtain a characteristic of a predetermined tunnel film thickness D1.

  However, as shown in FIG. 6B, when the high dielectric insulating film 7ab is formed with a film thickness exceeding a predetermined film thickness (for example, 3 to 4 [nm]), the upper layer of the high dielectric insulating film 7ab is formed. The silicon oxide film 7ac does not function as a tunnel insulating film. Then, the tunnel film thickness D2 becomes thinner than the above-described tunnel film thickness. Therefore, it is estimated that the high dielectric insulating film 7ab obtains a predetermined lower limit value in consideration of leakage current characteristics.

  In addition to the aluminum oxide film, an oxide film made of another metal such as yttrium or hafnium can be used as the high dielectric insulating film 7ab, but the electric field applied to the inter-gate insulating film 7 is 10 [MV / When the aluminum oxide film is applied, the optimum film thickness is about 3 nm, and when the yttrium oxide film is applied, the film thickness is about 4 nm. It has been confirmed that when the film is applied, the film thickness is about 8 [nm].

The manufacturing method of the said structure is demonstrated.
As shown in FIG. 7, an N well 2a and a P well 2b are formed in this order on the surface layer of a p-type single crystal silicon substrate 2, and a gate insulating film 5 (insulating film) is formed on the silicon substrate 2 at 1 to 15 nm. ] With a predetermined film thickness in the range. Next, as shown in FIG. 8, amorphous silicon is deposited on the gate insulating film 5 with a predetermined film thickness in the range of 10 to 200 [nm] by chemical vapor deposition. This amorphous silicon is polycrystallized by a subsequent heat treatment to be transformed into polycrystal silicon and configured as a conductive layer 6 (floating gate electrode FG). Next, as shown in FIG. 9, a silicon nitride film 9 is deposited with a predetermined film thickness in the range of 50 to 200 [nm] by chemical vapor deposition, and then a silicon oxide film 10 is deposited by chemical vapor deposition. A hard mask is deposited with a predetermined film thickness in the range of 50 to 400 [nm].

  Next, as shown in FIG. 10, after applying a photoresist 11, patterning is performed by a lithography technique, and the silicon oxide film 10 is anisotropically etched by RIE (Reactive Ion Etching) using the resist 11 as a mask. . Next, the resist 11 is removed by ashing or the like. Next, using the silicon oxide film 10 as a mask, the silicon nitride film 9 is anisotropically etched by the RIE method, and the conductive layer 6, the gate insulating film 5 and the upper portion of the silicon substrate 2 are anisotropically etched by the RIE method. Thereby, the element isolation trench 3 is formed in the surface layer of the silicon substrate 2.

  Next, as shown in FIG. 11, a silicon oxide film 4 as an insulating film is formed in the element isolation trench 3 by using an application technique or / and an insulating film forming technique such as HDP-CVD (High Density Plasma Chemical Vapor Deposition). Is embedded with a predetermined film thickness in the range of 200 to 1500 [nm]. At this time, the silicon oxide film 4 is formed so that the upper surface thereof is located above the upper surface of the silicon oxide film 10. At this time, when the polysilazane solvent is formed by coating by a coating technique, the polysilazane solvent is heat treated in an oxygen atmosphere or a water vapor atmosphere to increase the density, thereby baking the coating type insulating film into silicon. An element isolation insulating film 4 is formed by converting to an oxide film.

  Next, as shown in FIG. 12, the upper surface of the silicon oxide film 4 is planarized by the chemical mechanical polishing (CMP) method using the silicon nitride film 9 as a stopper.

  Next, as shown in FIG. 13, the upper surface of the silicon oxide film 4 is gated by processing with a hydrofluoric acid (HF) solution diluted with water under a condition having high selectivity with the silicon nitride film 9. Etching back is performed to a predetermined depth above the upper surface of the insulating film 5 and below the upper surface of the conductive layer 6. Next, as shown in FIG. 14, the silicon nitride film 9 is removed by etching with a chemical solution or the like to expose the upper surface of the polycrystalline silicon layer 6.

  Next, as shown in FIG. 15, a silicon nitride film 7aa is formed with a predetermined film thickness in the range of 1 to 5 [nm] under a temperature condition of about 800 ° C. by low pressure chemical vapor deposition (LP-CVD). . The silicon nitride film 7aa is formed on the upper surface of the silicon oxide film 4, the upper side surface of the polycrystalline silicon layer 6, and the region along the upper surface. The silicon nitride film 7aa may be formed by plasma nitriding (radical nitriding).

Next, as shown in FIG. 16, the high dielectric insulating film 7ab is formed with a film thickness (for example, 3 nm) equal to or less than the predetermined film thickness by an atomic layer growth method (ALD method). Next, as shown in FIG. 17, dichlorosilane and nitrous oxide (N ₂ O) are reacted at a temperature of, for example, about 800 ° C. by a low pressure chemical vapor deposition method (LP-CVD method) and a high dielectric constant is obtained by a CVD method. A silicon oxide film 7ac is deposited on the body insulating film 7ab with a predetermined film thickness in the range of 1 to 10 [nm], for example.

  Next, as shown in FIG. 18, a high dielectric insulating film 7b is formed on the silicon oxide film 7ac with a predetermined film thickness in the range of 1 to 20 nm by an ALD (Atomic Layer Deposition) method. In addition to the ALD method, it may be formed by a method such as a CVD method or a sputtering method. This aluminum oxide film 7b has a dielectric constant characteristic higher than about 7 which is a dielectric constant of the silicon nitride film.

Next, as shown in FIG. 19, by reacting dichlorosilane and nitrous oxide (N ₂ O) at a temperature of about 800 ° C. by low pressure chemical vapor deposition, a silicon oxide film is formed on the high dielectric insulating film 7b. 7ca is deposited with a predetermined film thickness in the range of 1 to 10 nm by the CVD method.

  Next, as shown in FIGS. 2A and 2B, a silicon nitride film 7cb is deposited with a predetermined film thickness in the range of 1 to 5 nm under a temperature condition of 800 ° C. by a low pressure chemical vapor deposition method. Conductive layer 8 is formed. The silicon nitride film 7cb may be formed by plasma nitriding (radical nitriding) treatment.

  Next, a mask pattern (not shown) is formed on the conductive layer 8, and the conductive layer 8, the intergate insulating film 7, and the polycrystalline silicon layer 6 among the stacked films 5 to 8 are anisotropically formed by the RIE method or the like. Etching is performed along the direction parallel to the placement surface of FIG. 2A using an etching technique, and the substrate is divided in a direction perpendicular to the placement surface of FIG. 2A. Then, as shown in FIG. 2C, the dividing region GV is formed so as to divide the gate electrode MG.

  Next, as shown in FIG. 2C, an impurity for forming the source / drain region 2c is ion-implanted into the surface layer of the silicon substrate 2 through the dividing region GV. Thereafter, an interlayer insulating film (not shown) is deposited in the dividing region GV, contacts for various wirings are formed in the interlayer insulating film, and the process proceeds to an upper layer wiring forming process. Are not directly related, and detailed description thereof is omitted. The conductive layer 8 is composed of a silicon layer and a metal silicide formed on the silicon layer. Although the silicon layer is deposited before the formation of the dividing region GV, the upper silicidation process using a metal is applied to the conductive layer 8. Depending on the material or the like, the gate electrode MG may be performed at any timing before or after the gate electrode MG is divided at the dividing region GV.

According to the present embodiment, the inter-gate insulating film 7 is formed between the floating gate electrode FG and the control gate electrode CG from the floating gate electrode FG side to the control gate electrode CG side. Since it has a laminated structure of film 7ab / silicon oxide film 7ac / high dielectric insulating film 7b / silicon oxide film 7ca / silicon nitride film 7cb, leakage current can be suppressed.
Since the high dielectric insulating film 7ab is formed of an oxide film of a non-transition metal element (Al), it is possible to prevent re-release of charges trapped in the high dielectric insulating film 7b and to suppress threshold fluctuation. it can.

Since the high dielectric insulating film 7ab is formed between the silicon nitride film 7aa and the silicon oxide film 7ac, it is possible to suppress a leakage current particularly during writing.
(Second Embodiment)
FIG. 20 shows a second embodiment of the present invention, which is different from the previous embodiment in the laminated structure of the intergate insulating film. The same parts as those of the above-described embodiment are denoted by the same reference numerals and description thereof is omitted, and only different parts will be described below.

  As described in the above embodiment, at the time of erasing each memory cell, the peripheral circuit applies a low voltage (for example, 0 V to 2.5 V) to the word line WL to be erased and a high voltage to the P well 2b. Then, the data is erased by the electrons passing from the charge storage layer FG to the P well 2b. In this case, since electrons are injected from the conductive layer 8 into the charge storage layer FG, the threshold voltage at the time of erasing the memory cell transistor Trm may be saturated.

  Therefore, in this embodiment, the layer structure of the intergate insulating film 17 shown in FIG. 20 is adopted. FIG. 20 schematically shows a sectional view instead of FIG. 2B. As shown in FIG. 20, the inter-gate insulating film 17 that replaces the inter-gate insulating film 7 is composed of the lower insulating film 17a that replaces the lower insulating film 7a / the high dielectric insulating film 7b / the upper insulating film 17c that replaces the upper insulating film 7c. It is comprised by the laminated structure of.

  Specifically, the inter-gate insulating film 17 has a laminated structure of silicon nitride film 7aa / silicon oxide film 7ac / high dielectric insulating film 7b / silicon oxide film 7ca / high dielectric insulating film 7cc / silicon nitride film 7cb. Has been. The lower insulating film 17a has a laminated structure of silicon nitride film 7aa / silicon oxide film 7ac, and the high dielectric insulating film 7ab is not formed.

The upper insulating film 17c has a laminated structure of silicon oxide film 7ca / high dielectric insulating film 7cc / silicon nitride film 7cb, and includes a high dielectric insulating film 7cc. That is, the high dielectric insulating film 7cc is formed between the silicon nitride film 7cb and the silicon oxide film 7ca constituting the upper insulating film 17c. The high dielectric insulating film 7 cc has the same configuration as the high dielectric insulating film 7 ab of the above-described embodiment, and is formed of an oxide film of a non-transition element such as an aluminum oxide (Al ₂ O ₃ ) film, for example. ing. Other structures are the same as those in the previous embodiment.

  When such an intergate insulating film 17 is manufactured, silicon nitride film 7aa / silicon oxide film 7ac / high dielectric insulating film 7b / silicon oxide film 7ca / high dielectric insulating film 7cc / silicon nitride film 7cb are sequentially formed. By laminating, it is formed by the same method and the same film thickness as the method shown in the above embodiment. When forming the high dielectric insulating film 7 cc, it is preferable to form it with a predetermined film thickness (for example, 3 nm or less) by the ALD method.

  In the present embodiment, the inter-gate insulating film 17 is formed between the floating gate electrode FG and the control gate electrode CG from the floating gate electrode FG side to the control gate electrode CG side, from the silicon nitride film 7aa / silicon oxide film 7ac / Since it has a laminated structure of high dielectric insulating film 7b / silicon oxide film 7ca / high dielectric insulating film 7cc / silicon nitride film 7cb, leakage current flowing through the inter-gate insulating film 17 can be suppressed. .

  In particular, since the high dielectric insulating film 7cc is formed between the silicon nitride film 7cb and the silicon oxide film 7ca, the leakage current flowing through the inter-gate insulating film 17 at the time of erasing can be suppressed.

  Since the high dielectric insulating film 7cc is formed of an oxide film of a non-transition metal element (Al), it is possible to prevent re-emission of charges trapped in the high dielectric insulating film 7b and to suppress threshold fluctuation. it can.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
Although applied to the nonvolatile semiconductor memory device 1 having a stacked structure of the floating gate electrode FG, the intergate insulating film 7, and the control gate electrode CG, the present invention can also be applied to other NOR type nonvolatile semiconductor memory devices. Further, the present invention can be similarly applied to a nonvolatile semiconductor memory device having a charge trap type cell structure (referred to as MONOS or SONOS) in which a silicon nitride film is applied as a charge trap layer instead of the floating gate electrode.

Although an embodiment in which an aluminum oxide (Al ₂ O ₃ ) film is applied as the high dielectric insulating film 7b has been described, an insulating film having a relative dielectric constant higher than that of a silicon nitride film may be applied. For example, strontium (Sr), aluminum (Al), magnesium (Mg), scandium (Sc), gadolinium (Gd), yttrium (Y), samarium (Sm), hafnium (Hf), zirconium (Zr), tantalum (Ta) ), Lanthanum (La), barium (Ba), bismuth (Bi), or any other oxide or nitride single layer film, or a composite film in which some of these layers are stacked. For example, a silicon nitride (Si ₃ N ₄ ) film having a relative dielectric constant of about 7, a magnesium oxide (MgO) film having a relative dielectric constant of about 10, and an yttrium oxide (Y ₂ O ₃ ) having a relative dielectric constant of about 16 A film, a hafnium oxide (HfO ₂ ) film having a relative dielectric constant of about 22, a zirconium oxide (ZrO ₂ ) film, a lanthanum oxide (La ₂ O ₃ ), or the like can be applied. As the high dielectric insulating film 7b, any one element of silicon (Si), aluminum (Al), magnesium (Mg), yttrium (Y), hafnium (Hf), zirconium (Zr), and lanthanum (La) is used. An oxide or nitride film at least included may be applied.

As the high dielectric insulating film 7b, a hafnium oxide (HfO ₂ ) film, a zirconium oxide (ZrO ₂ ) film, a hafnium silicate (HfSiO) film containing a transition metal such as hafnium or zirconium, a hafnium aluminate (HfAlO) film Alternatively, a film having a charge trap made of a ternary compound such as zirconium aluminate (ZrAlO) or zirconium silicate (ZrSiO) may be applied. This is because a metal oxide film containing a transition metal has a large amount of electron traps and a high electric field relaxation effect due to the trap, and can increase a tunnel distance by the influence of the electric field relaxation effect and reduce a high electric field leakage current.

  As the high dielectric insulating film 7ab or 7cc, an insulating film having a relative dielectric constant higher than that of the silicon nitride film may be applied. For example, a single layer film of any of non-transition metal oxides of magnesium (Mg), strontium (Sr), barium (Ba), or bismuth (Bi) may be used. When such a single-layer film of a non-transition metal oxide is applied, the amount of traps can be smaller than that of the high dielectric insulating film 7b. Therefore, the control gate electrode layer CG of charges trapped in the high dielectric insulating film 7b or Re-emission to the floating gate electrode FG can be prevented, and the threshold fluctuation can be suppressed.

  The laminated structure of the intergate insulating films 7 and 17 can be modified or expanded as follows. For example, a silicon oxide film may be applied instead of the silicon nitride film 7aa of the first embodiment, and the silicon nitride film 7cb in the upper insulating film 7c may be formed without being provided. That is, a stacked structure of silicon oxide film / high dielectric insulating film 7ab / silicon oxide film 7ac / high dielectric insulating film 7b / silicon oxide film 7ca may be applied from the lower layer side to the upper layer side.

  Further, a laminated structure of high dielectric insulating film 7ab / silicon oxide film 7ac / high dielectric insulating film 7b, high dielectric insulating film 7b / silicon oxide film 7ac / high dielectric insulating film 7ab may be applied.

  In the above-described embodiment, the high dielectric insulating films 7ab and 7cc are provided only in the lower insulating film 7a and only in the upper insulating film 17c. However, the lower insulating film 7a and the upper insulating film 17c are not provided. The structures may be combined as the lower and upper structures of the high dielectric insulating film 7b, respectively, and the high dielectric insulating films 7ab and 7cc may be provided on both the upper and lower layers of the high dielectric insulating film 7b. That is, even if a laminated structure of silicon nitride film 7aa / high dielectric insulating film 7ab / silicon oxide film 7ac / high dielectric insulating film 7b / silicon oxide film 7ca / high dielectric insulating film 7cc / silicon nitride film 7cb is applied. good. Further, a silicon oxide film may be provided between the floating gate electrode FG on the lower layer side of the silicon nitride film 7aa as necessary. In such a configuration, both the write / erase characteristics can be improved.

  Further, from the lower layer side to the upper layer side, silicon oxide film / silicon nitride film 7aa / high dielectric insulating film 7ab / silicon oxide film 7ac / high dielectric insulating film 7b / silicon oxide film 7ca / silicon nitride film 7cb, silicon oxide film A laminated structure of / silicon nitride film 7aa / silicon oxide film 7ac / high dielectric insulating film 7b / silicon oxide film 7ca / high dielectric insulating film 7cc / silicon nitride film 7cb may be applied. That is, the present invention can also be applied to a structure in which a silicon oxide film is provided on the lower layer side of the silicon nitride film 7aa with a film thickness of about 1 nm, for example.

  In this case, when the silicon nitride film 7aa is formed directly on the floating gate electrode FG, the configuration is particularly effective when the variation of the threshold value or the increase of the interface state due to the increase of the fixed charge cannot be allowed in the device. That is, by providing the silicon oxide film on the lower layer side of the silicon nitride film 7aa, an increase in fixed charge can be suppressed, and fluctuations in threshold value can be suppressed.

The top view which shows typically the structure in a non-volatile semiconductor memory device about one Embodiment of this invention Typical sectional drawing shown along the AA line of FIG. Enlarged cross-sectional view of portion B in FIG. 2A Typical sectional drawing shown along the CC line of FIG. The figure which shows the writing time dependence of the threshold voltage at the time of writing Characteristic diagram showing the dependence of the leakage current on the applied electric field Characteristic diagram showing film thickness dependence of leakage current characteristics The figure which shows roughly the band model by the side of the floating gate electrode in the insulating film between gates Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 1) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 2) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 3) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 4) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 5) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 6) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 7) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 8) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 9) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 10) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 11) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 12) Sectional drawing shown along the AA line of FIG. 1 in the middle of manufacture (the 13) FIG. 2B equivalent view according to the second embodiment of the present invention.

Explanation of symbols

  In the drawings, 2 is a silicon substrate (semiconductor substrate), 5 is a gate insulating film (first gate insulating film), 6, FG is a floating gate electrode (charge storage layer), and 7 is an inter-gate insulating film (second gate). Insulating film), 7aa is a silicon nitride film, 7ab is a high dielectric insulating film, 7ac is a silicon oxide film, 7b is a high dielectric insulating film, 7ca is a silicon oxide film, 7cb is a silicon nitride film, 7a is a lower insulating film, 7c is an upper insulating film, 8 is a conductive layer (control gate electrode layer), and CG is a control gate electrode layer.

Claims (5)

A semiconductor substrate;
A first gate insulating film formed on the semiconductor substrate;
A charge storage layer formed on the first gate insulating film;
A second gate insulating film formed on the charge storage layer;
A control gate electrode layer formed on the second gate insulating film,
The second gate insulating film has a relative dielectric constant between a silicon oxide film and a silicon nitride film between the charge storage layer and the control gate electrode layer between the charge storage layer and the control gate electrode layer. A layer structure of a first high dielectric insulating film having a higher relative dielectric constant and a second high dielectric insulating film having a higher relative dielectric constant than that of the silicon nitride film, A nonvolatile semiconductor memory device, wherein the first and second high dielectric insulating films have a structure sandwiching the silicon oxide film. A semiconductor substrate;
A first gate insulating film formed on the semiconductor substrate;
A charge storage layer formed on the first gate insulating film;
A second gate insulating film formed on the charge storage layer;
A control gate electrode layer formed on the second gate insulating film,
The second gate insulating film includes a first silicon nitride film and a first silicon oxide film between the charge storage layer and the control gate electrode layer from the charge storage layer side to the control gate electrode layer side. And a laminated structure of a first high dielectric insulating film, a second silicon oxide film, and a second silicon nitride film having a relative dielectric constant higher than that of the silicon nitride film, The relative dielectric constant of at least one of the first silicon nitride film and the first silicon oxide film or between the second silicon nitride film and the second silicon oxide film is higher than the relative dielectric constant of the silicon nitride film. A non-volatile semiconductor memory device comprising a second high dielectric insulating film having a relative dielectric constant. A semiconductor substrate;
A first gate insulating film formed on the semiconductor substrate;
A charge storage layer formed on the first gate insulating film;
A second gate insulating film formed on the charge storage layer;
A control gate electrode layer formed on the second gate insulating film,
The second gate insulating film is a three-layer silicon oxide film of first to third silicon oxide films between the charge storage layer and the control electrode layer between the charge storage layer side and the control gate electrode layer. A three-layer silicon oxide film structure, a first high dielectric insulating film having a relative dielectric constant higher than that of the silicon nitride film, and a relative dielectric constant of the silicon nitride film. And a second high dielectric insulating film having a relative dielectric constant higher than the relative dielectric constant, and the first high dielectric insulating film is one of the two layers interposed between the three-layer silicon oxide film structures. And the second high dielectric insulating film is formed in the other of the two layers interposed between the three-layer silicon oxide film structures. .   4. The nonvolatile semiconductor memory device according to claim 1, wherein the first high dielectric insulating film includes an oxide film of a transition metal element. Forming a first gate insulating film on the semiconductor substrate;
Forming a charge storage layer on the first gate insulating film;
Forming a first silicon nitride film on the charge storage layer;
Forming a first silicon oxide film on the first silicon nitride film;
Forming a first high dielectric insulating film having a relative dielectric constant higher than that of the silicon nitride film on the first silicon oxide film;
Forming a second silicon oxide film on the first high dielectric insulating film;
Forming a second high dielectric insulating film having a relative dielectric constant higher than that of the silicon nitride film on the second silicon oxide film;
Forming a second silicon nitride film on the second high dielectric insulating film;
Forming a control gate electrode layer on the second silicon nitride film. A method for manufacturing a nonvolatile semiconductor memory device, comprising:

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