CN104752359B - memory device and forming method thereof - Google Patents
memory device and forming method thereof Download PDFInfo
- Publication number
- CN104752359B CN104752359B CN201310745692.8A CN201310745692A CN104752359B CN 104752359 B CN104752359 B CN 104752359B CN 201310745692 A CN201310745692 A CN 201310745692A CN 104752359 B CN104752359 B CN 104752359B
- Authority
- CN
- China
- Prior art keywords
- layer
- mask
- substrate
- control grid
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
Abstract
A kind of memory device and forming method thereof, wherein, the forming method of memory device includes：Substrate with memory block and external zones is provided, the substrate surface of memory block has some adjacent memory cell, memory cell includes first medium layer, floating gate layer, second dielectric layer, control grid layer and the first mask layer, and the substrate surface of external zones has device architecture；The second mask film and the 3rd mask film are formed on substrate, memory cell and device architecture surface；The 3rd mask film is etched back to, untill the second mask film of external zones is exposed, the second mask film surface in memory block forms the 3rd mask layer；Using the 3rd mask layer as mask, the second mask film is etched, to form the second mask layer；Using the second mask layer as mask, the sidewall surfaces exposed on device architecture surface and control grid layer form silicide layer.The memory device performance that is formed is good, size reduction.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of memory device and forming method thereof.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type：Analog circuit, digital circuit
With D/A hybrid circuit, wherein memory device is an important kind in digital circuit.In recent years, in memory device, dodge
Deposit（flash memory）Development it is particularly rapid.Being mainly characterized by of flash memory can keep storing for a long time in the case of not powered
Information, therefore be widely used in the various urgent needs data to be stored and will not be disappeared because of power interruptions, it is in need to repeat to read
Write the memory of data.Moreover, flash memory has the advantages that integrated level is high, access speed is fast, is easy to wipe and rewrites, thus micro-
The multinomial field such as machine, Automated condtrol is widely used.Therefore, how to lift the performance of flash memory and reduce cost into
For an important topic.
Secondly, high density flash memory technology is developed, the performance for being advantageous to all kinds of accompanied electronic equipment improves, such as makees with flash memory
For the memory device in the electronic equipments such as digital camera, notebook computer or tablet personal computer.Therefore, the chi of flash cell is reduced
It is very little, and one of direction for being technology development with this cost for reducing flash cell.For nor gate（NOR）Electrically erasable tunnel oxide
Layer（ETOX, Erase Through Oxide）Flash memories（Flash Memory）For, made electrical contact with using autoregistration
（Self-Align Contact）Technique can make the size reduction of flash memory cell.
Fig. 1 is the cross-sectional view of the flash storage device formed using autoregistration electrical contact technique, including：Substrate
100, the surface of substrate 100 has some adjacent memory cell 101, and the memory cell 101 includes：Positioned at substrate 100
The tunnel oxide 110 on surface, the floating gate layer 111 positioned at the surface of tunnel oxide 110, the insulation positioned at the surface of floating gate layer 111
Layer 112, the control grid layer 113 positioned at the surface of insulating barrier 112 and the silicon nitride layer 114 positioned at the surface of control grid layer 113；Position
Source region in substrate 100 or drain region 102 between consecutive storage unit 101；Positioned at the both sides substrate of memory cell 101
The side wall 103 on 100 surfaces；The substrate between the surface of side wall 103, the surface of silicon nitride layer 114 and consecutive storage unit 101
The electric interconnection structure 105 on 100 surfaces.
However, the flash memory cell poor-performing that prior art is formed, and size needs to be reduced.
The content of the invention
Of the invention to solve the problems, such as to be to provide a kind of memory device and forming method thereof, the memory device performance formed changes
Kind, size reduction.
To solve the above problems, the present invention provides a kind of forming method of memory device, including：Substrate, the lining are provided
Bottom has memory block and external zones, and the substrate surface of the memory block has some adjacent memory cell, the memory cell
Including：Positioned at the first medium layer of substrate surface, the floating gate layer positioned at first medium layer surface, second positioned at floating boom layer surface
Dielectric layer, the control grid layer positioned at second medium layer surface and the first mask layer positioned at control grid layer surface, the periphery
The substrate surface in area has device architecture；The second mask film, Yi Jiwei are formed on substrate, memory cell and device architecture surface
In the 3rd mask film of the second mask film surface；The 3rd mask film is etched back to, until exposing the of external zones
Untill two mask films, the second mask film surface in memory block forms the 3rd mask layer, and the 3rd mask layer is at least sudden and violent
Second mask film of exposed portion control grid layer sidewall surfaces；Using the 3rd mask layer as mask, etching described second is covered
Film film, until exposing substrate and the device architecture surface of external zones, and at least expose the side wall table of part control grid layer
Face, form the second mask layer；Using second mask layer as mask, use self-aligned silicide process device architecture surface, with
And the sidewall surfaces that control grid layer exposes form silicide layer.
Optionally, the self-aligned silicide process includes：Using depositing operation the control grid layer sidewall surfaces exposed,
The substrate surface and device architecture forming metal layer on surface of first mask layer surface, external zones；Made using annealing process described
In the surface that the material of metal level enters control grid layer side wall and device architecture exposes, silicide layer is formed；In annealing process
Afterwards, remaining metal level is removed.
Optionally, the material of the metal level is one or more combinations in nickel, cobalt, titanium, tantalum.
Optionally, the material of the silicide layer is one or more combinations in nisiloy, cobalt silicon, titanium silicide, tantalum silicide.
Optionally, the formation process of the metal level is chemical liquid deposition technique, chemical vapor deposition method or physics
Gas-phase deposition.
Optionally, the technique for being etched back to the 3rd mask film is anisotropic dry etch process.
Optionally, before the self-aligned silicide process, the 3rd mask layer is removed.
Optionally, the material of first mask layer, the second mask layer and the 3rd mask layer is different, first mask
The material of layer, the second mask layer or the 3rd mask layer is silica, silicon nitride, silicon oxynitride, amorphous carbon or low-K dielectric material
Material.
Optionally, the material of the 3rd mask layer can also be photoresist.
Optionally, the material of the first medium layer is silica, and the material of the second dielectric layer is silica, nitrogenized
One or more combinations in silicon, silicon oxynitride.
Optionally, the material of the floating gate layer and control grid layer is polysilicon.
Optionally, the device architecture is grid structure, capacitance structure, fuse-wires structure, one kind in electric resistance structure or more
Kind.
Optionally, it is described be etched back to technique after, in the surface that the device architecture exposes, at least part surface material
Expect for polysilicon.
Optionally, there is doped region in the substrate of the memory cell both sides.
Optionally, in addition to：After silicide layer is formed, the second mask is removed；After the second mask layer is removed,
The substrate surface of memory cell both sides forms side wall；Form the 3rd dielectric layer on substrate, side wall and memory cell surface, described the
Have in three dielectric layers and expose substrate surface between some first mask layer top surfaces, side wall surface and consecutive storage unit
Opening；Side wall surface, the first mask layer top surface and consecutive storage unit between substrate surface form conduction
Structure.
Accordingly, the present invention also provides a kind of memory device formed using any of the above-described method, including：Lining is provided
Bottom, the substrate have memory block and external zones；Some adjacent memory cell of substrate surface positioned at the memory block, it is described
Memory cell includes：Positioned at the first medium layer of substrate surface, the floating gate layer positioned at first medium layer surface, positioned at floating gate layer table
The second dielectric layer in face, the control grid layer positioned at second medium layer surface and the first mask layer positioned at control grid layer surface；
Positioned at the device architecture of the substrate surface of the external zones；It is located at least in part control grid layer sidewall surfaces and device architecture table
The silicide layer in face.
Optionally, there is doped region in the substrate between consecutive storage unit.
Optionally, positioned at the memory cell both sides substrate surface side wall；Positioned at side wall surface, first mask layer
The conductive structure on the doped region surface between top surface and consecutive storage unit.
Compared with prior art, technical scheme has advantages below：
In the forming method of the memory device of the present invention, form second on substrate, memory cell and device architecture surface and cover
Film film and the 3rd mask film, because the distance between the consecutive storage unit is smaller, between the consecutive storage unit made
The depth-to-width ratio of groove is larger, and the 3rd mask film is simultaneously with perpendicular to the direction of memory cell side wall and vertically
Grown in the direction of substrate surface, therefore thickness of the 3rd mask film normal being formed in the groove in substrate direction is big
In the 3rd mask film thickness that external zones is formed, so as to subsequently be etched back to the 3rd mask film to exposing external zones
The second mask film after, the second mask film surface still mask layer of remainder the 3rd of memory block, and the 3rd mask
Layer at least exposes the second mask film positioned at part control grid layer sidewall surfaces.Subsequently with the 3rd mask layer etching the
After two mask films, part control grid layer sidewall surfaces can be at least exposed.Therefore, exist using self-aligned silicide process
During the device architecture surface suicide layers of external zones, the sidewall surfaces that can be exposed accordingly in control grid layer form silicide
Layer.The control grid layer resistance formed reduces, and reduces driving voltage and energy consumption；It is additionally, since the driving control grid layer
Voltage reduces, and reduces the quantity of word line strap, so as to reduce the size of chip or integrated circuit, improves integrated level.
Further, after silicide layer is formed, technique mixing between consecutive storage unit is made electrical contact with using autoregistration
Za Qu surfaces form conductive structure, and the conductive structure formed is formed at side wall surface, first mask layer by depositing operation
Doped region surface between top surface and consecutive storage unit, the conductive structure formed will not be by consecutive storage units
Between size limitation, may advantageously facilitate memory cell density improve.
In the memory device of the present invention, at least part control grid layer sidewall surfaces and device architecture surface have silicide
Layer, the silicide layer can reduce the resistance of control grid layer, so as to reduce driving voltage and energy consumption.It is additionally, since drive
Moving the voltage of the control grid layer reduces, and reduces the quantity of word line strap, so as to reduce the size of chip or integrated circuit, makes
Integrated level improves.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the flash storage device formed using autoregistration electrical contact technique；
Fig. 2 to Fig. 8 is the cross-sectional view of the forming process of the memory device of the embodiment of the present invention.
Embodiment
As stated in the Background Art, the flash memory cell poor-performing that prior art is formed, and size needs to be reduced.
Found by research, as dimensions of semiconductor devices reduces, density improves, between consecutive storage unit 101 away from
From diminution so that insufficient space between consecutive storage unit 101 is to form the conductive plunger of connection source region or drain region 102
The electrical connection with the source region or drain region 102 is realized, as shown in Figure 1, it is necessary to which to form electricity using autoregistration electrical contact technique mutual
Link structure 105.
Please continue to refer to Fig. 1, the autoregistration electrical contact technique includes：On the surface of substrate 100, the surface of side wall 103 and deposit
The surface of storage unit 101 forms dielectric layer 106, and photoresist layer is formed on the surface of dielectric layer 106（It is not shown）, the photoresist
Layer exposes the correspondence position of some memory cell 101；The dielectric layer 106 is etched with the photoresist layer, until exposing
Untill the surface of silicon nitride layer 114 and the surface of substrate 100, opening is formed in dielectric layer 106（It is not shown）；The shape in the opening
Into electric interconnection structure 105.The electric interconnection structure 105 formed is in contact with the surface of substrate 100, so as to source region or drain region
105 apply voltage.Moreover, the electric interconnection structure 105 is electrically isolated by side wall 103 and floating gate layer 111, passes through silicon nitride layer
114 and side wall 103 be electrically isolated with control grid layer 113.Wherein, the silicon nitride layer 114 can be formed in etch media layer 106
During opening, protect the top surface of control grid layer 113, and make to be subsequently formed in the electric interconnection structure 105 in opening with
It is electrically isolated between control grid layer 113.
However, because the top surface of the control grid layer 113 has silicon nitride layer 114 so that using autocollimation silicon
Change（Self-Aligned Silicide）Technique in other regions of substrate 100 device surface formed self-alignment silicide layer when,
The self-alignment silicide layer can not be formed with the surface of control grid layer 113 so that the control grid layer 113 can not be by certainly simultaneously
Being directed at silicification technics reduces resistance, then makes the formed poor-performing of memory cell 101.Specifically, autocollimation silicon is not formed
The resistance of control grid layer 113 of compound layer, it is more than 15 times of the control grid layer resistance formed with self-alignment silicide layer, therefore,
The driving voltage of memory device as described in Figure 1 is larger, is unfavorable for reducing energy consumption.
It is larger to be additionally, since the resistance of control grid layer 113 as shown in Figure 1, thus each control grid layer 113 need with it is more
The word line strap of quantity（Word Line Strap）Connection, each control grid layer 113 is obtained enough driving voltages so that
Floating gate layer 111 realizes write-in（write）, erasing（erase）Or programming（program）Operation.However, the quantity of the word line strap
Increase can cause chip or integrated circuit dimensions increase, be unfavorable for the raising of chip or integrated circuit integrated level.
In order to solve the above problems, the present invention proposes a kind of forming method of memory device.Wherein, it is single in substrate, storage
Member and device architecture surface form the second mask film and the 3rd mask film, due to the distance between described consecutive storage unit
Smaller, the depth-to-width ratio of groove is larger between the consecutive storage unit made, and the 3rd mask film is simultaneously with perpendicular to depositing
The direction of storage unit side wall and grown perpendicular to the direction of substrate surface, therefore the 3rd mask being formed in the groove
Thickness of the film normal in substrate direction is more than the 3rd mask film thickness that external zones is formed, so as to described in follow-up be etched back to
After 3rd mask film to the second mask film for exposing external zones, the second mask film surface still remainder of memory block
3rd mask layer, and the 3rd mask layer at least exposes the second mask film positioned at part control grid layer sidewall surfaces.
After subsequently etching the second mask film with the 3rd mask layer, part control grid layer sidewall surfaces can be at least exposed.
Therefore, can be accordingly in control gate when using device architecture surface suicide layers of the self-aligned silicide process in external zones
The sidewall surfaces that layer exposes form silicide layer.The control grid layer resistance formed reduces, and reduces driving voltage and energy consumption；
It is additionally, since and drives the voltage of the control grid layer to reduce, reduce the quantity of word line strap, so as to reduces chip or integrated electricity
The size on road, improves integrated level.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 8 is the cross-sectional view of the forming process of the memory device of the embodiment of the present invention.
It refer to Fig. 2, there is provided substrate 200, the substrate 200 have memory block 201 and external zones 202, the memory block
201 surface of substrate 200 has some adjacent memory cell 203, and the memory cell 203 includes：Positioned at the surface of substrate 200
First medium layer 231, the floating gate layer 232 positioned at the surface of first medium layer 231, the second medium positioned at the surface of floating gate layer 232
Layer 233, the control grid layer 234 positioned at the surface of second dielectric layer 233 and the first mask layer positioned at the surface of control grid layer 234
235, the surface of substrate 200 of the external zones 202 has device architecture 204.
The substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator（SOI）On substrate, insulator
Germanium（GOI）Substrate, glass substrate or III-V substrate, such as gallium nitride or GaAs etc..The substrate 200 is deposited
Storage area 201 is used to form memory device, and the external zones 202 of the substrate 200 is used to being formed peripheral circuit, the peripheral circuit by
Device architecture 204 and electric interconnection structure are formed.
The memory device that the memory cell 203 is formed is nor gate（NOR）Electrically erasable tunnel oxide（ETOX,
Erase Through Oxide）Flash memories.Wherein, the material of the first medium layer 231 is silica, described first
Dielectric layer 231 is tunnel oxide, channel region and floating gate layer 232 of the electronics by the first medium layer 231 in substrate 200
Between migrate, with realize write-in, erasing or programming etc. operation.The material of the floating gate layer 232 is polysilicon, the floating gate layer
Electronics can be stored in 232, to realize that the power-off for data stores.The second dielectric layer 233 is used to isolate the floating boom
Layer 232 and control grid layer 234, the material of the second dielectric layer 233 is silica, silicon nitride, one kind in silicon oxynitride or
Multiple combinations；Preferably, the second dielectric layer 233 is by silicon oxide layer, the silicon nitride layer positioned at silicon oxide layer surface, Yi Jiwei
Silicon oxide layer in silicon nitride layer surface is formed, i.e., described second dielectric layer 233 is oxide-nitride-oxide（ONO）Knot
Structure, the isolating power of the oxide-nitride-oxide structure is strong, and good with the binding ability of polycrystalline silicon material, can
Control grid layer 234 and floating gate layer 232 are effectively isolated, and makes the combination between control grid layer 234 and floating gate layer 232 stable.
The material of the control grid layer 234 is polysilicon, and the control grid layer 234 is used to be biased floating gate layer 232, passes through difference
Be biased to control the floating gate layer 232 of bottom it is specific performs write-in, erasing or programs etc. operate.
The formation process of the memory cell 203 includes：First medium film is formed on the surface of substrate 200；In first medium
Film surface forms the first polysilicon film；Second medium film is formed on the first polysilicon film surface；Formed on second medium film surface
Second polysilicon film；The first mask layer 235 is formed on the second polysilicon film surface, first mask layer 235 covers
Memory block 201 needs to form the correspondence position of memory cell 203；It is mask with first mask layer 235, using each to different
Property dry etch process etch the second polysilicon film, second medium film, the first polysilicon film and the first medium film, until
Untill exposing the surface of substrate 200, first medium layer 231, floating gate layer 232, the are formed on the surface of substrate 200 of memory block 201
Second medium layer 233 and control grid layer 234；Wherein, the first polysilicon film etches to form floating gate layer 232, the second polysilicon film etching
Form control grid layer 234.Second polysilicon film, second medium film, the formation work of the first polysilicon film and first medium film
Skill is chemical vapor deposition method or physical gas-phase deposition；In addition, the first medium film can also pass through thermal oxide work
Skill or wet process oxidation technology are formed.
Wherein, first mask layer 235 can also be formed on the surface of substrate 200 subsequently in consecutive storage unit 203
During conductive structure, the top surface of control grid layer 234 is protected, makes control grid layer 234 with being formed at leading for the top of memory cell 203
It is electrically isolated between electric structure.The material of first mask layer 235 is silicon nitride, the formation process of first mask layer 235
Including：The first mask film is formed on the second polysilicon film surface；Photoresist layer is formed in the first mask film surface；To described
Photoresist layer is exposed with graphical；Using patterned photoresist layer as mask, using anisotropic dry etch process
The first mask film is etched, untill the second polysilicon film is exposed, forms the first mask layer 235.
The surface of substrate 200 of the external zones 202 is also formed with device architecture 204, and the device architecture 204 is grid knot
One or more in structure, capacitance structure, fuse-wires structure, electric resistance structure.The device architecture 204 shown in the present embodiment Fig. 2 is
For forming the grid structure of transistor, the grid structure includes：Gate dielectric layer 241 positioned at the surface of substrate 200；Positioned at grid
The grid layer 242 on the surface of dielectric layer 241；The first side wall positioned at gate dielectric layer 241 and the surface of 242 both sides substrate of grid layer 200
243。
In the present embodiment, the device architecture 204 is formed simultaneously with memory cell 203.Specifically, the grid layer 242
The second sub- grid layer 242b including the first sub- grid layer 242a and positioned at the first sub- grid layer 242a surfaces.Wherein, it is described
First sub- grid layer 242a is etched by the first polysilicon film to be formed, and the second sub- grid layer 242b is etched by the second polysilicon film
Formed, the gate dielectric layer 241 is etched by first medium film to be formed.First mask layer is also formed into the of external zones 202
Two polysilicon film surfaces, and cover and need to form the correspondence position of grid layer 242, with the first mask of memory block 201
When the etching of layer 235 forms memory cell 203, the first polysilicon film, the second polysilicon are etched with the first mask layer of external zones 202
Film and first medium layer, to form gate dielectric layer 241, the first sub- sub- grid layer 242b of grid layer 242a and second, and in institute
State the first mask layer that etching technics removes external zones afterwards.Due to also having the first mask layer 235 and the in memory cell 203
Second medium layer 233, therefore the height of the memory cell 203 is high compared with the height of device architecture 204.
After gate dielectric layer 241 and grid layer 242 is formed, memory block 201 is covered with photoresist layer, and using deposition work
Skill forms side wall with technique is etched back in the sidewall surfaces of the gate dielectric layer 241 and the both sides of grid layer 242 and the surface of substrate 200
243, the material of the side wall 243 is one or more combinations in silica, silicon nitride, silicon oxynitride, and the side wall 243 is used
The position in source region and drain region in grid structure both sides substrate 200 is formed in definition.After the side wall 243 is formed, use
Ion implantation technology forms source region and drain region in the substrate 200 of grid structure both sides.
Refer to Fig. 3, substrate 200, memory cell 203 and the surface of device architecture 204 formed the second mask film 205,
And the 3rd mask film 206 positioned at the surface of the second mask film 205.
The second mask film 205 is subsequently used for forming the second mask layer, and second mask layer is as subsequently from right
The mask of quasi- planning technique.The 3rd mask film 206 is used to form the 3rd mask layer, and the 3rd mask layer is as fixed
The mask of adopted second mask layer pattern.
The second mask film 205 is different with the material of the 3rd mask film 206, makes the second mask film 205
And the 3rd have Etch selectivity between mask film 206, after the mask film 206 of subsequent etching the 3rd, institute can be retained
State the second mask film 205.Moreover, the material of first mask layer 235 also differs with the second mask film 205, then after
Continue when etching the second mask film 205, the pattern of first mask layer 235 will not be damaged, make the first mask layer 235
During conductive structure is subsequently formed, the top surface of control grid layer 234 can be protected.First mask layer 235,
The material of two mask films 205 or the 3rd mask film 206 is that silica, silicon nitride, silicon oxynitride, amorphous carbon or low K are situated between
Material.In addition, the material of the 3rd mask film 206 can also be photoresist.
In the present embodiment, the material of the second mask film 205 is silica, the shape of the second mask film 205
It is chemical vapor deposition method, atom layer deposition process or physical gas-phase deposition into technique；The 3rd mask film 206
Material be photoresist, the formation process of the 3rd mask film 206 is spin coating or spraying coating process.
In the present embodiment, there are some memory cell 203 in memory block 201, and is formed between consecutive storage unit 203
Groove（Do not indicate）.For the raising of the integrated level of chip or integrated circuit, size reduction, the memory cell 203 is parallel to lining
The size reduction of the surface direction of bottom 200, and the distance between consecutive storage unit 203 reduce, i.e., consecutive storage unit 203 it
Between groove depth-to-width ratio mutually strain greatly.The thinner thickness of the second mask film 205, the second mask film 205 formed
It is covered in memory cell 203, device architecture 204 and the surface of substrate 200.The thickness of the 3rd mask film 206 is thicker, described
3rd mask film 206 is filled in the groove between consecutive storage unit 203, moreover, being formed at the 3rd in the groove
The thickness ratio of mask film 206 is formed at the thickness of the 3rd mask film 206 of device architecture 204 and the film of 202 substrate of external zones 200
It is thicker.
Specifically, when the formation process of the 3rd mask film 206 is sunk for chemical vapor deposition method or physical vapor
During product technique, in the groove, the 3rd mask film 206 is simultaneously with perpendicular to the surface direction of substrate 200 and vertically
Grown in the sidewall surfaces direction of memory cell 203, i.e., the growth rate of the 3rd mask film 206 in groove faster makes in groove
The thickness of the 3rd mask film 206 it is thicker.When the 3rd mask film 206 for photoresist when, formation process be spin coating or
Spraying coating process, photoresist is set to be more easy to enter in groove, so that the thickness of the 3rd mask film 206 in groove is thicker.
The 3rd of the thickness ratio external zones 202 of the 3rd mask film 206 due to being formed between consecutive storage unit 203 covers
The thickness of film film 206 is thicker, and the 3rd mask that external zones 202 can be subsequently removed using anisotropic dry etch process is thin
Film 206, and the mask film 206 of channel bottom member-retaining portion the 3rd between consecutive storage unit 203.
Fig. 4, it is etched back to the 3rd mask film 206（As shown in Figure 3）, covered until exposing the second of external zones 202
Untill film film 205, the 3rd mask layer 206a, the 3rd mask are formed on the surface of the second mask film 205 of memory block 201
Layer 206a at least exposes the second mask film 205 of the sidewall surfaces of part control grid layer 234.
Masks of the 3rd mask layer 206a as the second mask film 205 of etching, and to etch the second mask film
Mask of 205 the second mask layers formed as follow-up self-aligned silicide process, because the 3rd mask layer 206a is at least sudden and violent
Second mask film 205 of the sidewall surfaces of exposed portion control grid layer 234, therefore the second mask layer that subsequent etching is formed is also extremely
The surface of the side wall of part control grid layer 234 is exposed less, so as to make self-aligned silicide process sudden and violent in the control grid layer 234
The sidewall surfaces exposed form silicide layer, the resistance of control grid layer 234 are reduced with this, so as to reduce the work of memory cell 203
Make voltage and energy consumption, improve the performance of memory cell 203.
The technique that is etched back to is anisotropic dry etch process, the quarter of the anisotropic dry etch process
Lose direction perpendicular to the surface of substrate 200, and on the direction on the surface of substrate 200 etch rate it is uniform, deposited due to adjacent
The thickness of the 3rd mask film 206 of the thickness ratio external zones 202 of the 3rd mask film 206 between storage unit 203 is thick, therefore is carving
, being capable of member-retaining portion the in the groove between consecutive storage unit 203 when etching off removes the 3rd mask film 206 of external zones 202
Three mask films 206 are to form the 3rd mask layer 206a.
By controlling the thickness of the 3rd mask layer 206a and forming the technique of the 3rd mask film 206, can make
Second mask film 205 of the 3rd mask layer 206a covering sidewall surfaces of floating gate layer 242 after etching, and at least expose portion
Divide the second mask film 205 of the sidewall surfaces of control gate 234.In follow-up self-aligned silicide process, floating gate layer 242 can obtain
To the second mask layer protection without forming silicide layer, make floating gate layer 242 can be used in store electronics.In the present embodiment,
The 3rd mask layer 206a completely reveals the second mask film 205 of the sidewall surfaces of control gate 234, the then silicon being subsequently formed
The sidewall surfaces of control gate 234 are completely covered in compound layer.
Fig. 5 is refer to, with the 3rd mask layer 206a（As shown in Figure 4）For mask, the second mask film is etched
205（As shown in Figure 4）, until exposing substrate 200 and the surface of device architecture 204 of external zones 202, and at least expose part
The sidewall surfaces of control grid layer 234, form the second mask layer 205a；After the second mask layer 205a is formed, described the is removed
Three mask layer 206a.
Masks of the second mask layer 205a as follow-up self-aligned silicide process, due to the 3rd mask layer 206a
At least expose the second mask film 205 on the surface of the side wall of part control gate 234, therefore with the 3rd mask layer 206a etchings the
After two mask films 205, the second mask layer 205a formed at least exposes the sidewall surfaces of part control grid layer 234.
In the present embodiment, the second mask layer 205a completely reveals the sidewall surfaces of control gate 234, the silicide layer being subsequently formed
Cover all sidewall surfaces of control gate 234.
The technique for etching the second mask film 205 is dry etch process or wet-etching technology.In the present embodiment
In, the technique of the second mask film 205 of etching is wet-etching technology, because the material of the second mask film 205 is oxygen
SiClx, the etching liquid of the wet-etching technology is hydrofluoric acid solution；The wet-etching technology is single for substrate 200, storage
Member 203 and device architecture 204 it is described smaller, and etch rate is fast.
The technique for removing the 3rd mask layer 206a is dry etch process or wet-etching technology, it is preferred that wet etching
Technique, surface, the second mask layer 205a surfaces, the surface of substrate 200 and the table of device architecture 204 for exposing memory cell 203
The damage that face is subject to is smaller.In addition, in the present embodiment, the material of the 3rd mask layer 206a is photoresist, then can also
The 3rd mask layer 206a is removed using degumming process or cineration technics.
Fig. 6 is refer to, using depositing operation in the sidewall surfaces of control grid layer 234 exposed, the second mask layer 205a tables
Face, the surface of the first mask layer 235, the surface of substrate 200 of external zones 202 and the forming metal layer on surface 207 of device architecture 206.
The material of the metal level 207 is that the one or more in nickel, cobalt, titanium, tantalum combine, the shape of the metal level 207
It is and chemical liquid deposition technique, chemical vapor deposition method or physical gas-phase deposition into technique.
Specifically, when the metal level 207 is nickel, the chemical liquid deposition technique is：Reaction solution includes NiSO4
Solution and (NH4)2SO4、NH4F and C6H5Na3O7One or more in solution, wherein, the NiSO4In reaction solution
Molar concentration be 0.01mol/L~1mol/L；The pH value of the reaction solution is 8~10；Sedimentation time is 30 seconds~3000
Second, depositing temperature is 0 DEG C~90 DEG C.
Because the second mask layer 205a exposes the sidewall surfaces of control grid layer 234, the metal level 207 is formed at
The sidewall surfaces of control grid layer 234, the metallic atom in the metal level 207 can spread to control gate 234, to form silicon
Compound layer, the resistance of control gate 234 is reduced with this.In addition, the metal level 207 is also formed into the table of substrate 200 of external zones 202
Face and the surface of grid layer 242, can be in the grid layer 242 of external zones 202, source region and drain region surface shape after the annealing made
Into silicide layer.
Fig. 7 is refer to, the material for making the metal level 207 using annealing process enters the side wall of control grid layer 234 and device
In the surface that structure 206 exposes, the sidewall surfaces exposed on the surface of device architecture 206 and control grid layer 234 form silicon
Compound layer 208.
The thermal anneal process is rapid thermal annealing, spike thermal annealing or laser thermal anneal；Specifically, quickly moved back when using
When fiery, the temperature of the rapid thermal annealing is 200~500 DEG C, and the time is 10 seconds~120 seconds, and protective gas is nitrogen or inertia
Gas；When using spike thermal annealing, temperature is 300~600 DEG C, and protective gas is nitrogen or inert gas；When using laser
During thermal annealing, temperature is 500~900 DEG C, and the time is 0.1 millisecond~2 milliseconds, and protective gas is nitrogen or inert gas.Institute's shape
Into silicide layer 207 thickness and annealing time extension and increase.
In the annealing process, the metallic atom in metal level 207 can spread into the control gate 234 being in contact,
The metallic atom can react to form silicide material with the polycrystalline silicon material of control gate 234, the silicide layer 208 formed
Material be nisiloy, cobalt silicon, titanium silicide, one or more combinations in tantalum silicide.The silicide layer 208 can make control gate
The resistance of layer 234 reduces, and so as to reduce the driving voltage of memory cell 203 and power consumption, improves the performance and stably of memory cell
Property.In the present embodiment, silicide layer 208 is formed close to the part of the sidewall surfaces of control gate 234.In another embodiment, institute
The material for stating control gate 234 is fully converted to silicide material.
In the present embodiment, silicide layer 208 is also formed into the surface of substrate 200 and the table of grid layer 242 of external zones 202
Face, the silicide layer can be as grid layer 242, source region and the electric contacting layers in drain region, subsequently can be in the silicon of external zones 202
The surface of compound layer 208 forms conductive structure, to realize and grid layer 242, source region and the electrical connection in drain region.
Fig. 8 is refer to, after an anneal process, removes remaining metal level 207（As shown in Figure 7）With remove the second mask
Layer 205a（As shown in Figure 7）；After the second mask layer 205a is removed, formed on the surface of substrate 200 of the both sides of memory cell 203
Side wall（Do not indicate）；The 3rd dielectric layer 209, the 3rd dielectric layer are formed on substrate 200, side wall and the surface of memory cell 203
Have in 209 and expose substrate 200 between some top surfaces of first mask layer 235, side wall surface and consecutive storage unit 203
The opening on surface（It is not shown）；Conductive structure 210 is formed in the opening.
The technique for removing residual metallic layer 207 and the second mask layer 205a is dry etch process or wet-etching technology,
Be in the present embodiment wet-etching technology, the selectivity of the wet-etching technology is excellent, can thoroughly remove it is remaining
Device architecture 204, memory cell 203 and silicide layer 208 is not lost while metal level 207.
The material of the side wall is one or more combinations in silica, silicon nitride or silicon oxynitride.The side wall energy
It is enough to protect the sidewall surfaces of memory cell 203 when forming the opening in the 3rd dielectric layer 209, and conduction can be electrically isolated
Structure 210 and the memory cell 203., can be in the side wall and the both sides of memory cell 203 after the side wall is formed
Form doped region in substrate 200, the doped region is used for source region or drain region as memory cell 203, in the doped region
Doped ions are p-type ion or N-type ion.
The material of the conductive structure 210 is metal, and the conductive structure 210 electrically connects with the doped region, for controlling
The channel region of the bottom of memory cell 203 processed is turned on and off, and enables the conductive structure 210 to select to be used to be write, wiped
The a certain memory cell 203 of operation is removed or becomes, i.e., described conductive structure 210 is the selection grid of the memory device formed
（select gate）Or bit line（bit line）.
The formation process of 3rd dielectric layer 209 includes：In the surface of substrate 200, the surface of side wall 208, memory cell 203
Surface and the surface of device architecture 204 form deielectric-coating, and the material of the deielectric-coating is silica, silicon nitride, silicon oxynitride or low K
Dielectric material；Photoresist layer is formed on the deielectric-coating surface, the photoresist layer exposes the correspondence of some memory cell 203
Position；Using the photoresist layer as mask, the deielectric-coating is etched using anisotropic dry etch process until exposing
Untill first mask layer 235, side wall and the surface of substrate 200, the opening in formation dielectric layer 210 and dielectric layer 210；Form opening
Afterwards, photoresist layer is removed.
The material of the conductive structure 210 is copper, tungsten or aluminium.The conductive structure 210 is formed at the surface of side wall 208,
The surface of substrate 200 between the top surface and consecutive storage unit 203 of one mask layer 235 forms conductive structure 210.Specifically
, the formation process of the conductive structure 210 includes：Conducting film is formed in the surface of dielectric layer 210 and opening, it is described to lead
The full opening of electrolemma filling；The conducting film is planarized using CMP process, until exposing the dielectric layer
Untill 210 surfaces, conductive structure 210 is formed in opening.
In one embodiment, barrier layer is also formed between the side wall and lower surface of the conductive structure 210 and opening,
The material on the barrier layer is the combination of one or both of titanium nitride, tantalum nitride, and the barrier layer is as the chemical machinery
The stop position of glossing.
In the forming method of the present embodiment, substrate, memory cell and device architecture surface formed the second mask film and
3rd mask film, because the distance between the consecutive storage unit is smaller, the depth of groove between the consecutive storage unit made
It is wide bigger, and the 3rd mask film is simultaneously with perpendicular to the direction of memory cell side wall and perpendicular to substrate table
The direction growth in face, therefore thickness of the 3rd mask film normal being formed in the groove in substrate direction is more than external zones
The 3rd mask film thickness formed, so as to be covered being subsequently etched back to the 3rd mask film to expose external zones second
After film film, the second mask film surface still mask layer of remainder the 3rd of memory block, and the 3rd mask layer is at least sudden and violent
Expose the second mask film positioned at part control grid layer sidewall surfaces.It is thin that the second mask is subsequently etched with the 3rd mask layer
After film, part control grid layer sidewall surfaces can be at least exposed.Therefore, self-aligned silicide process is being used in external zones
During device architecture surface suicide layers, the sidewall surfaces that can be exposed accordingly in control grid layer form silicide layer.Institute's shape
Into control grid layer resistance reduce, reduce driving voltage and energy consumption；It is additionally, since the voltage drop for driving the control grid layer
It is low, the quantity of word line strap is reduced, so as to reduce the size of chip or integrated circuit, improves integrated level.
Accordingly, the embodiment of the present invention also provides a kind of memory device, please continue to refer to Fig. 8, including：Substrate 200 is provided,
The substrate 200 has memory block 201 and external zones 202；It is some adjacent positioned at the surface of substrate 200 of the memory block 201
Memory cell 203, the memory cell 203 include：First medium layer 231 positioned at the surface of substrate 200, positioned at first medium layer
The floating gate layer 232 on 231 surfaces, the second dielectric layer 233 positioned at the surface of floating gate layer 232, the control positioned at the surface of second dielectric layer 233
Gate layer 234 processed and the first mask layer 235 positioned at the surface of control grid layer 234；Positioned at the table of substrate 200 of the external zones 202
The device architecture 204 in face；It is located at least in the silicide layer on the sidewall surfaces of part control grid layer 234 and the surface of device architecture 204
208。
In the memory device structures of the present embodiment, in addition to have in substrate 200 between consecutive storage unit 203 and mix
Miscellaneous area；Side wall 208 positioned at the surface of substrate 200 of the both sides of memory cell 203；Positioned at the surface of side wall 208, the first mask layer
The conductive structure 210 on the doped region surface between 235 top surface and consecutive storage unit 203.
In the structure of the present embodiment, at least part control grid layer sidewall surfaces and device architecture surface have silicide
Layer, the silicide layer can reduce the resistance of control grid layer, so as to reduce driving voltage and energy consumption.It is additionally, since drive
Moving the voltage of the control grid layer reduces, and reduces the quantity of word line strap, so as to reduce the size of chip or integrated circuit, makes
Integrated level improves.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (18)
- A kind of 1. forming method of memory device, it is characterised in that including：Substrate is provided, the substrate has memory block and external zones, and the substrate surface of the memory block has some adjacent deposit Storage unit, the memory cell include：Positioned at the first medium layer of substrate surface, the floating gate layer positioned at first medium layer surface, Second dielectric layer positioned at floating boom layer surface, the control grid layer positioned at second medium layer surface and positioned at control grid layer surface The first mask layer, the substrate surface of the external zones has device architecture；The second mask film is formed on substrate, memory cell and device architecture surface and positioned at the second mask film surface 3rd mask film；Wherein, the material of first mask layer is different from the material of the second mask film；The 3rd mask film is etched back to, untill the second mask film of external zones is exposed, second in memory block Mask film surface forms the 3rd mask layer, and the 3rd mask layer at least exposes the second of part control grid layer sidewall surfaces Mask film；Using the 3rd mask layer as mask, the second mask film is etched, until exposing the substrate and device of external zones Body structure surface, and the sidewall surfaces of part control grid layer are at least exposed, form the second mask layer；Using second mask layer as mask, exposed using self-aligned silicide process on device architecture surface and control grid layer The sidewall surfaces gone out form silicide layer.
- 2. the forming method of memory device as claimed in claim 1, it is characterised in that the self-aligned silicide process includes： Using depositing operation in the control grid layer sidewall surfaces exposed, the first mask layer surface, the substrate surface of external zones, Yi Jiqi Part body structure surface forms metal level；The material for making the metal level using annealing process enters control grid layer side wall and device architecture In the surface exposed, silicide layer is formed；After an anneal process, remaining metal level is removed.
- 3. the forming method of memory device as claimed in claim 2, it is characterised in that the material of the metal level be nickel, cobalt, One or more combinations in titanium, tantalum.
- 4. the forming method of memory device as claimed in claim 3, it is characterised in that the material of the silicide layer is nickel One or more combinations in silicon, cobalt silicon, titanium silicide, tantalum silicide.
- 5. the forming method of memory device as claimed in claim 2, it is characterised in that the formation process of the metal level is change Learn liquid deposition technique, chemical vapor deposition method or physical gas-phase deposition.
- 6. the forming method of memory device as claimed in claim 1, it is characterised in that the 3rd mask film of being etched back to Technique is anisotropic dry etch process.
- 7. the forming method of memory device as claimed in claim 1, it is characterised in that before the self-aligned silicide process, Remove the 3rd mask layer.
- 8. the forming method of memory device as claimed in claim 1, it is characterised in that first mask layer, the second mask Layer is different with the material of the 3rd mask layer, the material of first mask layer, the second mask layer or the 3rd mask layer be silica, Silicon nitride, silicon oxynitride, amorphous carbon or low-K dielectric material.
- 9. the forming method of memory device as claimed in claim 8, it is characterised in that the material of the 3rd mask layer can also Enough it is photoresist.
- 10. the forming method of memory device as claimed in claim 1, it is characterised in that the material of the first medium layer is Silica, the material of the second dielectric layer are one or more combinations in silica, silicon nitride, silicon oxynitride.
- 11. the forming method of memory device as claimed in claim 1, it is characterised in that the floating gate layer and control grid layer Material is silicon.
- 12. the forming method of memory device as claimed in claim 1, it is characterised in that the device architecture be grid structure, One or more in capacitance structure, fuse-wires structure, electric resistance structure.
- 13. the forming method of memory device as claimed in claim 1, it is characterised in that it is described be etched back to technique after, institute State in the surface that device architecture exposes, at least part surfacing is polysilicon.
- 14. the forming method of memory device as claimed in claim 1, it is characterised in that the substrate of the memory cell both sides It is interior that there is doped region.
- 15. the forming method of memory device as claimed in claim 1, it is characterised in that also include：Formed silicide layer it Afterwards, the second mask is removed；After the second mask layer is removed, the substrate surface in memory cell both sides forms side wall；Substrate, Side wall and memory cell surface form the 3rd dielectric layer, have in the 3rd dielectric layer and expose at the top of some first mask layers The opening of substrate surface between surface, side wall surface and consecutive storage unit；In side wall surface, the top surface of the first mask layer And the substrate surface between consecutive storage unit forms conductive structure.
- A kind of 16. memory device that any one method using as described in claim 1 to 15 is formed, it is characterised in that bag Include：Substrate is provided, the substrate has memory block and external zones；Some adjacent memory cell of substrate surface positioned at the memory block, the memory cell include：Positioned at substrate surface First medium layer, the floating gate layer positioned at first medium layer surface, the second dielectric layer positioned at floating boom layer surface, positioned at second be situated between The control grid layer of matter layer surface and the first mask layer positioned at control grid layer surface；Positioned at the device architecture of the substrate surface of the external zones；It is located at least in the silicide layer on part control grid layer sidewall surfaces and device architecture surface.
- 17. memory device as claimed in claim 16, it is characterised in that also include：Between consecutive storage unit There is doped region in substrate.
- 18. memory device as claimed in claim 17, it is characterised in that also include：Lining positioned at the memory cell both sides The side wall of basal surface；Positioned at side wall surface, the first mask layer top surface and consecutive storage unit between doped region table The conductive structure in face.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310745692.8A CN104752359B (en) | 2013-12-30 | 2013-12-30 | memory device and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310745692.8A CN104752359B (en) | 2013-12-30 | 2013-12-30 | memory device and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104752359A CN104752359A (en) | 2015-07-01 |
| CN104752359B true CN104752359B (en) | 2017-12-29 |
Family
ID=53591834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310745692.8A Active CN104752359B (en) | 2013-12-30 | 2013-12-30 | memory device and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104752359B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106531741B (en) * | 2015-09-10 | 2019-09-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN105513954B (en) * | 2016-01-29 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor devices |
| US10263004B2 (en) * | 2017-08-01 | 2019-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing |
| CN107731837A (en) * | 2017-09-19 | 2018-02-23 | 上海华虹宏力半导体制造有限公司 | Memory process method |
| CN108511448A (en) * | 2018-03-23 | 2018-09-07 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor structure |
| CN109524407B (en) * | 2018-10-19 | 2020-12-04 | 武汉新芯集成电路制造有限公司 | Memory and manufacturing method thereof |
| CN113380812B (en) * | 2020-02-25 | 2023-06-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN111326416B (en) * | 2020-04-01 | 2022-09-30 | 上海华虹宏力半导体制造有限公司 | Etching method |
| CN113745228B (en) * | 2020-05-29 | 2024-03-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113192959B (en) * | 2021-04-27 | 2023-11-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split gate type flash memory |
| CN116206969A (en) * | 2021-11-30 | 2023-06-02 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method and semiconductor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101145560A (en) * | 2006-09-15 | 2008-03-19 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| CN101399205A (en) * | 2007-09-28 | 2009-04-01 | 力晶半导体股份有限公司 | Method for making flash memory |
| CN102194758A (en) * | 2010-03-17 | 2011-09-21 | 宜扬科技股份有限公司 | Method for manufacturing straight character line NOR flash memory array |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110090442A (en) * | 2010-02-04 | 2011-08-10 | 삼성전자주식회사 | Non-volatile memory device and method of manufacturing the same |
-
2013
- 2013-12-30 CN CN201310745692.8A patent/CN104752359B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101145560A (en) * | 2006-09-15 | 2008-03-19 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| CN101399205A (en) * | 2007-09-28 | 2009-04-01 | 力晶半导体股份有限公司 | Method for making flash memory |
| CN102194758A (en) * | 2010-03-17 | 2011-09-21 | 宜扬科技股份有限公司 | Method for manufacturing straight character line NOR flash memory array |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104752359A (en) | 2015-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104752359B (en) | memory device and forming method thereof | |
| CN104752434B (en) | Memory device and forming method thereof | |
| CN104752360B (en) | memory device and forming method thereof | |
| CN104900593B (en) | Memory and forming method thereof | |
| KR100831390B1 (en) | High density flash memory device and fabricating method thereof | |
| CN106206445B (en) | The forming method of memory construction | |
| TW202145453A (en) | Ferroelectric memory device and method of forming the same | |
| CN104091803A (en) | Split gate memory, semiconductor device and method for making semiconductor device | |
| CN104681493A (en) | Forming method of semiconductor structure | |
| CN106601744B (en) | A kind of embedded flash memory and its manufacturing method and electronic device | |
| CN113035883A (en) | Three-dimensional memory and manufacturing method thereof | |
| CN105762114B (en) | The forming method of semiconductor structure | |
| CN106298788B (en) | Memory construction and forming method thereof | |
| CN111415937A (en) | Memory and forming method thereof | |
| CN108807393A (en) | Memory and forming method thereof | |
| CN105655341A (en) | Method for forming semiconductor device | |
| CN105513954A (en) | Forming method of semiconductor device | |
| CN104465664A (en) | Split-gate flash memory and manufacturing method thereof | |
| CN109659237B (en) | Forming method of flash memory device | |
| US11652004B2 (en) | Methods for forming memory devices | |
| US20220352207A1 (en) | 3d memory multi-stack connection method | |
| US11758735B2 (en) | Common-connection method in 3D memory | |
| US20230371242A1 (en) | Method for fabricating semiconductor device with oxide semiconductor material | |
| CN104752610B (en) | Semiconductor structure and forming method thereof | |
| CN117082861A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |