CN101399205A - Method for making flash memory - Google Patents
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- CN101399205A CN101399205A CNA2007101531614A CN200710153161A CN101399205A CN 101399205 A CN101399205 A CN 101399205A CN A2007101531614 A CNA2007101531614 A CN A2007101531614A CN 200710153161 A CN200710153161 A CN 200710153161A CN 101399205 A CN101399205 A CN 101399205A
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- 238000000034 method Methods 0.000 title claims abstract description 101
- 230000015654 memory Effects 0.000 title claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 54
- 238000007667 floating Methods 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 45
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 196
- 230000008569 process Effects 0.000 claims description 53
- 239000011241 protective layer Substances 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 239000002210 silicon-based material Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 2
- 150000003376 silicon Chemical class 0.000 claims 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 238000003860 storage Methods 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
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- 238000004891 communication Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention provides a method for manufacturing a flash memory, comprising the steps: a floating grid dielectric layer, a floating grid material layer, a dielectric layer, a control grid material layer, a metal silicide layer and a hard mask layer are sequentially formed on the surface of a semiconductor substrate, and then the hard mask layer is patterned; after that, the metal silicide layer, the control grid material layer, the dielectric layer and the floating grid dielectric layer which are covered by the hard mask layer are removed to form a stacking structure, the a silicon covering layer is formed to cover on the surface of the stacking structure, and then a thermal technique is carried out.
Description
Technical field
The invention provides a kind of manufacture method of flash memory, refer to that especially a kind of silicon protective layer that utilizes is with the structure of improving memory and the flash memory manufacture method of operating quality.
Background technology
Nonvolatile memory has can repeat the characteristic of erasing and reading and writing, add transmission fast, low power consumption, so application is very extensive, become the necessary element in many information, communication and the consumption electronic products.Yet,, promote the element integrated level of nonvolatile memory and the emphasis that quality just becomes current information industry and memory development of manufacturing for light and handy and high-quality electronic element products are provided.
Data bits according to the unit storage unit storage, non-volatile memory cells can be divided into single position again and store (single-bit storage) nonvolatile memory and dibit storage (dual-bit storage) nonvolatile memory, wherein common dibit stores nonvolatile memory for example separate grid type silicon-silica-silicon-nitride and silicon oxide-silicon type (Silicon-Oxide-Nitride-Oxide-Silicon, SONOS) memory and separate grid type metal-oxide silicon-silicon-nitride and silicon oxide-silicon type (Metal-Oxide-Nitride-Oxide-Silicon, MONOS) memory etc.Because the unit storage unit of separate grid type SONOS type memory and separate grid type MONOS type memory can store two information, therefore compared to general single position storage nonvolatile memory, can store more substantial information, become the main flow of nonvolatile memory gradually.
Please refer to Fig. 1 to Fig. 2, Fig. 1 to Fig. 2 is the process schematic representation of known making one separated grid electrode type quick flashing storage 10.At first as shown in Figure 1, semiconductor substrate 12 is provided, form an oxide layer 14 in surface, the semiconductor-based ends 12 then, then via technologies such as several deposition, photoetching and etchings, form a plurality of stacking structures 28 in surface, the semiconductor-based ends 12, comprise floating grid 16, dielectric layer 18, control grid 20, metal silicide layer 22 and hard mask layer 24 from the bottom to top in regular turn.Wherein, metal silicide layer 22 is generally tungsten silicide (tungsten silicide, WSi) material, and the control grid 20 that constitutes of metal silicide layer 22 and polycrystalline silicon material can be considered the word line of separated grid electrode type quick flashing storage 10.Since word line separated grid electrode type quick flashing storage 10 write, erase and reading speed on played the part of quite crucial role, yet the metal silicide layer 22 with the said method made but has very important sheet resistor (sheet resistance) problem, therefore known technology has also proposed modification method at the sheet resistor problem, for example after forming stacking structure 28, carry out suitable thermal process and change silicon atom and the distribution of tungsten atom in structure, to reach the purpose that reduces sheet resistor.
Therefore, according to known method, after forming stacking structure 28, a thermal process can be carried out so that the surface oxidation of stacking structure 28 and form oxide layer 26.Yet as shown in Figure 2, unsuitable thermal process can inwardly be eaten up part metals silicide layer 22, and makes the sidewall of stacking structure 28 produce the abnormal oxidation situation, for example causes the oxide layer 26 of metal silicide layer 22 sidewall surfaces to have bigger thickness.In the case, if the thickness of metal silicide layer 22 is too thick, perhaps the integrated level of memory cell is bigger, that is depth-width ratio (aspect ratio) is when big, the oxide layer 26 that then may cause thermal process to produce is too thick and have irregularly shaped, make 28 of adjacent stacking structures produce hole (void), cause the material in the subsequent technique can't effectively insert the zone of 28 of stacking structures, and take place aqueous vapor to infiltrate in the hole and influence the trustworthiness of separated grid electrode type quick flashing storage 10.In addition, can make the adherence of metal silicide layer 22 lower after the thermal process, produce the doubt that word line is peeled off (peel off).
From the above, though known technology attempts improving with thermal process the problem of word line sheet resistor, yet unsuitable thermal process but can cause causing word line to be peeled off and problem such as the rapid increase of sheet resistor and reliability be low as hole, metal silicide layer 22 oxidations or nitrogenize, just can find suitable thermal process parameter to reach the purpose of improvement memory quality so must spend the suitable time, very uneconomical.Therefore as how simple method produce flash memory with low sheet resistor, also can avoid above-mentioned because of other problems that thermal process produced, to improve the integrated operation usefulness and the trustworthiness of separated grid electrode type quick flashing storage, the still important issue that needs to be resolved hurrily for industry.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacture method of utilizing the silicon protective layer with the flash memory that improves storage operation usefulness.
According to claim of the present invention, provide a kind of method of making flash memory, the semiconductor substrate at first is provided, form a floating grid dielectric layer, a floating grid material layer, a dielectric layer, control gate material layers, a metal silicide layer and a hard mask layer in semiconductor-based basal surface in regular turn then, patterning hard mask layer makes hard mask layer have a control gate pattern again.Then remove part metals silicide layer, control gate material layers, dielectric layer and the floating grid material layer of the hard mask layer covering that is not patterned; stack structure to form one; on the semiconductor-based end, form a silicon protective layer then; a thermal process is carried out on covering stacking structure surface at last again.
According to claim of the present invention, other provides a kind of method of making flash memory.The semiconductor substrate at first is provided, form a floating grid dielectric layer, a floating grid material layer, a dielectric layer, control gate material layers, a metal silicide layer and a hard mask layer in semiconductor-based basal surface in regular turn then, patterning hard mask layer makes it have a control gate pattern again.Then remove the part metals silicide layer and control gate material layers of the hard mask layer covering that is not patterned,, make the control gate material layers form one and control grid until exposing dielectric layer.On the semiconductor-based end, form a silicon protective layer then, cover metal silicide layer and the sidewall surfaces of controlling grid, carry out a thermal process again.
Because the present invention is the sidewall surfaces elder generation formation silicon protective layer at metal silicide layer; carry out thermal process again and make the oxidation of silicon protective layer form oxide layer; can effectively protect the structure of metal tungsten silicide layer; avoid the metal silication tungsten layer in subsequent technique, to suffer erosion or damage and have influence on the operation usefulness of memory; and avoid metal silication tungsten layer abnormal oxidation, in thermal process, improve silicon/tungsten distribution proportion and word line sheet resistor problem simultaneously.
Description of drawings
Fig. 1 to Fig. 2 is the process schematic representation of known making separated grid electrode type quick flashing storage;
Fig. 3 to Fig. 8 makes the process schematic representation of first embodiment of flash memory method for the present invention;
Fig. 9 to Figure 14 makes the process schematic representation of second embodiment of flash memory method for the present invention.
The main element symbol description
The 12 semiconductor-based ends of 10 flash memories
14 oxide layers, 16 floating grids
18 dielectric layers, 20 polysilicon layers
22 metal silicide layers, 24 hard mask layers
26 oxide layers, 28 stacking structures
The 52 semiconductor-based ends of 50 flash memories
54 floating grid dielectric layers, 56 floating grid material layers
58 dielectric layer 58a, 58c oxide layer
62 metal silicide layers, 64 hard mask layers
66,88 silicon protective layers, 68,92,93,95 oxide layers
70 anisotropic etching process 72 gate dielectric of erasing
74 word line dielectric layers, 76 source electrodes
The 78 grid 80 word line grids of erasing
82,90,91 stacking structures, 84 floating grids
86 control grids, 87 control gate patterns
Embodiment
Please refer to Fig. 3 to Fig. 8, Fig. 3 to Fig. 8 makes the process schematic representation of first embodiment of the method for a flash memory 50 for the present invention.Flash memory 50 of the present invention is to be a separated grid electrode type quick flashing storage.At first, as shown in Figure 3, provide semiconductor substrate 52, it can be silicon base.Carry out an oxidation technology then, form an oxide layer in surface, the semiconductor-based ends 52, as floating grid dielectric layer 54.Then, form a floating grid material layer 56, a dielectric layer 58, control gate material layers 60, a metal silicide layer 62 and a hard mask layer 64 in regular turn in surface, the semiconductor-based ends 52, wherein floating grid material layer 56 preferably comprises polysilicon material layer with control gate material layers 60, metal silicide layer 62 can comprise the tungsten silicide material, hard mask layer 64 can comprise silicon nitride material, and dielectric layer 58 preferably comprises silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, ONO) dielectric material.In addition, before formation dielectric layer 58, can carry out a photoetching and etch process define floating grid to remove part floating grid material layer 56 part pattern (figure does not show) earlier.
Then, please refer to Fig. 4, patterning hard mask layer 64, be used as etching mask with hard mask layer 64 then, remove part metals silicide layer 62, control gate material layers 60, dielectric layer 58 and the floating grid material layer 56 of hard mask layer 64 coverings that are not patterned, to form stacking structure 82, remaining floating grid material layer 56 then forms floating grid 84 and control grid 86 respectively with control gate material layers 60.
Please refer to Fig. 5; form a silicon protective layer 66 in surface, the semiconductor-based ends 52; compliance ground covers stacking structure 82 and floating grid dielectric layer 54; it is made mode and comprises boiler tube deposition, chemical vapour deposition (CVD) or epitaxy method; it is preferred wherein to form silicon protective layer 66 with boiler tube deposition process and chemical gaseous phase depositing process, and its technological temperature is below 600 ℃.Silicon protective layer 66 can comprise extension, polycrystalline silicon material or amorphous silicon material.Then as shown in Figure 6, under 900 to 1050 ℃ technological temperature, carry out a thermal process, with the electrical quality of adjustment metal silicide layer 62, and then the sheet resistor of reduction word line.In this thermal process, silicon protective layer 66 is also oxidized and form an oxide layer 68.
Then, please refer to Fig. 7, carry out an anisotropic etching process 70, remove and be positioned at lip-deep residual silicon protective layers 66 of floating grid dielectric layer 54 and oxide layers 68, electrically connect between the adjacent stacking structure 82 avoiding.Please refer to Fig. 8, can form erase gate dielectric 72, source electrode 76, word line dielectric layer 74 and erase grid 78 and word line grid 80 in surface, the semiconductor-based ends 52 afterwards, just finish the making of the main element of flash memory 50.
Fig. 9 to Figure 12 makes the process schematic representation of second embodiment of flash memory method for the present invention, and for ease of explanation, Fig. 9 to 11 is subelement symbols of continuing to use Fig. 3 to Fig. 8, with the expression components identical.Please refer to Fig. 9, wherein Fig. 9 is the technology of hookup 3, make floating grid material layer 56, dielectric layer 58, control gate material layers 60, metal silicide layer 62 and hard mask layer 64 in regular turn on surface, the semiconductor-based ends 52, wherein dielectric layer 58 is the ONO dielectric layer, comprises silicon oxide layer 58a, silicon nitride layer 58b and silicon oxide layer 58c from the bottom to top in regular turn.Then as shown in Figure 9, carry out a photoetching and etch process, make it have at least one control gate pattern 87 with patterning hard mask layer 64.Then, utilize patterning hard mask layer 64 to be used as etching mask, and be used as etching stopping layer, metal silicide layer 62 and control gate material layers 60 are carried out an etch process, until exposing silicon oxide layer 58c with layer oxide layer 58c on the dielectric layer 58.
Please refer to Figure 10, form a silicon protective layer 88 comprehensively, overlay pattern hard mask layer 64, metal silicide layer 62 and control grid 86 surfaces, surface on the capping oxidation silicon layer 58c simultaneously in surface, the semiconductor-based ends 52.The formation method of silicon protective layer 88 comprises boiler tube deposition, chemical vapour deposition (CVD) or epitaxial growth technology, so the material of silicon protective layer 88 can comprise extension, polycrystalline silicon material or amorphous silicon material.Then as shown in figure 11, carry out a thermal process, with the silicon atom of change metal silicide layer 62 inside and the distribution proportion of tungsten atom; reduce the sheet resistor of metal silicide layer 62 or word line; in addition, in this thermal process, silicon protective layer 88 also can oxidation form an oxide layer 92.Then as shown in figure 12, carry out an anisotropic etching process, remove and be not patterned the part dielectric layer 58 and floating grid material layer 56 that hard mask layer 64 covers, to form stacking structure 90.Above-mentioned etch process also can remove partial oxidation layer 9 and patterning hard mask layer 64, and remaining floating grid material layer 56 promptly forms floating grid 84 in stacking structure 90.Afterwards, can continue on the semiconductor-based end 52, to make the elements such as contact plunger of floating grid dielectric layer, word line dielectric layer, the grid of erasing, word line grid and each electronic component correspondence, its component structure is not given unnecessary details at this similar in appearance to the described person of first embodiment of the invention.
It should be noted that; in the second embodiment of the present invention; also can be after forming silicon protective layer 88; carry out anisotropic etching process earlier and define floating grid 84; carry out the quality that thermal process is adjusted metal silicide layer 62 again, and the silicon protective layer 88 that oxidation is left is to form an oxide layer 92.As shown in figure 13, after finishing formation silicon protective layer 88 technologies of Figure 10, carry out an anisotropic etching process, remove and be not patterned the part dielectric layer 58 and floating grid material layer 56 that hard mask layer 64 covers, to form stacking structure 91.Above-mentioned etch process also can remove part silicon protective layer 88 and patterning hard mask layer 64, and remaining floating grid material layer 56 promptly forms floating grid 84 in stacking structure 91.Then as shown in figure 14, carry out a thermal process, to reduce the remaining silicon protective layer 88 of word line sheet resistor and oxidation to form an oxide layer 93, the sidewall at floating grid 84 also forms a thin oxide layer 95 simultaneously.
According to a second embodiment of the present invention; be before the pattern that defines floating grid 84; earlier at the sidewall surfaces formation silicon protective layer 88 of control grid 86 with the metal silicide layer 62 of patterning; treat after the thermal process; just etching defines floating grid 84, the floating grid 84 that forms after its advantage comprises have bigger critical dimension (critical dimension, CD); and then the coupling value of raising floating grid 84 and word line (control grid 86) (coupling ratio, CR).In addition, floating grid dielectric layer 54 is not exposed in the thermal process, so the method for present embodiment can be kept the better quality of floating grid dielectric layer 54.
Compared to known technology; the method that the present invention makes flash memory is to form one deck thin silicon protective layer earlier in the sidewall surfaces of controlling grid and metal silicide layer; carry out the electrical quality that thermal process is improved metal silicide layer again; therefore thermal process can't the attack metal silicide layer; can protect metal silicide layer to suffer damage in as technologies such as ashing or wet etchings follow-up; can guarantee that flash memory of the present invention has the uniform word line structure of size, and avoid abnormal oxidation phenomenon and the thing followed hole and the moisture issue of metal silicide layer in the known technology.From the above, the invention provides with simple process and produce structure and quality is good, and have the method for the flash memory of high reliability.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (21)
1. method of making flash memory, it comprises:
The semiconductor substrate is provided;
Form a floating grid dielectric layer, a floating grid material layer, a dielectric layer, control gate material layers, a metal silicide layer and a hard mask layer at this semiconductor-based basal surface in regular turn;
This hard mask layer of patterning makes this hard mask layer have a control gate pattern;
Remove this metal silicide layer of part, this control gate material layers, this dielectric layer and this floating grid material layer of this hard mask layer covering that is not patterned, stack structure to form one;
On this semiconductor-based end, form a silicon protective layer, cover this stacking structure surface; And
Carry out a thermal process.
2. method as claimed in claim 1, the method that wherein forms this silicon protective layer comprises a boiler tube depositing operation, a chemical vapor deposition method or an epitaxial growth technology.
3. method as claimed in claim 2, wherein the temperature of this boiler tube depositing operation and this chemical vapor deposition method is less than 600 ℃.
4. method as claimed in claim 1, wherein this silicon protective layer comprises polysilicon or amorphous silicon material.
5. method as claimed in claim 1, it is included in addition and carries out after this thermal process, removes to cover this residual on this floating grid dielectric layer surface silicon protective layer.
6. method as claimed in claim 5, the method that wherein removes this residual silicon protective layer comprises an anisotropic etching process.
7. method as claimed in claim 1, it comprises the following step in addition:
Part surface at this semiconductor-based end forms one source pole, is located at a side of this stacking structure;
On this semiconductor-based end of these stacking structure both sides, form erase a gate dielectric and a word line gate dielectric respectively; And
On erasing gate dielectric and this word line gate dielectric, this forms erase a grid and a word line grid respectively.
8. method as claimed in claim 1, wherein this control gate material layers and this floating grid material layer comprise polycrystalline silicon material respectively.
9. method as claimed in claim 1, wherein this metal silicide layer comprises the tungsten silicide material.
10. method as claimed in claim 1, wherein this thermal process is the sheet resistor that is used for reducing this metal silicide layer, and this silicon protective layer of oxidation is to form an oxide layer.
11. a method of making flash memory, it comprises:
The semiconductor substrate is provided;
Form a floating grid dielectric layer, a floating grid material layer, a dielectric layer, control gate material layers, a metal silicide layer and a hard mask layer at this semiconductor-based basal surface in regular turn;
This hard mask layer of patterning makes this hard mask layer have a control gate pattern;
Remove this metal silicide layer of part and this control gate material layers of this hard mask layer covering that is not patterned, until exposing this dielectric layer, so that should the control gate material layers form a control grid;
On this semiconductor-based end, form a silicon protective layer, cover the sidewall surfaces of this metal silicide layer and this control grid; And
Carry out a thermal process.
12. method as claim 11, other is included in and carries out after this thermal process, carry out an anisotropic etching process, to remove this dielectric layer and this floating grid material layer of this hard mask layer covering that is not patterned, so that this floating grid material layer forms a floating grid.
13. as the method for claim 11, the method that wherein forms this silicon protective layer comprises a boiler tube depositing operation, a chemical vapor deposition method or an epitaxy method.
14. as the method for claim 13, wherein the temperature of this boiler tube depositing operation and this chemical vapor deposition method is less than 600 ℃.
15. as the method for claim 11, wherein this dielectric layer is to be stacked up and down by one silica layer, a silicon nitride and silicon monoxide to constitute.
16. method as claim 15, wherein remove this metal silicide layer of part of this hard mask layer covering that is not patterned and the step of this control gate material layers and comprise an etch process, and this etch process is to be used as an etching stopping layer with a layer silicon oxide layer on this dielectric layer.
17. as the method for claim 11, wherein this silicon protective layer comprises polysilicon or amorphous silicon material.
18. as the method for claim 11, wherein this control gate material layers and this floating grid material layer comprise polycrystalline silicon material respectively.
19. as the method for claim 11, wherein this metal silicide layer comprises the tungsten silicide material.
20. as the method for claim 11, wherein this thermal process is the sheet resistor that is used for reducing this metal silicide layer, and this silicon protective layer of oxidation is to form an oxide layer.
21. method as claim 11, other is included in and carries out before this thermal process, carry out an anisotropic etching process, to remove this dielectric layer and this floating grid material layer of this hard mask layer covering that is not patterned, so that this floating grid material layer forms a floating grid.
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| CNA2007101531614A CN101399205A (en) | 2007-09-28 | 2007-09-28 | Method for making flash memory |
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| CNA2007101531614A CN101399205A (en) | 2007-09-28 | 2007-09-28 | Method for making flash memory |
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| CN102931239A (en) * | 2011-08-10 | 2013-02-13 | 无锡华润上华科技有限公司 | Semiconductor device and manufacturing method thereof |
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| CN104752359A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Memory device and forming method thereof |
| CN104752359B (en) * | 2013-12-30 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | memory device and forming method thereof |
| CN105206611A (en) * | 2014-06-16 | 2015-12-30 | 中芯国际集成电路制造(上海)有限公司 | Flash device and preparation method thereof |
| CN105206611B (en) * | 2014-06-16 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of Flash devices and preparation method thereof |
| CN104465664A (en) * | 2014-12-30 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and manufacturing method thereof |
| CN107533172A (en) * | 2015-04-03 | 2018-01-02 | 莫克斯泰克公司 | The oxidation of wire-grid polarizers and moisture barrier layer |
| CN107533172B (en) * | 2015-04-03 | 2020-08-14 | 莫克斯泰克公司 | Oxidation and moisture barrier layers for wire grid polarizers |
| CN107102394A (en) * | 2017-07-03 | 2017-08-29 | 京东方科技集团股份有限公司 | A kind of wire-grid polarizer, its preparation method and display panel |
| CN113192838A (en) * | 2021-03-24 | 2021-07-30 | 上海华虹宏力半导体制造有限公司 | Method for forming flash memory |
| CN113192838B (en) * | 2021-03-24 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Flash memory forming method |
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