JP2007049000A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent lowering in reliability and manufacturing yield such as short-circuiting or disturbing caused by processing shape defect of a floating gate electrode. <P>SOLUTION: A side wall spacer 8 formed in a side wall of an auxiliary gate 4 is constituted of a so-called high temperature oxide film (HTO film) which is deposited at a high temperature of about 800°C using dichlorosilane as a raw material to be a film denser than a silicon oxide film 6 constituting part of a cap insulating film. After deposition, it is further subjected to sintering at a high temperature of a deposition temperature or higher. Processing (double cutting) of a control gate and a floating gate is carried out by anisotropic dry etching and wet etching. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and more particularly, to a nonvolatile semiconductor memory device in which a memory cell is configured by a floating gate electrode for charge storage, a control gate electrode, and an auxiliary gate electrode, and a manufacturing method thereof. It is related to effective technology.

  2. Description of the Related Art As an electrically rewritable nonvolatile memory, a flash memory including a charge storage floating gate electrode (hereinafter referred to as a floating gate) and a control gate electrode (hereinafter referred to as a control gate) is known. In addition, as one type of flash memory, an auxiliary gate electrode (hereinafter referred to as an auxiliary gate) is further provided in the memory array, so that an AG ( Assist gate) -AND type flash memory is known.

  The AG-AND flash memory is disclosed in, for example, Japanese Patent Application Laid-Open No. 2005-85903 (Patent Document 1). In the memory array of the flash memory described in this document, a plurality of auxiliary gates extending in one direction are arranged adjacent to each other. In addition, a plurality of control gates extending in a direction perpendicular to the extending direction of the auxiliary gates are arranged adjacent to each other above the auxiliary gates to form a word line. Furthermore, a floating gate for storing electric charge is disposed in each space region of the plurality of auxiliary gates in a state of being electrically separated from the auxiliary gate and the control gate.

  When the miniaturization of the AG-AND flash memory progresses, the coupling ratio represented by the ratio of the capacitance between the floating gate and the control gate to the total capacitance around the floating gate decreases, It becomes difficult to operate the memory cell at high speed. As a countermeasure, the flash memory described in the above document attempts to increase the coupling ratio by making the height of the floating gate larger than the height of the auxiliary gate.

  In the AG-AND flash memory described in the above document, the floating gate having a height higher than that of the auxiliary gate is generally formed by the following method.

  First, a first polycrystalline silicon film for an auxiliary gate is deposited on a silicon substrate, and then a cap insulating film is deposited on top of the first polycrystalline silicon film. Since the height of the floating gate is defined by the thickness of the auxiliary gate (first polycrystalline silicon film) and the thickness of the cap insulating film, the cap insulating film is formed with a large thickness. The cap insulating film is composed of a silicon nitride film functioning as an etching stopper and a thick first silicon oxide film deposited thereon.

  Next, the cap insulating film and the first polycrystalline silicon film are patterned by dry etching using the photoresist film as a mask to form an auxiliary gate covered with a thick cap insulating film. Through the steps so far, a plurality of auxiliary gates extending in one direction are arranged adjacent to each other in the memory array region of the silicon substrate.

  Next, sidewall spacers are formed on the sidewalls of the auxiliary gate and the cap insulating film. The sidewall spacer is an insulating film for electrically separating the auxiliary gate and the floating gate. In order to form the sidewall spacer, after depositing a second silicon oxide film on the silicon substrate, the second silicon oxide film is anisotropically etched and left on the side walls of the auxiliary gate and the cap insulating film. The second silicon oxide film is deposited with a film thickness equal to or less than half the space width of the auxiliary gate.

  When the anisotropic etching is performed, an etching damage layer containing carbon or the like generated during etching is formed on the surface of the silicon substrate in the space region of the auxiliary gate. Therefore, next, dry etching with low damage is performed to remove the etching damage layer, and further, wet etching is performed to clean the surface of the silicon substrate, and then the silicon substrate is heat-treated to form thin silicon oxide on the surface. A film is formed.

  Next, by depositing the second polycrystalline silicon film for the floating gate on the silicon substrate, the space region of the auxiliary gate is filled with the second polycrystalline silicon film, and then the height of the surface is the cap insulating film. The surface of the second polycrystalline silicon film is etched back until it becomes slightly lower than the surface height.

  Next, a part of the cap insulating film (first silicon oxide film) covering the auxiliary gate and the sidewall spacer (second silicon oxide film) on the side wall are removed by dry etching. This etching is performed using the other part of the cap insulating film (silicon nitride film) as an etching stopper, and the etching is stopped when the surface of the silicon nitride film is exposed. Through the steps so far, the second polycrystalline silicon film having a height higher than that of the auxiliary gate remains in the space region of each of the plurality of auxiliary gates extending in one direction in the memory array region.

  Next, after forming a thin insulating film (ONO film) made of a silicon oxide film, a silicon nitride film, and a silicon oxide film on the silicon substrate, a first conductor film for a control gate is deposited on the ONO film. The first conductor film is composed of, for example, a polycrystalline silicon film and a tungsten silicide film deposited thereon.

Next, by patterning the first conductor film and the underlying ONO film and second polycrystalline silicon film by dry etching using the photoresist film as a mask, a control gate (word line) made of the first conductor film is formed. Form. Through the steps so far, a plurality of control gates extending in a direction orthogonal to the extending direction of the auxiliary gates are arranged adjacent to each other in the memory array region of the silicon substrate. Further, by this dry etching, the second polycrystalline silicon film extending in the same direction as the auxiliary gate is separated for each memory cell to form a floating gate.
JP 2005-85903 A

  The method for manufacturing a floating gate described in the above document has the following problems. This will be described with reference to FIGS.

  In order to form the floating gate, first, as shown in FIG. 25, the p-type well 2 is formed on the semiconductor substrate 1 made of single crystal silicon, and then the gate oxide film 3 is formed on the surface of the p-type well 2. . Next, after depositing an n-type polycrystalline silicon film and a cap insulating film 35 on the gate oxide film 3, the cap insulating film and the n-type polycrystalline silicon film are patterned by dry etching using a photoresist film as a mask. Thus, an auxiliary gate 34 made of an n-type polycrystalline silicon film is formed. The cap insulating film 35 is composed of, for example, a laminated film of a silicon nitride film and a first silicon oxide film deposited thereon. Next, a second silicon oxide film 38a is deposited on the semiconductor substrate 1 by a CVD method. Here, the second silicon oxide film 38a is deposited by a CVD (Chemical Vapor Deposition) method using a liquid source TEOS (TetraEthOxySilane) as a raw material. This is because the CVD method using TEOS as a raw material has the advantage that (1) the film formation rate is relatively high, so that the processing time of the process can be shortened, and (2) the loading effect that the film formation rate varies depending on the exposed area ratio. This is because it is suitable for forming a film uniformly in a narrow space region of the auxiliary gates 34, 34.

  Next, as shown in FIG. 26, sidewall spacers 38 are formed on the side walls of the auxiliary gate 34 and the cap insulating film 35 by anisotropically etching the second silicon oxide film 38 a. Here, a relatively high pressure (about 30 Pa) etching condition is employed to form the sidewall spacer 38.

  When the anisotropic etching is performed, the surface of the p-type well 2 is scraped in the space region of the auxiliary gates 34 and 34. Therefore, the surface of the p-type well 2 is cleaned by wet etching, and then the substrate 1 is heat-treated. As a result, a silicon oxide film 39 is formed on the surface of the p-type well 2.

  Next, as shown in FIG. 27, after depositing an n-type polycrystalline silicon film 40n on the substrate 1 by using the CVD method, the surface of the n-type polycrystalline silicon film 40n is etched back to thereby change the surface. The cap insulating film 35 is made to recede slightly below the surface. The n-type polycrystalline silicon film 40n is a conductor film that becomes a floating gate in a later process.

  Next, as shown in FIG. 28, a part of the cap insulating film 35 (first silicon oxide film) is removed by dry etching. This dry etching is performed using the silicon nitride film which is the remaining part of the cap insulating film 35 as an etching stopper. When the first silicon oxide film is dry-etched, the side wall spacers 38 above the exposed upper surface of the silicon nitride film are also removed, so that the upper surface of the silicon nitride film and the upper surface of the side wall spacer 38 have substantially the same height. . Through the steps so far, the n-type polycrystalline silicon film 40n that is higher than the auxiliary gate 34 and extends in the same direction as the auxiliary gate 34 is formed in a self-aligned manner with respect to the auxiliary gate 34 and the sidewall spacer 38. .

  Next, as shown in FIG. 29, after an ONO film 41 is formed on the substrate 1, an n-type polycrystalline silicon film 42 n, a tungsten silicide film 42 m, and a silicon oxide film 43 are sequentially deposited on the ONO film 41. The ONO film 41 is composed of three layers of insulating films (silicon oxide film, silicon nitride film, and silicon oxide film) deposited by the CVD method. The n-type polycrystalline silicon film 42n and the tungsten silicide film 42m are conductor films that will become control gates (word lines) in a later process.

  Next, by patterning the silicon oxide film 43, the tungsten silicide film 42m, and the n-type polycrystalline silicon film 42n, the control gate 42 (word line WL) is formed as shown in FIG. Next, the ONO film 41 and the n-type polycrystalline silicon film 40n in the space region of the control gates 42 and 42 are patterned to thereby form a strip-shaped n-type polycrystalline silicon film 40n extending in the same direction as the auxiliary gate 34. Are separated for each memory cell, and the floating gate 40 is formed in a self-aligned manner with respect to the control gate 42 (word line WL).

  As described above, in the conventional manufacturing method, when the sidewall spacer 38 made of the second silicon oxide film 38a is formed on the side wall of the auxiliary gate 34, the second silicon oxide film 38a is formed by the CVD method using TEOS as a raw material. Is deposited. Further, when forming the sidewall spacers 38 by anisotropically etching the second silicon oxide film 38a, etching conditions of relatively high pressure (about 30 Pa) are employed.

  However, since the second silicon oxide film (TEOS film) 38a deposited by the CVD method using TEOS as a raw material has low film density, the shape of the sidewall spacer 38 is formed by anisotropic etching and subsequent wet etching processes. Variations are likely to occur. Further, when the second silicon oxide film 38a is anisotropically etched under a relatively high pressure condition, a so-called microloading effect occurs in a narrow space region of the auxiliary gates 34 and 34, and a portion where etching proceeds and a portion where it is difficult to proceed. As a result, shape variations are likely to occur.

  As described above, it has been clarified by the present inventors that the conventional manufacturing method has a problem that the processed shape of the side wall spacer formed on the side wall of the auxiliary gate is likely to be uneven.

  As described above, the floating gate of the AG-AND flash memory is formed in a self-aligned manner with respect to the auxiliary gate and the sidewall spacer. Therefore, when the processed shape of the side wall spacer serving as the base of the floating gate is uneven, the polycrystalline silicon film for the floating gate filled in the space region of the auxiliary gate also follows the processed shape of the side wall spacer. It becomes a shape. As a result, in the process of etching the polycrystalline silicon film to form the floating gate, the portion of the polycrystalline silicon film that is behind the side wall spacer is difficult to be etched. Causes a short circuit without being separated.

  In addition, if the polycrystalline silicon film in the shadow of the side wall spacer becomes difficult to etch, the planar shape of the floating gate has sharp four corners that are difficult to etch even if the short circuit between adjacent floating gates does not occur. It becomes an irregular shape that protrudes (see FIG. 30). If the floating gate has such a shape, a problem of “disturb phenomenon” that unintentionally changes the threshold voltage of the surrounding memory cell when the rewrite operation of a predetermined memory cell is repeatedly performed is likely to occur. It is possible.

That is, as shown in FIG. 31, if the four corners of the floating gate (FG ₀ ) of the selected memory cell (MC ₀ ) are sharp, electric field concentration occurs at the location during the erase operation, so that electrons have high energy. It is emitted to the silicon substrate in the state of holding. The electrons emitted to the silicon substrate generate secondary electrons in the substrate, and the generated electrons enter the silicon oxide film on the substrate surface again. Then, secondary electrons having entered in the silicon oxide film, the selected memory cell (MC ₀₎ by the erase field is away from the selected memory cell (MC _0), adjacent memory cells _(MC 1, MC ₂₎ particularly facing In an erase state with a low threshold voltage, it is injected into the floating gates (FG ₁ , FG ₂ ) of the adjacent memory cells (MC ₁ , MC ₂ ). As described above, when the four corners of the floating gate (FG ₀ ) of the selected memory cell (MC ₀ ) are pointed, it is originally changed by secondary electrons generated by electrons having high energy that are emitted during erasing. This causes a disturb phenomenon in which the threshold voltages of adjacent memory cells (MC ₁ , MC ₂ ) that are not desired also increase.

FIG. 32 is a graph showing changes in the threshold voltage of adjacent memory cells (MC ₁ , MC ₂ ) that have undergone the disturb phenomenon.

  The word line selected at the time of rewriting is different each time, but as one case, there is a possibility that a specific word line is continuously selected and rewritten. When considering such an extreme case, the threshold voltage of the memory cell adjacent to the selected memory cell having the floating gate with the four corners gradually increases due to the disturb phenomenon, and finally exceeds the predetermined voltage range. This leads to erroneous writing of stored information. This is a disturb phenomenon to adjacent memory cells.

  In the future, if the memory cell size is further miniaturized and the memory cell interval becomes narrower, such a problem may become more prominent. Further, there is a problem that it is difficult to determine the shape defect of the floating gate that causes the disturb phenomenon in the pattern defect inspection process in the wafer process. Therefore, in the manufacturing process of the AG-AND type flash memory, it is required not to cause a shape defect of the floating gate, that is, not to have a shape with four sharp corners.

  An object of the present invention is to provide a technique for preventing a decrease in reliability and manufacturing yield in a nonvolatile memory element such as an AG-AND type flash memory.

  Another object of the present invention is to suppress the disturb phenomenon in the nonvolatile memory element.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A manufacturing method of a semiconductor integrated circuit device according to the present invention includes the following steps.
(A) forming a cap insulating film having a thickness greater than that of the first conductor film on the first conductor film after forming the first conductor film on the main surface of the semiconductor substrate;
(B) By patterning the cap insulating film and the first conductor film, a plurality of first conductor pieces that are covered with the cap insulating film and extend in the first direction with a predetermined space are formed. The process of
(C) A high temperature oxide film is formed on the main surface of the semiconductor substrate using a CVD method using dichlorosilane as a raw material, and then the high temperature oxide film is anisotropically etched to thereby form a plurality of the first conductors. Forming a sidewall spacer made of the high-temperature oxide film on each side wall of the piece and the cap insulating film;
(D) a step of forming a silicon oxide film by high-temperature thermal oxidation treatment in the space region of the first conductor piece after cleaning the main surface of the semiconductor substrate;
(E) forming a second conductor film on a main surface of the semiconductor substrate and filling the second conductor film in each space region of the first conductor piece covered with the cap insulating film;
(F) A step of etching back the second conductor film to such an extent that the cap insulating film is exposed and the second conductor film remains in the space region of the first conductor piece by anisotropic etching. ,
(G) after the step (f), forming a first insulating film on the main surface of the semiconductor substrate and forming a third conductor film on the first insulating film;
(H) A second direction that is made of the third conductor film by patterning the third conductor film, the first insulating film, and the second conductor film, and intersects the first direction with a predetermined space. Forming a plurality of third conductor pieces extending in length and forming a second conductor piece made of the second conductor film in a lower region of each of the third conductor pieces.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a nonvolatile memory element such as an AG-AND type flash memory, it is possible to prevent a decrease in reliability and manufacturing yield.

  In addition, the disturb phenomenon in the nonvolatile memory element can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  In the present embodiment, the present invention is applied to an AG-AND type flash memory having a capacity of 4 Gbit (gigabit), for example.

  FIG. 1 is a circuit diagram showing a memory array of an AND type flash memory according to the present embodiment, FIG. 2 is a plan view of a principal part showing a simplified configuration of the memory array, and FIG. 3 is a line AA in FIG. FIG.

  The AND-type flash memory is located between a plurality of auxiliary gates 4 extending in the Y direction of the memory array, a plurality of control gates 12 extending in the X direction orthogonal thereto, and auxiliary gates 4 and 4 adjacent to each other. In addition, a floating gate 10 is provided as a charge storage film formed in a state of being insulated from the auxiliary gate 4 and the control gate 12. Although there is no particular limitation, the auxiliary gates 4 are connected to a common wiring (not shown), for example, with four gates as a unit, and an inversion layer serving as a write operation and a local bit line is formed according to circumstances. Used for. That is, when a predetermined voltage is applied to the auxiliary gate 4, an n-type inversion layer functioning as a source or drain of the memory cell is formed on the semiconductor substrate 1 (p-type well 2) below the auxiliary gate 4. Since the inversion layer extends in the Y direction of the memory array along the auxiliary gate 4, it is used as a local bit line. As a result, the memory cell size can be reduced as compared with the case where the diffusion layers for the source and drain are formed in the p-type well 2 in advance or the wiring for the local bit line is formed in the upper layer of the memory cell. it can. The auxiliary gate 4 also has an isolation function between adjacent memory cells. This eliminates the need for an isolation region in the memory array, thereby further reducing the memory cell size. For example, 256 control gates 12 form a word line WL and are formed for one block of memory cells.

  As shown in FIG. 3, the auxiliary gate 4 is formed on the gate insulating film (gate oxide film) 3 on the surface of the p-type well 2. The auxiliary gate 4 is made of, for example, an n-type polycrystalline silicon film as a conductor film, and, for example, a silicon nitride film 5 is formed thereon as an insulating film constituting a cap insulating film of the auxiliary gate 4. Sidewall spacers 8 made of an insulating film such as a silicon oxide film are formed on the side walls of the auxiliary gate 4 and the silicon nitride film 5. As will be described later, the AND type flash memory according to the present embodiment forms the sidewall spacer 8 with a silicon oxide film having high density.

  The charge accumulation floating gate 10 is disposed in the space region of the auxiliary gates 4 and 4 adjacent to each other, and is formed on the silicon oxide film 9 on the surface of the p-type well 2. The silicon oxide film 9 is a film that functions as a tunnel insulating film of the memory cell, and information is written by injecting electrons from the surface of the p-type well 2 to the floating gate 10 through the silicon oxide film 9. Is called. Further, information is erased by emitting electrons from the floating gate 10 to the p-type well 2 through the silicon oxide film 9. The floating gate 10 is insulated from the auxiliary gate 4 via an insulating film (silicon oxide film) 7 formed on the side wall of the auxiliary gate 4 and a sidewall spacer 8.

  The floating gate 10 and the control gate 12 (word line WL) thereabove are insulated from each other via the ONO film 11. The ONO film 11 includes a two-layer silicon oxide film and a silicon nitride film formed therebetween. The control gate 12 (word line WL) includes an n-type polycrystalline silicon film doped with, for example, P or As as a conductor film, and a refractory metal film such as a tungsten silicide (WSi) film as a conductor film thereon. It consists of a deposited polycide film.

  The floating gate 10 is formed such that the height from the surface of the p-type well 2 is higher than that of the auxiliary gate 4. As a result, even if the memory cell is miniaturized, the facing area between the floating gate 10 and the control gate 12 can be increased, so that a reduction in the coupling ratio is suppressed and the memory cell can be operated at high speed. Become.

  23 and 24 are circuit diagrams showing voltage application conditions when information is rewritten in a predetermined selected memory cell. The AG-AND type flash memory can rewrite information in the memory cell in units of word lines.

  When erasing data in a predetermined memory cell, a predetermined erase voltage is first applied to the selected word line SW and each auxiliary gate AGn (n = 0 to 3) as shown in FIG. Are emitted to the substrate (FN (Fowlor Nordheim) tunnel emission). As a result, the threshold voltages of all the memory cells MC connected to the selected word line SW are set to an erased state equal to or lower than a predetermined value.

  When writing data to a predetermined memory cell, as shown in FIG. 24, first, 8V is applied to the selection gate AG2, and 5V is applied to the selection gate AG0. At the same time, a voltage lower than the voltage applied to the selection gates AG0 and AG2 is applied to the selection gate AG1 adjacent to the selected memory cell to be written. In this state, an inversion layer is formed on the surface of the semiconductor substrate under select gates AG0 and AG2. At this time, the inversion layer under the selection gate AG2 is electrically connected to the bit line GBL1, and a potential of about 4.5V is applied. The inversion layer under the selection gate AG0 is electrically connected to the bit line GBL0, and a ground potential such as 0V is applied. Thereby, a current flows from the inversion layer on the bit line GBL1 side to the inversion layer on the bit line GBL0 side, but the channel of the selected memory cell to be written and the weak inversion layer formed below the selection gate AG1 adjacent thereto. The electric field concentration occurs between the first and second electrodes, and hot electrons are generated on the surface of the semiconductor substrate by the electric field concentration. The hot electrons are injected into the floating gate of the selected memory cell by the electric field generated by the high potential (15 V in this case) of the selected word line SW. The The selected memory cell is in a state where the threshold voltage is high and data is written by injecting electrons into the floating gate.

  Next, the manufacturing method of the AND type flash memory according to the present embodiment will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 4, boron (B) is ion-implanted into a semiconductor substrate (hereinafter referred to as a substrate) 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm. 2 is formed. Subsequently, the substrate 1 is thermally oxidized to form a gate oxide film 3 having a thickness of about 7 to 9 nm on the surface of the p-type well 2.

  Next, as shown in FIG. 5, after depositing an n-type polycrystalline silicon film 4n doped with phosphorus (P) or arsenic (As) on the gate oxide film 3 by using a CVD method, an n-type polycrystalline silicon film is then deposited. A silicon nitride film 5 and a silicon oxide film 6 are deposited on the silicon film 4n as a cap insulating film by a CVD method. The thickness of the n-type polycrystalline silicon film 4n is about 70 nm. Further, in order to sufficiently increase the height of the floating gate 10 formed in a later step, the cap insulating film (the silicon nitride film 5 and the silicon oxide film 6) has a thickness of at least that of the n-type polycrystalline silicon film 4n. It is larger than the film thickness, and more preferably at least twice that of the n-type polycrystalline silicon film 4n. Here, the thickness of the silicon nitride film 5 is about 70 nm, and the thickness of the silicon oxide film 6 is about 250 nm. As described above, since the silicon oxide film 6 needs to be thickened, the silicon oxide film 6 is deposited by a CVD method having a high film formation rate, for example, a normal pressure to low pressure CVD method using a liquid source TEOS (TetraEthOxySilane) as a raw material. .

  Next, as shown in FIGS. 6 and 7 (cross-sectional views taken along line AA in FIG. 6), the silicon oxide film 6, the silicon nitride film 5, and the n-type multi-layer are formed by dry etching using a photoresist film as a mask. By patterning the crystalline silicon film 4n, the auxiliary gate 4 made of the n-type polycrystalline silicon film 4n is formed.

  Next, as shown in FIG. 8, a thin silicon oxide film 7 having a thickness of about 10 nm is formed on the side wall of the processed auxiliary gate 4 (n-type polycrystalline silicon film 4n) by thermal oxidation. The silicon oxide film 7 on the side wall of the auxiliary gate 4 is formed in order to improve the withstand voltage between the auxiliary gate 4 and the floating gate 10 formed in a later process. When this thermal oxidation is performed, a silicon oxide film 7 is also formed on the surface of the p-type well 2 between the auxiliary gates 4 and 4.

  Next, as shown in FIG. 9, a silicon oxide film 8a having a thickness of about 40 nm is deposited on the substrate 1 by the CVD method. This silicon oxide film 8a is a so-called high-temperature oxide film deposited at a high temperature of about 800 ° C. using dichlorosilane as a raw material so as to be denser than the silicon oxide film 6 constituting a part of the cap insulating film. (HTO film), and after film formation, baking is performed at a temperature higher than the film formation temperature.

  Next, as shown in FIGS. 10 and 11 (cross-sectional view taken along the line AA in FIG. 10), the silicon oxide film 8a is anisotropically etched to thereby form the auxiliary gate 4 and the cap insulating film (silicon nitride). Sidewall spacers 8 are formed on the respective side walls of the film 5 and the silicon oxide film 6).

  Since the silicon oxide film 8a (high temperature oxide film) constituting the sidewall spacer 8 is denser than the silicon oxide film (TEOS film) deposited by the CVD method using TEOS as a raw material, the anisotropic etching speed is increased. Is smaller than the TEOS film. In particular, in the narrow space region of the auxiliary gates 4 and 4 where the side wall spacers 8 are formed, the etching rate is likely to decrease significantly due to the microloading effect of dry etching. In consideration of the density of elements in the plane of the substrate 1, there is a difference in the etching rate between the central region and the peripheral region of the memory array. Further, there are slight variations in the dimensions of the auxiliary gate 4, the film thickness of the silicon oxide film 8a, the space width of the auxiliary gates 4 and 4, and the like.

  For this reason, when the sidewall spacer 8 is formed by anisotropically etching the silicon oxide film 8a made of a high temperature oxide film, the thickness of the sidewall spacer 8 tends to vary. As a countermeasure, in this embodiment, the silicon oxide film 8a is etched in a state where the pressure in the chamber of the dry etching apparatus is lowered to 10 Pa or less, preferably about 5 Pa. Thereby, since the variation in the film thickness of the sidewall spacer 8 due to the various factors described above can be reduced, the forward tapered sidewall spacer 8 having no irregularities on the surface can be formed.

  When the above-described anisotropic etching is performed, the silicon oxide film 7 on the surface of the p-type well 2 is removed in the space region of the auxiliary gates 4 and 4, so that the exposed surface of the p-type well 2 is generated during etching. An etching damage layer containing carbon or the like is generated. Therefore, next, dry etching with low damage is performed to remove the etching damage layer, and wet etching is performed to clean the surface of the p-type well 2. A silicon oxide film 9 having a thickness of about 7 to 10 nm is formed on the surface. When the silicon oxide film 9 is formed, the substrate 1 may be heat-treated in a nitrogen atmosphere. Thereby, nitrogen is segregated at the interface between the silicon oxide film 9 and the p-type well 2p, and the film quality of the silicon oxide film 9 functioning as a tunnel oxide film of the memory cell is improved, so that the charge retention characteristics of the memory cell are improved. .

  Next, as shown in FIG. 12, an n-type polycrystalline silicon film 10n doped with phosphorus or arsenic is deposited on the substrate 1 using a CVD method, and then the surface of the n-type polycrystalline silicon film 10n is deposited. By etching back, the surface is made to recede slightly below the surface of the silicon oxide film 6 (cap insulating film). The surface step between the n-type polycrystalline silicon film 10n and the silicon oxide film 6 is preferably within about 30 nm. The n-type polycrystalline silicon film 10n is a conductor film that becomes the floating gate 10 in a later process.

  Next, as shown in FIG. 13, the silicon oxide film 6 which is a part of the cap insulating film is removed by dry etching. This dry etching is performed using the silicon nitride film 5 which is the remaining part of the cap insulating film as an etching stopper. When the silicon oxide film 6 is dry-etched, the sidewall spacers 8 above the exposed upper surface of the silicon nitride film 5 are also removed, so that the upper surface of the silicon nitride film 5 and the upper surface of the sidewall spacer 8 are approximately the same height. Become. Through the steps so far, a strip-shaped n-type polycrystalline silicon film 10 n that is higher than the auxiliary gate 4 and extends in the same direction as the auxiliary gate 4 is formed in a self-aligned manner with respect to the auxiliary gate 4 and the sidewall spacer 8. Is done. Further, the n-type polycrystalline silicon film 10n is deposited on the forward-tapered sidewall spacer 8 having no irregularities on the surface, so that the surface of the n-type polycrystalline silicon film 10n also has an irregular shape.

  Next, as shown in FIG. 14, an ONO film 11 is formed on the substrate 1. The ONO film 11 is composed of three layers of insulating films (silicon oxide film, silicon nitride film, and silicon oxide film) deposited by the CVD method. The two layers of silicon oxide films sandwiching the silicon nitride film may be formed by a thermal oxidation method instead of the CVD method.

  Next, as shown in FIG. 15, an n-type polycrystalline silicon film 12n doped with phosphorus or arsenic, a tungsten silicide film 12m, and a silicon oxide film 13 are sequentially deposited on the ONO film 11 using the CVD method. The film thickness of the n-type polycrystalline silicon film 12n above the n-type polycrystalline silicon film 10n is about 80 nm, and the film thicknesses of the tungsten silicide film 12m and the silicon oxide film 13 are each about 150 nm.

  Next, as shown in FIGS. 16 and 17 (cross-sectional view taken along line BB in FIG. 16), the silicon oxide film 13 is patterned by dry etching using a photoresist film as a mask. Subsequently, after removing the photoresist film, the tungsten silicide film 12m and the n-type polycrystalline silicon film 12n are patterned using the silicon oxide film 13 as a mask material. Through the steps so far, the control gate 12 (word line WL) made of the tungsten silicide film 12m and the n-type polycrystalline silicon film 12n is formed.

  Next, as shown in FIG. 18, FIG. 19 (cross-sectional view along the line BB in FIG. 18) and FIG. 20 (cross-sectional view along the line CC in FIG. 18), the control gate 12 (word line) Using the silicon oxide film 13 covering (WL) as a mask, the ONO film 11 and the n-type polycrystalline silicon film 10n in the space region of the control gates 12 and 12 are dry-etched. Subsequently, in order to remove the remaining film of the n-type polycrystalline silicon film 10n that cannot be removed only by this dry etching, a wet etching process is performed using a heated APM (ammonia + hydrogen peroxide) cleaning solution or hydrofluoric acid. . That is, patterning of the word line WL and the floating gate 10 is performed using dry etching and wet etching. Through the steps so far, the band-shaped n-type polycrystalline silicon film 10n extending in the same direction as the auxiliary gate 4 is separated for each memory cell and is self-aligned with respect to the control gate 12 (word line WL). A floating gate 10 is formed.

Next, thermal oxidation is performed on the main surface of the semiconductor substrate by a high-temperature rapid heating process using a gas containing oxygen (O ₂ ). By performing this thermal oxidation treatment, the exposed semiconductor substrate, the side surface of the floating gate 10 and the side surface of the control gate 12 are oxidized to form an oxide film of about several nm (not shown). The main purpose of this thermal oxidation treatment is to suppress electric field concentration at the gate end of the floating gate 10. Further, it is an object of the present invention to oxidize and completely remove the remaining film of the n-type polycrystalline silicon film 10n which cannot be removed even by the dry etching process or the wet etching process by this thermal oxidation.

  The thermal oxidation treatment may be performed by an ISSG (In-Situ Steam Generation) oxidation method. The ISSG oxidation method is a method in which hydrogen and oxygen are directly introduced into a reduced-pressure heat treatment chamber and a radical oxidation reaction is performed in an atmosphere at about 1000 ° C.

  As described above, according to the manufacturing method of the present embodiment, the sidewall spacer 8 has a forward tapered shape with no irregularities on the surface. As a result, when the n-type polycrystalline silicon film 10n is dry-etched to form the floating gate 10, the n-type polycrystalline silicon film 10n is etched in the shaded portion of the sidewall spacer 8 as in the prior art. There is no problem of being left behind. In other words, according to the manufacturing method of the present embodiment, when the floating gate 10 is formed by dry etching the n-type polycrystalline silicon film 10n, the floating gates 10 and 10 are caused by the shape defect of the sidewall spacer 8. It is possible to reliably prevent a short circuit without being separated.

  Further, as described above, according to the manufacturing method of the present embodiment, the n-type polycrystalline silicon film 10n is deposited on the forward-tapered sidewall spacer 8 having no irregularities on the surface, so that the n-type polycrystalline is obtained. The surface of the silicon film 10n also has a shape without unevenness. As a result, after the n-type polycrystalline silicon film 10n is dry-etched to form the floating gate 10, a wet etching process is performed using an APM solution. The remaining film remaining on the side surface of the spacer 8 in a thin skin state is also removed satisfactorily. Therefore, as shown in FIG. 21, the floating gate 10 has a planar shape in which the length of the portion in contact with the sidewall spacer 8 (length in the extending direction of the auxiliary gate 4) b is the same as the length a of the central portion. The rectangular shape is smaller (b ≦ a) than that.

  On the other hand, FIG. 22 shows a planar shape of the floating gate 10 that can occur when the sidewall spacer formed on the side wall of the auxiliary gate is formed of a TEOS film. As described above, when the silicon oxide film deposited by the CVD method using TEOS as a raw material is anisotropically etched under a relatively high pressure etching condition, the processed shape of the sidewall spacer tends to be uneven. Therefore, the floating gate 10 formed in a self-aligned manner with respect to the auxiliary gate and the side wall spacer has a rugged shape in which the four corners are sharp and protruded. That is, the planar shape of the floating gate 10 is such that the length of the portion in contact with the sidewall spacer (length in the extending direction of the auxiliary gate) b ′ is larger than the length a of the central portion (b ′> a). Become. When the floating gate 10 has such a shape, the electric field concentrates at the four corners of the floating gate 10 during the erase operation, and electrons are emitted to the substrate with high energy. Secondary electrons are generated. When the secondary electrons are injected into the floating gate of the adjacent memory cell, a disturb phenomenon occurs in which the threshold voltage of the adjacent memory cell increases undesirably. On the other hand, the floating gate 10 according to the present embodiment does not have a shape in which the four corners are sharp and project the corners, so that the above-described disturb phenomenon can be suppressed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, multi-value information can be stored in the memory cell MC. Since this multi-value storage is performed by changing the amount of electrons injected into the floating gate 4 by changing the write time by keeping the write voltage of the selected word line SW constant, a memory having several kinds of threshold levels. A cell MC can be formed. That is, four or more values such as “00” / “01” / “10” / “11” can be stored. Thereby, since one memory cell MC functions as two memory cells, it is possible to reduce the size of the flash memory.

  In the above embodiment, the present invention is applied to an AG-AND type flash memory having a floating gate having a height higher than that of the auxiliary gate. However, the present invention is not limited to this. That is, according to the present invention, the first conductor film is patterned when the second conductor film for the control gate is patterned after the space region of the auxiliary gate having the sidewall spacer formed on the side wall is filled with the first conductor film. In general, the present invention can be applied to an AG-AND type flash memory in which a floating gate is formed.

  The present invention is effective when applied to a semiconductor integrated circuit device in which a flash memory is composed of a floating gate electrode for charge storage, a control gate electrode, and an auxiliary gate electrode.

1 is a circuit diagram showing a memory array of an AND type flash memory according to an embodiment of the present invention. FIG. 1 is a plan view of a principal part showing a simplified configuration of an AND type flash memory according to an embodiment of the present invention; It is sectional drawing along the AA line of FIG. It is principal part sectional drawing which shows the manufacturing method of the AND type flash memory which is one embodiment of this invention. FIG. 5 is a fragmentary cross-sectional view showing the manufacturing method of the AND flash memory following FIG. 4. FIG. 6 is a plan view of relevant parts showing a method for manufacturing an AND type flash memory following FIG. 5. It is sectional drawing along the AA line of FIG. FIG. 7 is an essential part cross-sectional view showing the manufacturing method of the AND type flash memory following FIG. 6; FIG. 9 is a fragmentary cross-sectional view showing the manufacturing method of the AND flash memory following FIG. 8. FIG. 10 is a plan view of relevant parts showing a method for manufacturing an AND type flash memory following FIG. 9; It is sectional drawing along the AA line of FIG. FIG. 11 is a fragmentary cross-sectional view showing the manufacturing method of the AND type flash memory following FIG. 10. 13 is a fragmentary cross-sectional view showing the manufacturing method of the AND flash memory following FIG. 12. FIG. FIG. 14 is a fragmentary cross-sectional view showing the manufacturing method of the AND type flash memory following FIG. 13; FIG. 15 is a fragmentary cross-sectional view showing the manufacturing method of the AND flash memory following FIG. 14. FIG. 16 is a plan view of relevant parts showing a method for manufacturing an AND type flash memory following FIG. 15; It is sectional drawing along the BB line of FIG. FIG. 17 is a plan view of relevant parts showing a method for manufacturing an AND type flash memory following FIG. 16; It is sectional drawing along the BB line of FIG. It is sectional drawing along CC line of FIG. It is a figure which shows the planar shape of the floating gate obtained by the manufacturing method of this Embodiment. It is a figure which shows the planar shape of the floating gate obtained by the conventional manufacturing method. FIG. 5 is a circuit diagram showing an erase operation of an AND type flash memory according to an embodiment of the present invention. FIG. 5 is a circuit diagram showing a write operation of an AND type flash memory according to an embodiment of the present invention. It is principal part sectional drawing which shows the manufacturing method of the AND type flash memory of a prior art example. FIG. 26 is a fragmentary cross-sectional view showing the manufacturing method of the AND flash memory following FIG. 25. FIG. 27 is an essential part cross-sectional view showing a manufacturing method of the AND type flash memory following FIG. 26; FIG. 27 is a sectional view of the substantial part showing the production method of the subsequent AND type flash memory. FIG. 29 is a fragmentary cross-sectional view showing the manufacturing method of the AND flash memory following FIG. 28. FIG. 30 is a plan view of relevant parts showing a method for manufacturing an AND type flash memory following FIG. 29; FIG. 6 is a plan view showing a selected memory cell and a memory cell adjacent to the selected memory cell during an erasing operation. 5 is a graph showing a change in threshold voltage of an adjacent memory cell that has undergone a disturb phenomenon.

Explanation of symbols

1 semiconductor substrate 2 p-type well 3 gate insulating film (gate oxide film)
4 Auxiliary gate 4n n-type polycrystalline silicon film 5 silicon nitride film 6 silicon oxide film 7 insulating film (silicon oxide film)
8a Silicon oxide film 8 Side wall spacer 9 Silicon oxide film 10 Floating gate 10n n-type polycrystalline silicon film 11 ONO film 12 control gate 12n n-type polycrystalline silicon film 12m tungsten silicide film 13 silicon oxide film 34 auxiliary gate 35 cap insulating film 38a Second silicon oxide film 38 Side wall spacer 39 Silicon oxide film 40 Floating gate 40n n-type polycrystalline silicon film 41 ONO film 42 control gate 42n n-type polycrystalline silicon film 42m tungsten silicide film 43 silicon oxide film AGn auxiliary gate WL word line

Claims (25)

Manufacturing method of semiconductor integrated circuit device having the following steps:
(A) forming a cap insulating film having a thickness greater than that of the first conductor film on the first conductor film after forming the first conductor film on the main surface of the semiconductor substrate;
(B) patterning the cap insulating film and the first conductor film to form a first conductor piece whose upper part is covered with the cap insulating film;
(C) After forming a high temperature oxide film on the main surface of the semiconductor substrate using a CVD method using dichlorosilane as a raw material, the high temperature oxide film is anisotropically etched, whereby the first conductor piece and Forming a side wall spacer made of the high temperature oxide film on each side wall of the cap insulating film;   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the thickness of the cap insulating film is twice or more the thickness of the first conductor film.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the dense density of the high temperature oxide film is larger than the dense density of the cap insulating film.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the anisotropic etching of the high-temperature oxide film is performed under a pressure condition of 10 Pa or less.   5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the anisotropic etching of the high temperature oxide film is performed under a pressure condition of 5 Pa or less. Manufacturing method of semiconductor integrated circuit device having the following steps:
(A) After forming the first conductor film on the main surface of the semiconductor substrate, the first conductor film is formed of a laminated film of a first insulating film and a second insulating film, and is more than the first conductor film. Forming a cap insulating film having a thick film thickness;
(B) patterning the cap insulating film and the first conductor film to form a first conductor piece whose upper part is covered with the cap insulating film;
(C) After forming a high temperature oxide film on the main surface of the semiconductor substrate using a CVD method using dichlorosilane as a raw material, the high temperature oxide film is anisotropically etched, whereby the first conductor piece and Forming a side wall spacer made of the high temperature oxide film on each side wall of the cap insulating film; Manufacturing method of semiconductor integrated circuit device having the following steps:
(A) forming a cap insulating film having a thickness greater than that of the first conductor film on the first conductor film after forming the first conductor film on the main surface of the semiconductor substrate;
(B) By patterning the cap insulating film and the first conductor film, a plurality of first conductor pieces that are covered with the cap insulating film and extend in the first direction with a predetermined space are formed. The process of
(C) A high temperature oxide film is formed on the main surface of the semiconductor substrate using a CVD method using dichlorosilane as a raw material, and then the high temperature oxide film is anisotropically etched to thereby form a plurality of the first conductors. Forming a sidewall spacer made of the high-temperature oxide film on each side wall of the piece and the cap insulating film;
(D) a step of forming a silicon oxide film by high-temperature thermal oxidation treatment in the space region of the first conductor piece after cleaning the main surface of the semiconductor substrate;
(E) forming a second conductor film on a main surface of the semiconductor substrate and filling the second conductor film in each space region of the first conductor piece covered with the cap insulating film;
(F) Etching back the second conductor film to such an extent that the cap insulating film is exposed and the second conductor film remains in a space region of the first conductor piece by anisotropic etching;
(G) after the step (f), forming a first insulating film on the main surface of the semiconductor substrate and forming a third conductor film on the first insulating film;
(H) A second direction that is made of the third conductor film by patterning the third conductor film, the first insulating film, and the second conductor film, and intersects the first direction with a predetermined space. Forming a plurality of third conductor pieces extending in length and forming a second conductor piece made of the second conductor film in a lower region of each of the third conductor pieces.   8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the dense density of the high temperature oxide film is larger than the dense density of the cap insulating film.   8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the anisotropic etching of the high temperature oxide film is performed under a pressure condition of 10 Pa or less.   10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the anisotropic etching of the high temperature oxide film is performed under a pressure condition of 5 Pa or less.   8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the patterning of the second conductor film in the step (h) is performed by a combination of dry etching and wet etching using hydrofluoric acid or an APM cleaning solution. Method. After the step (h), a step of forming a silicon oxide film on a side surface of the patterned second conductor film by a high-temperature rapid heating thermal oxidation method;
The method of manufacturing a semiconductor integrated circuit device according to claim 7, further comprising:   8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein a planar dimension of the second conductor piece along the first direction is larger in a central portion than in a region in contact with the sidewall spacer. .   The first conductor piece constitutes an auxiliary gate electrode of the nonvolatile memory, the second conductor piece constitutes a charge accumulation floating gate electrode of the nonvolatile memory, and the third conductor piece constitutes the nonvolatile memory. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the control gate electrode of the memory is configured. Manufacturing method of semiconductor integrated circuit device having the following steps:
(A) a step of sequentially forming a first conductor film, a first insulating film, and a second conductor film on the main surface of the semiconductor substrate;
(B) patterning the second conductor film, the first insulating film, and the first conductor film into a predetermined shape by dry etching;
(C) A step of performing wet etching on the second conductor film and the first conductor film after the step (b).   16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the wet etching is performed using fluorinated nitric acid or an APM cleaning solution.   16. The semiconductor integrated circuit according to claim 15, wherein an etching amount of the first conductor film in a direction horizontal to the main surface of the semiconductor substrate is larger than an etching amount of the second conductor film in the direction. Device manufacturing method.   18. The method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein the wet etching is performed using an APM cleaning solution. Prior to step (a),
(D) forming a third conductor film on the main surface of the semiconductor substrate and forming a cap insulating film on the third conductor film;
(E) patterning the cap insulating film and the third conductor film to form a conductor piece whose upper part is covered with the cap insulating film;
(F) forming a second insulating film on the main surface of the semiconductor substrate, and then anisotropically etching the second insulating film to form sidewall spacers on the side walls of the conductor piece and the cap insulating film; Forming a process,
16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, further comprising:   The said conductor piece is not patterned when patterning the said 2nd conductor film, the said 1st insulating film, and the said 1st conductor film in the said process (b) to a defined shape, The pattern is characterized by the above-mentioned. 19. A method for manufacturing a semiconductor integrated circuit device according to 19.   The first conductor film constitutes a floating gate electrode for charge storage of a nonvolatile memory, the second conductor film constitutes a control gate electrode of the nonvolatile memory, and the conductor piece is formed of the nonvolatile memory. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein the auxiliary gate electrode is formed.   20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein the second insulating film is formed by a CVD method using dichlorosilane as a raw material. After the step (c),
(G) a step of forming a silicon oxide film on a side surface of the patterned first conductor film by a high-temperature rapid heating thermal oxidation method;
20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, further comprising: A semiconductor substrate having a main surface;
A plurality of auxiliary gate electrodes, the upper part of which is covered with a cap insulating film and extending in the first direction of the main surface with a predetermined space;
A sidewall spacer made of a silicon oxide film formed on each side wall of the cap insulating film and the auxiliary gate electrode;
A plurality of control gate electrodes extending in a second direction intersecting the first direction with a predetermined space;
A semiconductor integrated circuit device having a plurality of charge storage floating gate electrodes formed in a region located below the control gate electrode in a space region of the auxiliary gate electrode,
The semiconductor integrated circuit device according to claim 1, wherein a planar dimension of the floating gate electrode along the first direction is larger in a central portion than in a region in contact with the sidewall spacer.   25. The semiconductor integrated circuit device according to claim 24, wherein the silicon oxide film constituting the sidewall spacer is a high-temperature oxide film formed by a CVD method using dichlorosilane as a raw material.

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