JP2007067223A - Semiconductor device and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability in a semiconductor device including a flash memory having an auxiliary gate electrode structure. <P>SOLUTION: The device includes: a plurality of auxiliary gate electrodes AG which are formed on the main surface of a semiconductor board 1 through a gate insulating film 2; floating gate electrodes FG which are formed to be insulated electrically from the auxiliary gate electrodes AG by side wall insulating films 4 formed on the side walls of the auxiliary gate electrodes AG, and are formed through the gate insulating films 2; and a plurality of control gate electrodes CG which are formed on inter-layer dielectrics 5 formed to cover the floating gate electrodes FG. The surface of the interlayer dielectrics 5 has irregular shape. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a flash memory having an auxiliary gate electrode configuration and a technique effective when applied to the manufacturing technique.

  The AND type flash memory is a memory of various portable devices such as portable personal computers, digital still cameras, portable music players, digital video cameras, PDAs (Personal Digital Assistants), cellular phones, etc., information devices or communication devices. Used as a medium.

  Non-Patent Document 1 discloses a technique related to an AND flash memory having an assist gate electrode (AG).

Non-Patent Document 2 discloses a technique related to the surface state of a polycrystalline silicon electrode of a DRAM (Dynamic Random Access Memory).
Y. Sasago, et al .; “90-nm-node multi-level AG-AND type flash memory with cell size of true 2F2 / bit and programming throughput of 10MB / s”; 2003 IEEE M.Yoshimaru, et al .; “RUGGED SURFACE POLY-Si ELECTRODE AND TEMPERATURE DEPOSITED Si3N4 FOR 64MBIT AND BEYOND STC DRAM CELL”; 1990IEEE

  The present inventors are conducting research and development of an AND type flash memory (hereinafter simply referred to as “flash memory”) having an assist gate electrode (AG). For example, a 1 Gb (gigabit) flash memory can be formed by adopting a 0.13 μm process. Note that the writing speed of the 1 Gb flash memory is, for example, about 10 Mb / s.

  Further, a larger capacity 4 Gb flash memory can be formed by a 90 nm process which has been miniaturized. Here, a 4 Gb flash memory formed by the 90 nm process investigated by the present inventors will be described with reference to FIGS. FIG. 14 is a plan view of an essential part schematically showing the memory cell region M2 of the flash memory examined by the present inventors. FIGS. 15A and 15B are cross-sectional views taken along lines X1-X1 and Y1-Y1 in FIG. 14, respectively. 14 indicates the extending direction of the local data line in the first direction, and X indicates the extending direction of the word line WL in the second direction orthogonal to the first direction.

  On the semiconductor substrate 1 in the memory cell region M2 of the flash memory, a plurality of auxiliary gate electrodes AG extending in the Y direction are arranged adjacent to each other. A cap insulating film 3 made of, for example, silicon nitride is formed on each auxiliary gate electrode AG. In the upper layer of the plurality of auxiliary gate electrodes AG, a plurality of word lines WL extending in the X direction orthogonal to the extending direction of the auxiliary gate electrode AG are arranged adjacent to each other. The floating gate electrode FG is electrically isolated from other members between the word lines WL and the semiconductor substrate 1 between the adjacent auxiliary gate electrodes AG. Has been placed. Reference numeral 2 denotes a gate insulating film, reference numeral 4 denotes a sidewall insulating film, reference numeral 5 denotes an interlayer insulating film, and reference numerals 6, 7, and 8 denote insulating films.

  When the 4 Gb flash memory achieves the same writing speed as the 1 Gb flash memory (for example, about 10 Mb / s), the floating gate electrode FG has a height (thickness) of the upper surface of the auxiliary gate electrode AG. It is formed so as to be higher than the height (thickness). Note that the 4 Gb flash memory has a structure in which the height of the floating gate of the 1 Gb flash memory is about 50 to 70 nm, for example, and the height of the floating gate is about 300 nm, for example.

  However, the present inventor has found that the AND type flash memory having the auxiliary gate electrode has the following problems.

  The threshold voltage (Vth) of the memory cell fluctuates due to the parasitic capacitance between adjacent bits, and as a result, the information (“0” or “1”) stored in the memory cell is garbled (Vth It is a problem of blur. In particular, until the 0.13 μm process generation, since the space between adjacent bits is wide, the parasitic capacitance between adjacent bits is small and the problem has not been revealed. However, in the 90 nm process generation with advanced miniaturization, the threshold voltage fluctuates. This becomes a big problem. The problem is that in the 4 Gb flash memory, the floating gate electrode is higher than that in the 1 Gb flash memory, and because the distance between the adjacent floating gate electrodes is reduced by the 90 nm process of finer processing. It is considered that one of the factors is that the capacitance between the floating gate electrodes increases and the read operation failure (Vth blur) due to coupling between the floating gate electrodes increases.

  Here, the read operation failure due to the coupling between the floating gate electrodes is caused when the selected bit is read according to the write level of the floating gate electrode (non-selected bit) adjacent to the selected floating gate electrode (selected bit). That is, the threshold voltage changes. That is, the threshold voltage at the time of reading the selected bit changes due to the influence of the charge accumulated in the adjacent non-selected bits. This is affected by the capacitance between the selected bit and the floating gate electrode of the non-selected bit adjacent thereto.

  Therefore, it is considered that the read failure can be reduced by reducing the capacitance between the floating gate electrodes and reducing the influence of the charge of the adjacent floating gate electrodes. However, this reduction in the capacitance between the floating gate electrodes is caused by the coupling ratio between the capacitance of the insulating film formed on the floating gate electrode and the capacitance of the insulating film formed below the floating gate electrode, which affects the writing speed. There is a trade-off relationship for improvement.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device having a flash memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the semiconductor device according to the present invention, the surface shape of the interlayer insulating film formed on the floating gate electrode is uneven.

  In addition, the semiconductor device manufacturing method according to the present invention is such that the surface shape of a conductor layer that will later become a floating gate electrode is made uneven.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By making the surface shape of the interlayer insulating film formed on the floating gate electrode uneven and increasing the substantial surface area, the capacitance between adjacent floating gate electrodes can be reduced, so that the threshold voltage of the memory cell Variation can be suppressed or prevented. Therefore, the reliability of the semiconductor device having a flash memory can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  The semiconductor device of the present embodiment is, for example, a 4 Gb (Gigabit) AND type flash memory. FIG. 1 is a schematic main circuit diagram of the memory cell region M1 of the semiconductor device according to the embodiment of the present invention. The arrow Y indicates the first direction, and the arrow X orthogonal to the first direction Y indicates the second direction.

  In the memory cell region M1, a plurality of auxiliary gate lines (first gate electrodes) AGL extending in the first direction Y are arranged along the second direction X. In the memory cell region M1, a plurality of word lines WL extending in the second direction X are arranged side by side along the first direction Y. Further, in the memory cell region M1, nonvolatile memory cells (hereinafter referred to as memory cells) MC are arranged in the vicinity of the intersections of the plurality of auxiliary gate lines AGL and the plurality of word lines WL.

  Each memory cell MC is connected in parallel between adjacent local data lines BL (drain line DL and source line SL). However, the drain line DL and the source line SL are not formed on a semiconductor substrate (hereinafter referred to as a substrate) from the beginning, and a desired voltage is applied to the auxiliary gate wiring AGL when information is written or read. Thus, the inversion layer is formed in the substrate portion facing the auxiliary gate line AGL.

  Each memory cell MC has a memory MISFET Qm that contributes to information storage. The memory MISFET Qm has a floating gate electrode (second gate electrode) and a control gate electrode (third gate electrode). The floating gate electrode of the memory MISFET Qm is an electrode in which charges contributing to information storage are accumulated. The control gate electrode of the memory MISFET Qm is formed by a part of the word line WL. Each word line WL is electrically connected to control gate electrodes of a plurality of memory MISFETs Qm arranged along the second direction X. The width (short dimension, first dimension Y dimension) of the word line WL is, for example, 90 nm.

  Next, FIG. 2 is a plan view of the main part of the memory cell region M1 in FIG. 1, and FIGS. 3A and 3B are a sectional view taken along line X1-X1 and a sectional view taken along line Y1-Y1 in FIG. . In FIG. 2, some members are omitted for easy understanding of the drawing.

The memory cell region M1 of the flash memory according to the present embodiment is a so-called contactless type array having no contact hole for each memory cell MC. The substrate 1 is made of, for example, p-type silicon (Si) single crystal. The symbol DNW indicates an n-type buried region, and the symbol PWL indicates a p-well. The p well PWL is surrounded by the underlying n-type buried region DNW. On the main surface of the substrate 1, a band-like shape extending in the first direction Y in FIG. 2 via a gate insulating film 2 made of, for example, silicon oxide (SiO ₂ or the like, having a dielectric constant of 3.8, for example) A plurality of auxiliary gate lines AGL (auxiliary gate electrodes AG) are arranged side by side in the second direction X so as to be along each other. Each auxiliary gate line AGL is made of, for example, low-resistance polycrystalline silicon, and a cap insulating film 3 is formed on each upper surface thereof. The cap insulating film 3 is made of, for example, silicon nitride (Si ₃ N ₄ or the like, the dielectric constant is 7 to 8 for example), and the thickness thereof is, for example, about 50 nm. Further, side walls (side wall insulating films) 4 made of, for example, silicon oxide are formed on the side surfaces of each auxiliary gate wiring AGL and the cap insulating film 3.

  N-type semiconductor regions for the drain line DL and the source line SL are not formed on the substrate 1. By applying a desired voltage to the auxiliary gate line AGL during the write and read operations of the flash memory, an n-type inversion layer is formed on the main surface portion (p well PWL) of the substrate 1 facing the auxiliary gate line AGL. Thus, the drain line DL (drain region) and the source line SL (source region) are formed. That is, since the inversion layer is used as the local data line BL, a diffusion layer is not required in the memory array, and the data line pitch can be reduced. In addition, since the trench isolation part is not formed in the memory array, the area of the memory array can be reduced. Further, since the drain line DL and the source line SL of the adjacent memory cells MC are shared, the area occupied by the memory array can be reduced.

Above the auxiliary gate wiring AGL, a plurality of strip-like word lines WL extending in the second direction X of FIG. 2 through the cap insulating film 3 and the interlayer insulating film (interlayer insulating film) 5 They are arranged side by side in the first direction Y of FIG. 2 so as to be parallel to each other. The insulating film 5 is formed of, for example, a laminated film in which a silicon oxide film, a silicon nitride (Si ₃ N ₄ or the like) film, and a silicon oxide film are sequentially deposited from the lower layer. The surface shape of the insulating film 5 is uneven. As will be described later, the surface shape of the floating gate electrode FG is uneven, and a silicon oxide film by ISSG oxidation, a silicon nitride film by CVD, and a silicon oxide film by ISSG oxidation are deposited on the floating gate electrode FG. As a result, the surface shape of the insulating film 5 is uneven.

Each word line WL is formed of, for example, a laminated film of low-resistance polycrystalline silicon and tungsten silicide (WSi _x ) thereon, and a part of the word line WL serves as the control gate electrode CG. On each word line WL, an insulating film 6 made of, for example, silicon oxide is formed.

  The floating gate electrode FG of the memory MISFET Qm is located between the adjacent adjoining auxiliary gate lines AGL and in a position where the word lines WL overlap in a plane, that is, between the opposing surfaces of the control gate electrode CG and the substrate 1. It is formed in a state of being insulated from other portions. The floating gate electrode FG is made of, for example, low-resistance polycrystalline silicon, and is formed on the main surface of the substrate 1 via a gate insulating film 2 made of, for example, a silicon oxide film.

  The floating gate electrode FG is insulated and separated from the auxiliary gate wiring AGL by the sidewall 4 and from the word line WL by the insulating film 5. The floating gate electrode FG is formed so that the height from the main surface of the substrate 1 to the upper surface of the floating gate electrode FG is higher than the height from the main surface of the substrate 1 to the upper surface of the auxiliary gate wiring AGL. Yes. That is, the floating gate electrode FG is formed in a convex shape in cross section. An interval between adjacent floating gate electrodes FG along the second direction X is, for example, about 90 nm.

  Further, the surface shape of the floating gate electrode FG is uneven. As will be described later, the surface shape of the exposed floating gate electrode FG made of polycrystalline silicon is uneven by spraying high-concentration phosphorus on the main surface of the semiconductor substrate 1 and performing a heat treatment at about 560 ° C. to 570 ° C., for example. It is in the shape.

  On the main surface of the substrate 1, insulating films 7 and 8 made of, for example, silicon oxide are sequentially deposited from below. The insulating film 7 is buried between the word lines WL adjacent to each other in the first direction Y and between the floating gate electrodes FG adjacent to each other in the first direction Y. The adjacent word lines WL and the floating gate electrodes FG adjacent to each other in the first direction Y are insulated and separated.

  Here, for example, in the case of a configuration in which a floating gate electrode having a concave cross section is formed between adjacent auxiliary gate lines AGL as in a 1 Gb flash memory, when the memory cell MC is reduced, the adjacent interval between the auxiliary gate lines AGL. Therefore, the thickness of the conductor film for forming the floating gate electrode FG must be reduced, and the processing of the floating gate electrode FG becomes difficult. On the other hand, as shown in this embodiment mode, when the floating gate electrode FG has a convex cross section, the floating gate electrode FG can be easily processed even if the memory cell MC is reduced. Therefore, miniaturization of the memory cell MC can be promoted.

  Further, since the capacitance between the floating gate electrode FG and the control gate electrode CG is formed on the convex side wall surface and the convex upper surface of the floating gate electrode FG, even if the minimum processing size is further reduced, the capacitance of the floating gate electrode FG is reduced. By increasing the height, the facing area between the floating gate electrode FG and the control gate electrode CG can be increased. Further, the capacitance between adjacent floating gate electrodes FG can increase the effective surface area because the surface shape of the interlayer insulating film 5 formed on the floating gate electrode FG is uneven. That is, since the capacity can be increased without increasing the area occupied by the memory cell MC, the coupling ratio between the floating gate electrode FG and the control gate electrode CG and the coupling ratio between adjacent floating gate electrodes FG are improved. Can be made.

  Therefore, the controllability of the voltage control of the floating gate electrode FG by the control gate electrode CG can be improved, so that the writing and erasing speed of the flash memory can be improved even at a low voltage, and the operating voltage of the flash memory can be reduced. The voltage can be lowered. In addition, since the parasitic capacitance between adjacent memory cells MC (floating gate electrode FG) can be reduced, fluctuations in the threshold voltage of the memory cell MC (memory MISFET Qm) can be suppressed or prevented. Therefore, the reliability of the flash memory can be improved.

  Next, an example of the data read operation of the flash memory according to the present embodiment will be described with reference to FIGS.

  In the data read operation, for example, about 2 to 5 V is applied to the word line WL to which the control gate electrode of the memory MISFET Qm (Qm0) of the selected memory cell MC is connected, and the threshold value of the selected memory MISFET Qm (Qm0). Determine. Further, a negative voltage of, for example, about 0 V or −2 V is applied to the other word lines WL to turn off the unselected memory MISFET Qm.

  Further, by applying about 5 V, for example, to the auxiliary gate wiring AGL for forming the source and drain of the selected memory MISFET Qm (Qm0), the source line SL and the main surface portion of the substrate 1 facing the auxiliary gate wiring AGL are respectively applied. An n-type inversion layer for the drain line DL is formed. In addition, by applying 0 V to the other auxiliary gate lines AGL, for example, an inversion layer is not formed on the main surface portion of the substrate 1 opposed to the auxiliary gate lines AGL, so that the MISFET Qm (Qm0) for the selected memory is formed. And the MISFET Qm for non-selected memory are isolated.

In this state, for example, about 1 V is applied to the global data line to which the n-type inversion layer for the source line SL of the selected memory MISFET Qm (Qm0) is connected, while 0 V is applied to the other global data lines. To do. In this state, a voltage of about 0 V applied to the common drain wiring is supplied to the drain of the selected memory MISFET Qm (Qm0) through the n-type inversion layer for the drain line DL. By doing so, reading data of MISFETQm selection memory so as to flow a common drain read toward the wiring current I _R from the global data line (Qm0).

  At this time, the threshold voltage of the selected memory MISFET Qm (Qm0) changes depending on the state of the charge stored in the floating gate electrode FG. Therefore, the selected memory MISFET Qm (Qm0) is selected depending on the current flowing between the source and drain. Data of the memory MISFET Qm (Qm0) can be determined.

  According to the present embodiment, the parasitic capacitance between adjacent bits (memory cells MC) can be reduced by making the surface shape of the insulating film 5 over the floating gate electrode FG uneven, so that the memory cells MC ( It is possible to suppress or prevent fluctuations in the threshold voltage of the memory MISFET Qm). Therefore, the reliability of the flash memory can be improved.

  Next, an example of the data read operation of the flash memory according to the present embodiment will be described with reference to FIGS. Data writing is premised on a source side hot electron injection method by source side selection and constant charge injection. Thus, efficient data writing can be performed at high speed with low current.

  In the data write operation, for example, about 13V to 15V is applied to the word line WL to which the control gate electrode CG of the memory MISFETQm (Qm0) of the selected memory cell MC is connected, and for example, 0V is applied to the other word lines WL. .

  For example, about 2 V is applied to the auxiliary gate wiring AGL for forming the source of the selected memory MISFET Qm (Qm0), and about 7 V is applied to the auxiliary gate wiring AGL for forming the drain of the selected memory MISFET Qm (Qm0). As a result, an n-type inversion layer for forming a source is formed on the main surface portion of the substrate 1 facing the auxiliary gate wiring AGL, and n for forming a drain is formed on the main surface portion of the substrate 1 facing the auxiliary gate wiring AGL. A mold inversion layer is formed. For example, 0 V is applied to the other auxiliary gate lines AGL so that an inversion layer is not formed on the main surface portion of the substrate 1 facing the auxiliary gate lines AGL, and the selected memory MISFET Qm (Qm0) is not selected. Isolation with the memory MISFET Qm is performed.

  In this state, a voltage of about 4 V applied to the common drain wiring is supplied to the drain of the selected memory MISFET Qm (Qm0) through the n-type inversion layer for the drain line DL. Further, for example, 0 V is applied to the global data line to which the n-type inversion layer for the source line SL of the selected memory MISFET Qm (Qm0) is connected. Further, the p well PWL is held at 0V, for example.

At this time, current I _w of writing flows from the drain to the source in MISFETQm for selection memory (Qm0), the charge accumulated in the inversion layer of the n-type source side when the gate insulating as certain channel current The floating gate electrode FG is efficiently injected through the film 2 (constant charge injection method). As a result, data is written to the selected memory MISFET Qm (Qm0) at high speed. On the other hand, the drain current does not flow from the drain to the source of the unselected memory MISFET Qm so that data is not written.

  In addition, multi-value data can be stored in each memory cell MC (memory MISFET Qm). This multi-value storage is performed by changing the amount of hot electrons injected into the floating gate electrode FG by changing the write time by keeping the write voltage of the word line WL constant, for example. A memory cell MC having a level can be formed. That is, four or more values such as “00” / “01” / “10” / “11” can be stored. For this reason, the function for two memory cells MC can be realized by one memory cell MC. Therefore, it is possible to reduce the size of the flash memory.

  Next, an example of the data erasing operation of the flash memory according to the present embodiment will be described with reference to FIGS. In the data erasing operation, a negative voltage is applied to the word line WL to be selected, thereby performing FN (Fowler Nordheim) tunnel emission from the floating gate electrode FG to the substrate 1. That is, for example, about −16 V is applied to the word line WL to be selected, while a positive voltage is applied to the substrate 1. For example, 0 V is applied to the auxiliary gate wiring AGL, and no n-type inversion layer is formed. As a result, the charge for data stored in the floating gate electrode FG is discharged to the substrate 1 through the gate insulating film 2, and the data in the plurality of memory cells MC are erased collectively.

  Next, a method for manufacturing the flash memory according to the present embodiment will be described with reference to FIGS. 4A to 13B are sectional views of portions corresponding to the X1-X1 line and the Y1-Y1 line in FIG. 2, respectively.

  First, as shown in FIG. 4, a substrate 1 made of p-type silicon (Si) single crystal (planar substantially circular semiconductor plate called a semiconductor wafer at this stage) is prepared, and n-type embedded in this substrate 1. Region DNW and p well PWL are sequentially formed. Next, a gate insulating film 2 made of, for example, silicon oxide and having a thickness of about 10 nm is formed on the p-well PWL of the substrate 1 by a thermal oxidation method such as an ISSG (In-Situ Steam Generation) oxidation method.

  Subsequently, a conductor film (first conductor layer) 10 made of low resistance polycrystalline silicon doped with, for example, phosphorus (P) is deposited on the main surface of the substrate 1, and a cap insulation made of, for example, silicon nitride is deposited thereon. A film (first insulating film) 3 is deposited, and a dummy insulating film (second insulating film) 11 made of, for example, silicon oxide is further deposited thereon. The conductor film 10, the cap insulating film 3, and the dummy insulating film 11 are deposited by, for example, a CVD (Chemical Vapor Deposition) method.

  Subsequently, as shown in FIG. 5, the dummy insulating film 11, the cap insulating film 3, and the conductor film 10 are patterned by dry etching using an etching mask, thereby forming the auxiliary gate wiring AGL by the conductor film 10. . The dummy insulating film 11, the cap insulating film 3, and the auxiliary gate wiring AGL at this stage have a strip-like pattern extending in the first direction Y and are arranged in stripes.

  Subsequently, as shown in FIG. 6, the substrate 1 (semiconductor wafer) is subjected to a thermal oxidation process such as an ISSG oxidation method, and high-quality insulation made of, for example, silicon oxide on the side surfaces of the auxiliary gate wiring AGL and the like. After the film is formed, an insulating film 4A made of, for example, silicon oxide is deposited on the main surface of the substrate 1 by, for example, a CVD method using TEOS (Tetra Ethyl Ortho Silicate) gas. The insulating film 4A is deposited so as not to completely fill the adjacent portions of the stripe pattern formed by the dummy insulating film 11, the cap insulating film 3, and the auxiliary gate wiring AGL.

  Subsequently, as shown in FIG. 7, sidewalls (sidewall insulating films) 4 are formed on the side surfaces of the laminated pattern of the auxiliary gate wiring AGL, the cap insulating film 3 and the dummy insulating film 11 by etching back the insulating film 4A. To do. Next, on the main surface of the substrate 1 (semiconductor wafer), a floating gate electrode forming conductor film (second conductor layer) 12 made of, for example, low-resistance polycrystalline silicon, the dummy insulating film 11, the cap insulating film 3 and Deposition is performed by a CVD method or the like so that the adjacent portion of the stripe pattern formed by the auxiliary gate wiring AGL is completely filled.

  Subsequently, as shown in FIG. 8, the conductive film 12 on the main surface of the substrate 1 is subjected to an etch-back process by an anisotropic dry etching method or a CMP (Chemical Mechanical Polishing) process, whereby the dummy film is formed. A conductive pattern 12a (second conductive layer) for forming a floating gate electrode is formed between adjacent stripe patterns formed by the insulating film 11, the cap insulating film 3, and the auxiliary gate wiring AGL.

  Subsequently, as shown in FIG. 9, the dummy insulating film 11 and the sidewalls 4 are etched by a dry etching method or a wet etching method. At this time, the etching selectivity between silicon oxide, silicon, and silicon nitride is increased so that silicon oxide is easier to remove than silicon and silicon nitride. Thereby, the cap insulating film 3 made of silicon nitride is caused to function as an etching stopper. Further, all of the dummy insulating film 11 made of silicon oxide is removed, but the upper portion of the side wall 4 made of silicon oxide is removed and left on the side surface of the auxiliary gate wiring AGL.

  Subsequently, as shown in FIG. 10, high-concentration phosphorus is sprayed on the main surface of the substrate 1 (semiconductor wafer), and heat treatment is performed at, for example, about 560 ° C. to 570 ° C., thereby forming the exposed polycrystalline silicon. The surface shape of the conductor pattern 12a is made uneven. In other words, the uneven portion 12b is formed on the surface of the conductor pattern 12a.

  Subsequently, as shown in FIG. 11, an interlayer insulating film (interlayer insulating film) 5 for electrically insulating the floating gate electrode and the control gate electrode is formed on the main surface of the substrate 1 (semiconductor wafer). As the insulating film 5 for the interlayer film, for example, a laminated film (ONO (Oxide Nitride Oxide) film) of silicon oxide film / silicon nitride film / silicon oxide film can be used. These silicon oxide films are formed by, for example, the ISSG oxidation method, and the silicon nitride film is formed by, for example, the CVD method. Since the insulating film 5 is formed on the conductor pattern 12a having a concavo-convex surface, the surface shape of the insulating film 5 is also concavo-convex. In other words, the insulating film 5 made of a laminated film of silicon oxide film / silicon nitride film / silicon oxide film is formed with the seed (uneven portion) 12b made of polycrystalline silicon formed on the surface of the conductor pattern 12a as a nucleus, The surface shape of the insulating film 5 is uneven.

Subsequently, a conductor film (third conductor layer) 13 for forming a word line is deposited on the insulating film 5 in the main surface of the substrate 1 (semiconductor wafer). The conductor film 13 is formed by sequentially depositing, for example, a low resistance polycrystalline silicon film and a tungsten silicide film from the lower layer by the CVD method or the like. Next, an insulating film 6 made of, for example, silicon oxide is deposited on the conductor film 13 in the main surface of the substrate 1 (semiconductor wafer) by, for example, a CVD method using a mixed gas of ozone (O ₃ ) gas and TEOS gas. To do. Next, a cap film (masking layer) 15 made of, for example, polycrystalline silicon is deposited on the insulating film 6 in the main surface of the substrate 1 (semiconductor wafer) by a CVD method or the like.

  Subsequently, as shown in FIG. 12, a cap pattern 15a is formed from the cap film 15 by photolithography and etching. In the memory cell region, a plurality of cap patterns 15a for forming word lines are formed. The cap pattern 15a is a flat belt-like pattern extending in a direction perpendicular to the paper surface of FIG. A part of the surface of the insulating film 6 is exposed from between adjacent cap patterns 15a.

  Subsequently, as shown in FIG. 13, by using the cap pattern 15a as an etching mask, the insulating film 6 and the conductor film 13 exposed from the cap pattern 15a are removed by dry etching, thereby forming the word line WL made of the conductor film 13. To do. The cap pattern 15a is also removed when the conductor film 13 is removed by etching.

  Subsequently, using the remaining pattern of the insulating film 6 as an etching mask, the insulating film 5 and the conductor pattern 12a exposed therefrom are removed by a dry etching method. Thereby, a plurality of floating gate electrodes FG made of the conductor pattern 12a are formed in the memory region (the memory cell region M1 and the memory cell peripheral region).

  Subsequently, the insulating film 7 (see FIG. 3) is deposited on the main surface of the substrate 1 (semiconductor wafer) by a CVD method or the like. As a result, the insulating film 7 is buried between adjacent word lines WL, adjacent floating gate electrodes FG, adjacent auxiliary gate lines AGL, and the like. Subsequently, after the insulating film 8 (see FIG. 3) is deposited on the main surface of the substrate 1 (semiconductor wafer) by a CVD method or the like, the upper surface thereof is flattened by, for example, a CMP method or the like. Then, after depositing a metal film on the main surface of the substrate 1 (semiconductor wafer), this is patterned to form wiring. In this way, a flash memory having memory cells MC was manufactured (see FIG. 3).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the invention made mainly by the present inventor is applied to the flash memory manufacturing method which is the field of use behind the invention has been described. However, the present invention is not limited to this and can be applied in various ways. For example, the present invention can also be applied to a method for manufacturing a semiconductor device having a flash memory and a logic circuit such as a microprocessor on the same substrate.

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor devices.

FIG. 3 is a schematic main circuit diagram of a memory cell region of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view of a main part of a memory cell region in FIG. (A) And (b) is sectional drawing of the X1-X1 line | wire and Y1-Y1 line | wire of FIG. 2, respectively. It is principal part sectional drawing which shows typically the memory area | region of the semiconductor device in the manufacturing process of embodiment of this invention. FIG. 5 is a main part cross-sectional view schematically showing a memory region of the semiconductor device in the manufacturing process following FIG. 4; FIG. 6 is a fragmentary cross-sectional view schematically showing a memory region of the semiconductor device in the manufacturing process subsequent to FIG. 5; FIG. 7 is a main part sectional view schematically showing a memory region of the semiconductor device in the manufacturing process following FIG. 6; FIG. 8 is a fragmentary cross-sectional view schematically showing a memory region of the semiconductor device in the manufacturing process following FIG. 7. FIG. 9 is a main part cross-sectional view schematically showing the memory region of the semiconductor device in the manufacturing process following FIG. 8; FIG. 10 is a main part cross-sectional view schematically showing the memory region of the semiconductor device in the manufacturing process following FIG. 9; FIG. 11 is a main part cross-sectional view schematically showing the memory region of the semiconductor device in the manufacturing process following FIG. 10; FIG. 12 is a main part cross-sectional view schematically showing the memory region of the semiconductor device in the manufacturing process following FIG. 11; FIG. 13 is a fragmentary cross-sectional view schematically showing a memory region of the semiconductor device in the manufacturing process following FIG. 12. It is a principal part top view which shows typically the memory area of the flash memory which the present inventors examined. (A) And (b) is sectional drawing of the X1-X1 line | wire and Y1-Y1 line | wire of FIG. 14, respectively.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Cap insulating film (1st insulating film)
4 Side wall (side wall insulating film)
4A Insulating film 5 Insulating film (interlayer insulating film)
6, 7, 8 Insulating film 10 Conductor film (first conductor layer)
11 Dummy insulating film (second insulating film)
12 Conductor film (second conductor layer)
12a Conductor pattern 12b Uneven portion (seed)
13 Conductor film (third conductor layer)
15 Cap film 15a Cap pattern AG Auxiliary gate electrode (first gate electrode)
AGL Auxiliary gate line BL Local data line CG Control gate electrode (third gate electrode)
DL drain line DNW n-type buried region FG Floating gate electrode (second gate electrode)
M1, M2 Memory cell area MC Memory cell PWL p well Qm MISFET for memory
SL Source line WL Word line

Claims (5)

A semiconductor substrate;
A plurality of first gate electrodes formed on a main surface of the semiconductor substrate through a gate insulating film and extending in a first direction along the main surface of the semiconductor substrate;
A cap insulating film formed on the first gate electrode;
A sidewall insulating film formed on the sidewall of the first gate electrode;
Between the adjacent first gate electrodes, the sidewall insulating film is electrically insulated from the first gate electrode, and is formed on the main surface of the semiconductor substrate via the gate insulating film. A formed second gate electrode;
An interlayer insulating film formed to cover the cap insulating film and the second gate electrode;
A plurality of third gate electrodes formed on the interlayer insulating film so as to extend in a second direction intersecting the first direction;
The height from the main surface of the semiconductor substrate to the upper surface of the second gate electrode is higher than the height from the main surface of the semiconductor substrate to the upper surface of the first gate electrode,
A semiconductor device characterized in that a surface shape of the interlayer insulating film is uneven. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the surface shape of the second gate electrode is uneven. The semiconductor device according to claim 1,
A semiconductor device, wherein an adjacent interval between the second gate electrodes adjacent to each other in the second direction is about 90 nm or less. A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing a semiconductor substrate;
(B) forming a gate insulating film on the main surface of the semiconductor substrate;
(C) depositing a first conductor layer to be a first gate electrode later on the gate insulating film;
(D) depositing a first insulating film on the first conductor layer;
(E) depositing a second insulating film on the first insulating film;
(F) By patterning the first conductor layer, the first insulating film, and the second insulating film, the plurality of first gate electrodes, the first insulating film, and the second extending in the first direction. Forming an insulating film pattern;
(G) forming a sidewall insulating film on a side surface of the plurality of first gate electrodes, the first insulating film, and the second insulating film;
(H) The first gate electrode, the first insulating film, and the second insulating film are adjacent to each other between the patterns, on the gate insulating film, extending in the first direction, and then the second gate. Forming a plurality of second conductor layers to be electrodes;
(I) The plurality of second conductor layers are removed from the surface side, and the height from the main surface of the semiconductor substrate to the top surfaces of the plurality of second conductor layers is set to the first gate electrode from the main surface of the semiconductor substrate. A step of making the height higher than the upper surface of
(J) removing a part of the second insulating film and the sidewall insulating film;
(K) A step of making the surface shape of the plurality of second conductor layers uneven.
(L) depositing an interlayer insulating film so as to cover surfaces of the first insulating film and the plurality of second conductor layers;
(M) depositing a third conductor layer to be a third gate electrode later on the interlayer insulating film;
(N) The plurality of second gate electrodes separated in the first direction by patterning the third conductor layer, the interlayer insulating film, and the plurality of second conductor layers, and in the first direction Forming a plurality of the third gate electrodes extending in a second direction intersecting with each other. In the manufacturing method of the semiconductor device according to claim 4,
In the step (n), the plurality of second conductor layers are patterned so that an adjacent interval between the second gate electrodes adjacent along the second direction is about 90 nm or less. Device manufacturing method.

Images