KR100789610B1 - Method of manufacturing flash memory device - Google Patents

Abstract

A method for manufacturing a flash memory device is provided to suppress generation of a void between a first element and a second element by removing a TEOS layer as a top layer of a spacer. An isolation layer(33) is formed on a semiconductor substrate(31) in order to define unit cell elements(61,63) including a first and second cell regions. A gate oxide layer(35), a floating gate(37), an ONO layer(39), and a control gate(41) are formed on each of the first and second cell regions. A spacer including a first TEOS layer(43), a silicon nitride layer(45), and a second TEOS layer is formed on both sides of the gate oxide layer, the floating gate, the ONO layer, and the control gate. A source/drain region(49) is formed on the semiconductor substrate of both sides of the control gate. A silicide layer(51) is formed on the control gate and the source/drain region. The second TEOS layer is removed from the spacer by performing an etch process. A via hole is formed to expose the silicide layer on the drain region by forming and patterning an interlayer dielectric on the semiconductor substrate. A contact plug is formed within the via hole.

Description

Method of manufacturing flash memory device

1 is a diagram showing a layout of a cell array of a conventional flash memory device.

FIG. 2 is a cross-sectional view taken along the line II ′ of the cell array of the flash memory device of FIG. 1. FIG.

3A to 3H are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

31: semiconductor substrate 33: device isolation film

35: gate oxide film 37: floating gate

39: ONO film 41: control gate

43: first TEOS film 45: silicon nitride film

47: second TEOS film 48: spacer

49: source / drain region 51: silicide film

53: interlayer insulating film 55: via hole

57: contact plug 61, 63: cell element

The present invention relates to a flash memory device, and more particularly to a method of manufacturing a flash memory device that can prevent voids.

Flash memory devices are a type of programmable ROM (PROM) capable of writing, erasing, and reading information.

Flash memory devices may be divided into NOR-type structures in which cells are disposed in parallel between bit lines and ground, and NAND-type structures arranged in series, according to a cell array scheme.

NOR flash memory devices are commonly used for booting mobile phones because they allow high-speed random access when performing read operations. NAND-type flash memory devices have a slow read speed but a fast write speed, and are suitable for data storage and small size.

In addition, the flash memory device may be classified into a stack gate type and a split gate type according to the unit cell structure, and a floating gate device and a silicon-oxide-nitride-oxide-silicon (SONOS) device according to the shape of the charge storage layer. It can be divided into. Among them, the floating gate device usually includes a floating gate formed of polycrystalline silicon surrounded by an insulator, and the floating gate is charged by channel hot carrier injection or FN tunneling by Fowler-Nordheim Tunneling. Is injected or discharged to store and erase data.

1 is a diagram illustrating a layout of a cell array of a conventional flash memory device.

As shown in FIG. 1, a plurality of word lines 1 are arranged, and bit lines 3 are arranged to intersect the word line 1. The cell element is disposed at the intersection of the word line 1 and the bit line 3. Contact plugs 5 are arranged which are electrically connected to bit lines 3 between adjacent first and second cell elements. The first and second cell elements are electrically connected to one contact plug 5.

The cell element is selected by the word line 1, and the data signal supplied to the bit line 3 is stored in the selected cell element through the contact plug 5 or the data signal stored in the selected cell element is contact plug. It can be supplied to the bit line 3 via (5).

Therefore, the unit cell may be defined by the first and second cell elements.

FIG. 2 is a cross-sectional view taken along the line II ′ of the cell array of the flash memory device of FIG. 1.

As shown in FIG. 2, the unit cell may be defined by the first and second cell elements 26 and 28.

An element isolation film 13 (STI) is formed on the semiconductor substrate 11 to partition the cell elements.

First and second cell devices 26 and 28 are formed between the device isolation layers 13.

The gate oxide film 15, the floating gate 16, the ONO (oxide / nitride / oxide) film 17 and the control gate 18 are sequentially formed on the semiconductor substrate 11.

Spacers 21 are formed on side surfaces of the gate oxide film 15, the floating gate 16, the ONO film 17, and the control gate 18 to separate and protect the gate region. The spacer 21 includes a TEOS film 21a and a SiN film 21b.

Source / drain regions 23 are formed on the semiconductor substrate 11 on both sides of the spacer 21.

The silicide layer 24 is formed in the control gate 18 and the source / drain region 23 to improve the electrical contact performance between the gate region and the source / drain region 23.

Accordingly, the first and second gate regions including the gate oxide layer 15, the floating gate 16, the ONO layer 17, the control gate 18, and the spacer 21 and the source / drain regions 23 are formed. Cell elements 26 and 28 are formed.

An interlayer insulating layer 29 is formed on the first and second cell elements 26 and 28.

However, the first and second cell elements 26 and 28 have a very narrow width due to the thickness of the spacers 21 formed in the cell elements 26 and 28. In particular, in order to reduce the device size, the width between the first and second cell devices 26 and 28 is further reduced.

As such, when the interlayer insulating layer 29 is formed in a very narrow state between the first and second cell elements 26 and 28, defects such as voids may occur in the interlayer insulating layer 29.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a flash memory device capable of preventing a defect such as a void by expanding a width between cell elements to sufficiently secure a gap fill margin of an interlayer insulating film.

According to a first embodiment of the present invention for achieving the above object, a method of manufacturing a flash memory device, forming a device isolation film on a semiconductor substrate to partition a unit cell device including a first and a second cell region step; Forming a gate oxide film, a floating gate, an ONO film, and a control gate in each of the first and second cell regions on the semiconductor; Forming a spacer including a first TEOS film, a silicon nitride film, and a second TEOS film on both sides of the gate oxide film, the floating gate, the ONO film, and the control gate; Forming a source / drain region on the semiconductor substrate at both sides of the control gate; Forming a silicide layer on the control gate and the source / drain region; Performing a wet etching process to remove the second TEOS layer of the spacer; Forming and patterning an interlayer dielectric layer on the semiconductor substrate from which the second TEOS layer has been removed to form a via hole exposing the silicide layer on the drain region; And forming a contact plug in the via hole.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3A to 3H are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

As shown in FIG. 3A, the device isolation film 33 is formed on the semiconductor substrate 31 using a silicon oxide film or a BPSG film. The device isolation layer 33 is formed to partition the unit cell device.

In the present invention, the unit cell device may include first and second cell devices. Therefore, the device isolation layer 33 is not formed between the first and second cell devices. The first and second cell devices may be formed between adjacent device isolation layers 33.

The gate oxide film 35, the first polysilicon film, the ONO (oxide / nitride / oxide) film 39, and the second polysilicon film are sequentially stacked on the semiconductor substrate 31.

The gate oxide layer 35 and the floating gate 37 are selectively patterned by selectively patterning the gate oxide layer 35, the first polysilicon layer, the ONO layer 39, and the second polysilicon layer, respectively. ), The ONO film 39 and the control gate 41 are formed. The first cell region is an area for forming the first cell device, and the second cell area is an area for forming the second cell device.

As shown in FIG. 3B, a first tetraethyl orthosilicate (TEOS) layer 43, a silicon nitride (SiN) layer 45, and a second layer are disposed on the semiconductor substrate 31 including the control gate 41. The TEOS film 47 is sequentially stacked.

As shown in FIG. 3C, the first TEOS film 43, the silicon nitride film 45, and the second TEOS film 47 are selectively patterned to form the first TEOS film 43 and the silicon. A spacer 48 composed of the nitride film 45 and the second TEOS film 47 is formed. The spacer 48 is formed to separate and protect the gate region, and may be formed on both side surfaces of the gate oxide layer 35, the floating gate 37, the ONO layer 39, and the control gate 41. . The spacer 48 may be formed in a round shape by reactive ion etching (RIE). Both ends of each of the first TEOS layer 43, the silicon nitride layer 45, and the second TEOS layer 47 may be exposed to the outside by the patterning.

As shown in FIG. 3D, a source / drain region is formed on the semiconductor substrate 31 on both sides of the spacer 49 by performing an ion implantation process using the spacer 49 and the control gate 41 as a mask. Form 49. The source / drain region 49 is a region having conductivity by implanting ions by an ion implantation process.

Subsequently, a conductive material such as cobalt is formed and patterned on the entire region of the semiconductor substrate 31 including the spacer 49 to form the pattern in the control gate 41 and the source / drain region 49 of the gate region. The silicide film 51 is formed. The silicide layer 51 may be formed to improve electrical contact performance between the gate region and the source / drain region 49 and the wiring to be formed later.

Accordingly, the first and second gate and source / drain regions 49 include the gate oxide layer 35, the floating gate 37, the ONO layer 39, the control gate 41, and the spacers 48. Second cell elements 61 and 63 are formed.

As shown in FIG. 3E, the semiconductor substrate 31 is immersed in an etching solution such as hydrogen fluoride (HF) using a wet etching process to remove the second TEOS film 47, which is the uppermost layer of the spacer 48. .

In this case, the mixing ratio of the hydrogen fluoride (HF) and water (H 2 O) may have a range of 1: 100 to 1: 200, the process time may have a range of 100 seconds to 140 seconds.

As such, by removing the second TEOS film 47 of the spacer 48, the width between the first and second elements 61 and 63 is increased by twice the thickness of the second TEOS film 47. do. Therefore, as the width between the first and second elements 61 and 63 is greatly increased, voids are not generated between the first and second cell elements 61 and 63 when gap filling the interlayer insulating film described later. .

As shown in FIG. 3F, the boron phosphor silicate glass (BPSG) or the second TEOS layer 47 is removed and the semiconductor substrate 31 including the first and second cell elements 61 and 63 is removed. An interlayer insulating film 53 is formed using an insulating material such as USG (undoped silicate glass).

As described above, as the second TEOS layer 47 is removed, the width between the first and second cell elements 61 and 63 increases significantly, so that the interlayer insulating layer 53 is formed in the first and second layers. The gap between the first and second cell elements 61 and 63 when the gap is filled between the two cell elements 61 and 63 prevents defects such as voids from occurring in the interlayer insulating layer 53.

As shown in FIG. 3G, the interlayer insulating layer 51 may be exposed to expose the silicide layer 51 on the drain region 49 formed on the semiconductor substrate 31 between the first and second cell elements 61 and 63. 53 is selectively patterned to form via holes 55.

As shown in FIG. 3H, a conductive material such as tungsten is formed in the via hole 55 to form a contact plug 57.

Thereafter, a metal wire (not shown) that is electrically connected to the contact plug 57 may be formed.

As described above, according to the present invention, the TEOS film, which is the uppermost layer of the spacer, is removed to increase the width between the first and second devices by twice the thickness of the TEOS film. Accordingly, as the width between the first and second devices is greatly increased, voids are not generated between the first and second cell devices when the interlayer insulating film is gapfilled.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

Forming an isolation layer on the semiconductor substrate to partition the unit cell device including the first and second cell regions; Forming a gate oxide film, a floating gate, an ONO film, and a control gate in each of the first and second cell regions on the semiconductor; Forming a spacer including a first TEOS film, a silicon nitride film, and a second TEOS film on both sides of the gate oxide film, the floating gate, the ONO film, and the control gate; Forming a source / drain region on the semiconductor substrate at both sides of the control gate; Forming a silicide layer on the control gate and the source / drain region; Performing a wet etching process to remove the second TEOS layer of the spacer; Forming and patterning an interlayer dielectric layer on the semiconductor substrate from which the second TEOS layer has been removed to form a via hole exposing the silicide layer on the drain region; And Forming a contact plug in the via hole. The method of claim 1, wherein the etching solution of the wet etching process is hydrogen fluoride. 2. The flash memory of claim 1, wherein the conditions of each of the common wet methods include a mixing ratio of hydrogen fluoride and water in the range of 1: 100 to 1: 200 and a process time in the range of 100 to 140 seconds. Method of manufacturing the device. The method of claim 1, wherein an interval between the first and second cell regions is increased by twice the thickness of the second TEOS layer due to the removal of the second TOES layer.

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