CN101207091B - Method manufactruing of flash memory device - Google Patents

Method manufactruing of flash memory device Download PDF

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CN101207091B
CN101207091B CN2007103018967A CN200710301896A CN101207091B CN 101207091 B CN101207091 B CN 101207091B CN 2007103018967 A CN2007103018967 A CN 2007103018967A CN 200710301896 A CN200710301896 A CN 200710301896A CN 101207091 B CN101207091 B CN 101207091B
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semiconductor substrate
gate pattern
voluntarily
silicide
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CN101207091A (en
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朴真河
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DB HiTek Co Ltd
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Dongbu Electronics Co Ltd
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Priority claimed from KR1020060135571A external-priority patent/KR100789610B1/en
Priority claimed from KR1020060137287A external-priority patent/KR100840645B1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

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Abstract

The invention relates to a flash memory which increases the electric property by reducing or preventing gap from generating. The method for producing the flash memory according to the implementation way of the invention comprises the steps as follow: a plurality of gate patterns containing a tunnel oxide layer, a floating gate, a dielectric medium layer and a control gate is formed on a semiconductor substrate; a separator is formed at the upper part of the side wall of the gate pattern as the combined insulation layer structure; a source/leakage region can be formed at the upper part of the semiconductor at the two sides of the control gate; and the insulation layer which is positioned at the outermost of the separator layer is removed. A contact hole can be formed between the gate patterns by forming and drawing a insulation layer between layers. A contact plug is formed in the contact hole.

Description

The manufacture method of flush memory device
The application requires to enjoy the korean patent application No.10-2006-0137287 that submitted on December 29th, 2006, the korean patent application No.10-2006-0131443 that on December 20th, 2006 submitted to, the rights and interests of the korean patent application No.10-2006-0135571 that on December 27th, 2006 submitted to are incorporated herein its full content as a reference.
Technical field
The present invention relates to a kind of manufacture method of flush memory device, more specifically, relate to a kind of manufacture method that can prevent the flush memory device that the space generates.
Background technology
Flush memory device is a kind of programmable ROM that can write, wipe and read information.Flush memory device forms the unit string (unit string) that is configured to cell transistor connected in series.Be connected between bit line (bit line) and the ground wire because unit string is parallel, memory cell can right and wrong (NAND) type, is applicable to highly integrated.Be connected between bit line and the ground wire because cell transistor is parallel, memory cell can be or non-(NOR) type, be applicable to high speed operation.
Owing to can read the or/no type flush memory device at a high speed, so it can be used for guiding mobile phone.Have writing speed faster owing to having lower reading speed, so it is applicable to the storage data, wherein can considers to compress with nand type flash memory device.
According to the structure of unit cell, flush memory device can be divided into folded grid type or split-gate type.According to the configuration of charge storage layer, flush memory device can be divided into floating grid device and SONOS (silicon oxide nitride oxide silicon) device.The floating grid device generally includes the floating grid that is formed by polysilicon, and insulator ring is around it.Can or use FN (follower-Nordheim) tunneling effect that electric charge is injected or emission from floating grid by the channel hot carrier injection in order to store with obliterated data.
Yet because semiconductor device trends towards highly integratedly, flash cell should use the design rule of reduced size.Therefore, 0.13 μ flush memory device has the contact point in enough space formation unit cells.Along with reducing of unit cell size, form unit cell gate regions can with hole become too narrow so that after depositing operation, produce space A, as shown in Figure 1 to interlayer (interlayer) dielectric layer.
Space A changes the feature of each unit, produces the abnormal problem of word line work.Form contact point subsequently, if inject such as metals such as tungsten W, then tungsten can cause contact point contact bridge phenomenon to space A diffusion.Thereby tungsten can connect into bridge with other contact points.It is undesired that the grid that form in word line may move.The mistake that this will cause in the unit operations makes the reliability of flush memory device and output demote greatly.
Summary of the invention
Embodiments of the present invention relate to a kind of manufacture method of flush memory device, thereby by reducing or preventing that the space from producing the raising electrology characteristic.According to the embodiment of the present invention, the manufacture method of flush memory device is included in and forms a plurality of gate patterns that contain tunnel oxidation layer, floating grid, dielectric layer and control gate on the Semiconductor substrate.Above the side wall of this gate pattern, form separation pad as the composite insulation layer structure.Can above the semiconductor of these control gate both sides, form source/drain regions.Above described semiconductor, apply photoresist film.By not to exposure of the photoresist film between the gate pattern and development, between described gate pattern, form scum silica frost.Remove described scum silica frost.Above the Semiconductor substrate that has removed described scum silica frost, form interlevel dielectric layer.Remove and be positioned at the outmost insulating barrier of spacing cushion layer.Can be by interlayer (interlayer) dielectric layer be carried out composition and form contact hole between gate pattern.In this contact hole, form contact plug.
Description of drawings
Fig. 1 shows the space that produces in the flush memory device manufacturing process;
Fig. 2 a shows the technology cross-sectional view that is used to illustrate according to the manufacture method of the flush memory device of embodiment of the present invention to Fig. 2 h;
Fig. 3 shows the design sketch that is used for the manufacture method of flush memory device according to embodiment of the present invention;
Fig. 4 a shows the cross-sectional view that is used for the manufacturing process of flush memory device according to embodiment of the present invention to 4f;
Fig. 5 a shows the cross-sectional view that is used for the manufacturing process of flush memory device according to embodiment of the present invention to 5d.
Embodiment
Fig. 2 a shows the technology cross-sectional view that is used to illustrate according to the manufacture method of the flush memory device of embodiment of the present invention to Fig. 2 h.
Shown in the embodiment of Fig. 2 a, according to the manufacture method of flush memory device of the present invention above Semiconductor substrate 10 cellular zone and logic area in form a plurality of gate patterns 110 and 120 respectively, at this, Semiconductor substrate 10 forms technology, trap formation technology and raceway groove through the device isolation layer and forms technology.
In cellular zone, form identical shaped a plurality of gate patterns 110.A plurality of gate patterns can comprise the dielectric layer 40 of floating grid 30, the control gate 50 that plays the word line effect and the isolated controlling grid 50 and the floating grid 30 of tunnel oxidation layer 20, storage data.At this, dielectric layer 40 can be formed by for example oxygen-nitrogen-oxygen (ONO) structure.Form after a plurality of gate patterns 110 and 120, in the Semiconductor substrate 10 of cover gate pattern 110 not and 120, inject the low concentration impurity ion, form lightly doped drain (LDD) district.
Shown in Fig. 2 b, above the Semiconductor substrate 10 that contains a plurality of gate patterns 110 and 120, form oxide layer 63 and nitration case 64 subsequently according to the order of sequence.At this, the oxide layer 63 that is formed by tetraethoxysilane can form
Figure G2007103018967D00031
Arrive
Figure G2007103018967D00032
Thickness.Can above this oxide layer 63, form by silicon nitride Arrive The nitration case 64 of thickness.
As mentioned above, after forming oxide layer 63 and nitration case 64 according to the order of sequence, shown in the embodiment of Fig. 2 c, can on the oxide layer 63 of gate pattern 110 and 120 both sides and nitration case 64, carry out reactive ion etching (RIE) and form spacing cushion layer 60.Form the first hole district D1 simultaneously, it is space empty between the gate pattern 110.The surface of in the first hole district D1, exposing Semiconductor substrate 10.Use spacing cushion layer 60 to carry out ion implantation technology as the ion injecting mask and form source/drain region 49, it is the high-concentration dopant district of Semiconductor substrate 10.Formation spacing cushion layer 60 is isolated and is protected gate pattern 110, and because reactive ion etching (RIE) can have round-shaped.
Shown in Fig. 2 d, can use etchant to remove the nitration case 64 of separation pad 60, this etchant is 80% to 90% specifically can be 85% phosphoric acid (H 3PO 4) and the mixture of deionized water, thereby can keep oxide layer 63.Shown in the embodiment of Fig. 2 c, the first hole district D1 that the reason that removes nitration case 64 is to form spacing cushion layer 60 is narrower.Form in the back during the technology of interlayer dielectric layer 200, may produce the space in the first narrow like this hole district.In order to prevent that the space from producing, and removes the nitration case 64 of spacing cushion layer 60.The second hole district D2 has enough spaces to prevent the space generation when forming interlayer dielectric layer 200 between the gate pattern 110.For example, the width of the second hole district D2 can be about 90nm to 150nm.
, if use etchant remove the nitration case 64 of lateral wall partitioning bed course 60, then also remove oxide layer the upper side of gate pattern 110 above, expose the control gate 50 of gate pattern 110 thereafter.In the wet processing of the self-aligned silicide process of carrying out subsequently (salicide process), will damage gate pattern, make a side autoregistration silication of unwanted gate pattern 110 and 120.In order to prevent this from occurring, shown in the embodiment of Fig. 2 e, behind the nitration case 64 that removes spacing cushion layer 60, deposition self-aligned silicide barrier layer 140 above Semiconductor substrate 10.
Self-aligned silicide barrier layer 140 is to use low pressure chemical vapor deposition (LPCVD) method to remove nitration case 64 on Semiconductor substrate, by the SiN film that even ladder covers (uniform step coverage) that has of deposition on the Semiconductor substrate 10 that contains gate pattern 110 and 120, this SiN film has and is about
Figure G2007103018967D00041
Arrive
Figure G2007103018967D00042
Thickness.
After forming self-aligned silicide barrier layer 140, shown in the embodiment of Fig. 2 f, for removing, the zone of aiming at silicide process in execution voluntarily aims at silicide barrier layer 140 voluntarily, carry out the non-silicide RIE that aims at voluntarily, thereby, the silicide barrier layer of aligning voluntarily 140 that is injected with dopant area of the upside of the removable multiple source/drain region 49 that comprises Semiconductor substrate 10 and gate pattern 110 and 120.Therefore; although aim at voluntarily on the side wall that 140 of silicide barrier layers remain in gate pattern 110 and 120; thereby the side wall of protection gate pattern 110 and 120; remove behind the wet processing of the residual oxide in this zone in execution; the high-melting point metal that has that is formed by cobalt etc. is deposited upon the zone that silicide process is aimed in execution voluntarily; and carry out quick thermal treatment process thereon, thus can be on gate pattern 110 and 120 and the upper side in the multiple source/drain region 49 of semiconductor 10 above form a plurality of silicide layers 170 of aiming at voluntarily.
Carry out aim at silicide process voluntarily after, shown in the embodiment of Fig. 2 g, can contain Semiconductor substrate 10 between the gate pattern 110 of protect the second hole district D2 above formation interlevel dielectric layer 200.Use by phosphosilicate glass (PSG), boron phosphorus silicate glass (BPSG), unadulterated silex glass (USG) or PETEOS as metal before medium (PMD) form interlevel dielectric layer 200.Thereby the second hole district D2 has enough width does not produce the space when forming interlevel dielectric layer 200.Therefore, shown in the embodiment of Fig. 3, can provide the interlevel dielectric layer 200 that does not produce the space.
Shown in the embodiment of Fig. 2 h,, and, then in interlevel dielectric layer 200, will not produce the space by using electric conducting material filler opening 55 to form drain electrode contact point 57 such as tungsten (W) if between gate pattern 110, form contact hole 55.Therefore, when deposits tungsten in contact hole 55, can not produce the diffusion phenomena that cause by the space, thereby flush memory device can move normally.
Fig. 4 a shows cross-sectional view according to the manufacturing process of the flush memory device of embodiment of the present invention to 4f.As Fig. 4 a to shown in the 4f to be used for the manufacturing process of flush memory device according to embodiment of the present invention different at the aspects such as structure of spacing cushion layer, but other part technologies are identical with first execution mode.Therefore, similar Reference numeral is represented similar element and is omitted wherein description in the accompanying drawing.
At first, shown in the embodiment of Fig. 4 a, sequential aggradation first oxide layer 63, nitration case 64 and second oxide layer 65 above the Semiconductor substrate 10 that contains a plurality of gate patterns 110 that are used for whole upper floor units unit and 120.
At this, can form thickness approximately
Figure G2007103018967D00051
Arrive
Figure G2007103018967D00052
First oxide layer 63 that forms by tetraethyl orthosilicate (TEOS).Can form thickness is about
Figure G2007103018967D00053
Arrive
Figure G2007103018967D00054
The nitration case that forms by silicon nitride.Can form thickness is about
Figure G2007103018967D00055
Arrive
Figure G2007103018967D00056
Second oxide layer 65 that forms by TEOS.
Shown in the embodiment of Fig. 4 b,, then form spacing cushion layer 60 at the place, two sides of gate pattern 110 and 120 if can pass through reactive ion etching (RIE) method etching first oxide layer 63, nitration case 64 and second oxide layer 65.Form the first hole district D1 simultaneously, it is space empty between the gate pattern 110.In the first hole district D1, expose the surface of Semiconductor substrate 10.Nitration case 64 can be used as etch stop layer, thereby can stop etch process at nitration case 64.Forming spacing cushion layer 60 isolates and protects gate pattern 110.By reactive ion etching (RIE), this spacing cushion layer can be circular.Can expose the two ends of first oxide layer 63 and the nitration case 64 and second oxide layer 65 in edge.Can use spacing cushion layer 60 to carry out ion implantation technology with formation source/drain region 49 as the ion injecting mask, it is the high density doped region of Semiconductor substrate 10.
Shown in Fig. 4 c, can form in the surface of the Semiconductor substrate 10 that contains spacing cushion layer 60 and the electric conducting material of composition such as cobalt forms in the source/drain region 49 in control gate 50 and gate regions and aims at silicide layer 170 voluntarily.Can form and aim at the electrical contact performance that silicide layer 170 improves the lead that area of grid and source/drain region 49 and back will form voluntarily.
Shown in the embodiment of Fig. 4 d, with Semiconductor substrate 10 immerse such as in the etchant of hydrogen fluoride (HF) to remove second oxide layer 65, it is the outermost layer of spacing cushion layer 60.At this moment, the mixing ratio of hydrogen fluoride (HF) and water (H2O) can change in the scope at about 1: 100 to 1: 200, and the process time can change in the scope at about 100 seconds to 140 seconds.Second oxide layer 65 that removes spacing cushion layer 60 makes the width of gate pattern 110 approximately double.Because the width between the gate pattern 110 increases greatly,, between gate pattern 110, will not produce the space when interlevel dielectric layer 200 during at the back filling pore.
Shown in the embodiment of Fig. 4 e, can above the Semiconductor substrate 10 that contains gate pattern 110 and 120, use dielectric substance to form interlevel dielectric layer 200 such as phosphosilicate glass (PSG), boron phosphorus silicate glass (BPSG), unadulterated silex glass (USG) or PETEOS.
Shown in the embodiment of Fig. 4 f, composition interlevel dielectric layer 200 is with the silicide layer 51 of 49 tops, source of exposure/drain region selectively, and this source/drain region 49 is formed at the top of the Semiconductor substrate 10 between the gate pattern 110, thereby forms contact hole 55.Available electric conducting material filler opening 55 such as tungsten (W) forms drain electrode contact 57.
Manufacture method does not according to the embodiment of the present invention produce the space in interlevel dielectric layer 200.When tungsten is filled in the contact hole 55, do not experience the diffusion phenomena that produce owing to the space.Thereby the flush memory device operation is normal.
Fig. 5 a is to describe the cross-sectional view that is used for the manufacturing process of flush memory device according to embodiment of the present invention to 5d.Show the manufacturing process that is used for flush memory device according to embodiment of the present invention to 5d as Fig. 5 a and aim at voluntarily the silicide except forming scum silica frost at the first hole district D1 and producing, other parts can be identical with other execution modes.Therefore, similar Reference numeral is represented similar element and is omitted wherein description in the accompanying drawing.
Shown in the embodiment of Fig. 5 a, the upper surface coating photoresist film in Semiconductor substrate 10 through overexposure and developing process, thereby only forms photoresist pattern 150 at logic region.At this moment, shown in the embodiment of Fig. 5 b, in cellular zone, do not expose and the photoresist film of the first hole district D1 that develops and keep this photoresist film, thereby in the first hole district D1, form scum silica frost 160.
Keep scum silica frost 160,, be not removed thereby remove in the step at photoresist subsequently because in developing process, there is not abundant exposed photoresist film.As mentioned above, in the first hole district D1, form scum silica frost 160, thereby in the etch process of second oxide layer 65 subsequently, in first oxide layer 63, do not produce undercutting (under cut) phenomenon.
Shown in the embodiment of Fig. 5 c, use BHF solution to remove outmost second oxide layer 65 of spacing cushion layer 60 by wet etching process.In the etch process of second oxide layer 65, the edge of first oxide layer 63 that formed by same material of etching covers (cap) region D 2 thereby form spacing cushion layer 60 and second together.
Remove than first oxide layer 63 and the nitration case 64 relative second thicker oxide layers 65, thereby the second hole district D2 has enough width.Therefore, after forming spacing cushion layer 60, the first hole district D1 of contact hole 55 to be formed is not too narrow, thereby prevents that when forming interlevel dielectric layer 200 space from producing.Can reduce the hole between the gate pattern 110 by the thickness of second oxide layer 65 that removes, thereby the device that can reach higher degree is integrated.Even change the profile (profile) of spacing cushion layer 60, the whole operation of flush memory device is unaffected.
Scum silica frost 160 is formed between the gate pattern 110, thereby at the wet etching process that is used for removing second oxide layer 65, the bar that scum silica frost 160 serves as first oxide layer 63 prevents etchant etching first oxide layer 63.Therefore, prevented undercut phenomenon in the edge of first oxide layer 63.This helps to prevent that contact hole 55 in the back from forming the formation of the bridge in the technologies.
Shown in the embodiment of Fig. 5 d, after photoresist pattern 150 that removes logic area and scum silica frost 160, above Semiconductor substrate 10, form interlevel dielectric layer 200.Form after the contact hole 55 between gate pattern 110, can deposit, for example tungsten (W) forms drain electrode contact point 57.
Owing in interlevel dielectric layer 200, do not produce the space, when deposits tungsten, can not produce the diffusion phenomena that cause by the space, thereby make that the flush memory device operation is normal.In first oxide layer 63 of gate pattern 110, do not produce undercut phenomenon, thereby when forming drain electrode contact point 57, can eliminate the influence of the bridge of the device-to-device that causes owing to the diffusion of imbedding tungsten.
But be to be understood that for those skilled in the art, can in disclosed execution mode, make various modifications and distortion.Therefore, under the situation that does not break away from the spirit and scope of the present invention, can design various other improvement and the distortion that will fall in the disclosed the spirit and scope of the present invention.

Claims (19)

1. the manufacture method of a flush memory device comprises:
Above Semiconductor substrate, form a plurality of gate patterns that contain tunnel oxidation layer, floating grid, dielectric layer and control gate;
Above the side wall of described gate pattern, form and have the compound spacing cushion layer of composite insulation layer;
In the Semiconductor substrate of described gate pattern both sides, form at least one source/drain region;
Above described Semiconductor substrate, apply photoresist film;
By not to exposure of the photoresist film between the gate pattern and development, between described gate pattern, form scum silica frost;
Remove the outmost insulating barrier of described compound spacing cushion layer;
Remove described scum silica frost;
Above the Semiconductor substrate that has removed described scum silica frost, form interlevel dielectric layer;
Above described Semiconductor substrate,, between described gate pattern, form contact hole by described interlevel dielectric layer is carried out composition; And
In described contact hole, form contact plug.
2. method according to claim 1 is characterized in that, described spacing cushion layer is stacked (stack) that contains first oxide layer, nitration case and second oxide layer.
3. method according to claim 2 is characterized in that, first oxide layer of described spacing cushion layer is formed by tetraethoxysilane, and described nitration case is formed by silicon nitride and described second oxide layer is formed by tetraethoxysilane.
4. method according to claim 1 is characterized in that, uses wet etch process to remove described outmost insulating barrier.
5. method according to claim 3 is characterized in that, is included in the silicide layer of aligning voluntarily that forms in gate pattern and the source/drain region.
6. method according to claim 4 is characterized in that, the etchant in described wet etching process is a kind of in BHF and the hydrogen fluoride.
7. method according to claim 6 is characterized in that, the mixing ratio that each etch process all comprises hydrogen fluoride and water in 1: 100 to 1: 200 scope and the process time 100 seconds to 140 seconds scope.
8. method according to claim 5 is characterized in that, in source/drain region by the described silicide layer of aiming at voluntarily of described contact holes exposing.
9. method according to claim 1 is characterized in that, described spacing cushion layer is piling up by described oxide layer and described nitration case.
10. method according to claim 9 is characterized in that, comprises:
Deposition is aimed at silicide barrier layer voluntarily above the described Semiconductor substrate that contains the spacing cushion layer that has removed nitration case;
Carry out and non-ly aim at the silicidation reaction ion(ic) etching voluntarily carrying out the described zone of aiming at silicide process voluntarily, so that remove the silicide barrier layer of aligning voluntarily in the described zone; And
Carry out aim at silicide process voluntarily after, remainingly form described interlevel dielectric layer above aiming at silicide barrier layer voluntarily and leaving the Semiconductor substrate of described gate pattern having removed.
11. method according to claim 10 is characterized in that, the described insulating barrier that the outermost that uses etchant to remove described spacing cushion layer applies, and wherein said etchant is 80% to 90% phosphoric acid (H 3PO 4) and the mixture of 10% to 20% deionized water.
12. method according to claim 10 is characterized in that, the described silicide barrier layer of aiming at voluntarily is for using having the silicon nitride film that even ladder covers and forming of low-pressure chemical vapor deposition method deposition
Figure F2007103018967C00021
Arrive Thickness.
13. method according to claim 12 is characterized in that, the width that is formed with the hole district between the described gate pattern of aiming at silicide barrier layer voluntarily is that 90nm is to 150nm.
14. method according to claim 10 is characterized in that, comprises:
Removing the described silicide barrier layer of aiming at voluntarily above the described gate upper surface He above described source/drain region; And
Use metal level under high-melting-point by forming a plurality of silicide layers of aiming at voluntarily carrying out the described described metal level of area deposition of aiming at silicide process voluntarily, and carry out rapid thermal anneal process.
15. method according to claim 1 is characterized in that, described interlevel dielectric layer is a medium and use by the group of forming of phosphosilicate glass, boron phosphorus silicate glass, unadulterated silex glass and PETEOS one of them to form before the metal.
16. method according to claim 1 is characterized in that, comprises to use described gate pattern by the low concentration impurity ion being injected into the lightly doped drain that forms in the described Semiconductor substrate.
17. method according to claim 1 is characterized in that, comprises:
Form the device isolation layer contain the Semiconductor substrate of unit cell device of described gate pattern in differentiation above; And
Above described control gate and described source/drain region, form and aim at silicide layer voluntarily.
18. method according to claim 1 is characterized in that, because the hole that makes between the described gate pattern that removes of described outmost insulating barrier doubles.
19. a flush memory device comprises:
The a plurality of gate patterns that contain tunnel oxidation layer, floating grid, dielectric layer and control gate above Semiconductor substrate;
Compound spacing cushion layer above described gate pattern side wall with composite insulation layer;
At least one source/drain region in the Semiconductor substrate of described gate pattern both sides;
Contact hole between the described gate pattern that penetrates interlayer insulating film above the described Semiconductor substrate; And
Plug in described contact hole,
Wherein, described contact hole is by apply photoresist film above described Semiconductor substrate, form scum silica frost by the photoresist film between the gate pattern not being exposed and is developed between the described gate pattern, remove the outmost insulating barrier of described compound spacing cushion layer, remove described scum silica frost, form interlevel dielectric layer above the Semiconductor substrate that has removed described scum silica frost, composition forms by described interlevel dielectric layer is carried out above described Semiconductor substrate then.
CN2007103018967A 2006-12-20 2007-12-20 Method manufactruing of flash memory device Expired - Fee Related CN101207091B (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
KR1020060131443 2006-12-20
KR10-2006-0131443 2006-12-20
KR1020060131443A KR100831158B1 (en) 2006-12-20 2006-12-20 Method manufactruing of flash memory device
KR1020060135571A KR100789610B1 (en) 2006-12-27 2006-12-27 Method of manufacturing flash memory device
KR1020060135571 2006-12-27
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US10784270B2 (en) * 2018-06-26 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method to improve fill-in window for embedded memory
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