KR100590380B1 - Method of manufacturing a flash memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory device, and in the case where a junction line is formed by a W Local Interconnection (WLI) method, since a gap between a gate and a contact must be sufficiently secured, In order to solve the problem that the junction line can be minimized by the WLI method, a spacer insulating film is formed on the sidewall of the control gate, and a tungsten plug is formed by the self-aligning method to minimize the distance between the gate and the contact A method of manufacturing a flash memory device capable of sufficiently securing a gate length is disclosed.

WLI method, self-alignment method

Description

[0001] The present invention relates to a method of manufacturing a flash memory device,             

1 is a layout diagram illustrating a method of manufacturing a conventional flash memory device.

FIGS. 2A to 2C are cross-sectional views taken along the line X-X 'in FIG. 1 for explaining a method of manufacturing a conventional flash memory device.

3A to 3D are cross-sectional views of a device for explaining a method of manufacturing a flash memory device according to the present invention.

FIG. 4 is a layout diagram illustrating a drain separation process during a manufacturing process of a flash memory device according to the present invention. FIG.

Description of the Related Art [0002]

10: semiconductor substrate 11: element isolation film

12: floating gate 13: control gate

14: drain contact 15: source contact

21: Tunnel oxide film 22: Dielectric film

23: first interlayer insulating film 24: photoresist pattern

25: tungsten plug 26: second interlayer insulating film

27: metal wiring

31: semiconductor substrate 32: tunnel oxide film

33: floating gate 34: dielectric film

35: control gate 36: spacer insulating film

37: sidewall oxide film 38: tungsten plug

39: interlayer insulating film 40: metal wiring

S: Source D: Drain

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device by minimizing a gap between a gate electrode and a contact when a junction line is formed by a W Local Interconnection (WLI) And to a method of manufacturing a flash memory device capable of minimizing the size.

Generally, in a flash memory device, a common source line is connected to a junction region, and a common source line is connected by a WLI method in accordance with a demand for miniaturization of a cell size. However, the conventional WLI method requires a lot of masking processes and requires a sufficient gap between the gate and the contact, which makes it impossible to miniaturize the cell size.

A method of manufacturing a flash memory device using the conventional WLI method will now be described with reference to FIGS. 1 and 2. FIG.

FIG. 1 is a layout view illustrating a method of manufacturing a conventional flash memory device. FIGS. 2A to 2C are cross-sectional views taken along the line X-X 'in FIG. 1 for explaining a method of manufacturing a conventional flash memory device.

2A, a tunnel oxide film 21 and a conductive material for a floating gate are sequentially formed on a semiconductor substrate 10 on which a device isolation film 11 is formed, and a conductive material for a floating gate and a tunnel oxide film (21) is etched. Thereafter, the dielectric film 22 and the conductive material for the control gate are sequentially formed on the entire structure, the gate etching process is performed to complete the control gate 13, and then the self-aligned etching process is continued, 12) is completed. Thereafter, a source / drain ion implantation process is performed to form a source S and a drain D. Next, after the first interlayer insulating film 23 is formed and planarized on the entire structure, the first interlayer insulating film 23 is etched so that the source S and the drain D are exposed by an etching process using a contact mask The drain contact 14 and the source contact 15 are formed.

Referring to FIG. 2B, a barrier metal layer (not shown) and tungsten are sequentially deposited and etched on the entire structure in which the drain contact 14 and the source contact 15 are formed to form a drain contact 14 and a source contact 15 A tungsten plug 25 is formed.

A second interlayer insulating film 26 is formed on the entire structure in which the tungsten plug 25 is formed and a tungsten plug 25 buried in the drain contact 14 in the etching process using the contact mask is formed, And a metal wiring 27 is formed on the entire structure.

In the manufacturing process of the flash memory device, it is necessary to secure a sufficient gap between the gate and the contact in order to prevent breakage of the device when the drain contact and the source contact are formed. As a result, the cell size can not be minimized. In addition, since 5 V is applied to the drain terminal during the programming of the flash memory device, it is difficult to realize a cell having a gate length of 0.2 m or less, which causes a problem of cell punch through characteristic deterioration.

Accordingly, the present invention provides a method of manufacturing a flash memory device that forms a junction line using a WLI method, in which a WLI is formed by a self-aligning method to minimize a gap between a gate and a contact, And a method for manufacturing a flash memory device.

According to an aspect of the present invention, there is provided a method of fabricating a flash memory device, including: forming a tunnel oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer sequentially on a semiconductor substrate having an isolation layer; Forming a control gate by etching the second polysilicon layer and the dielectric film in a gate etching process, forming an insulating material on the entire structure, etching the spacer to form a spacer insulating film on the sidewall of the patterned second polysilicon layer step; Etching the first polysilicon layer and the tunnel oxide film to form a floating gate, and simultaneously exposing the semiconductor substrate in a region where the source and drain are to be formed; Forming a source and an drain, and forming a sidewall oxide film on the sidewall of the floating gate; Depositing a barrier metal layer and tungsten on the entire structure, and then etching the tungsten layer and the barrier metal layer to form a tungsten plug; Forming a drain contact pad on the drain side by partially opening and etching the line-shaped tungsten on the drain side, thereby forming a drain contact pad; Forming an interlayer insulating film on the entire structure in which the tungsten plug is formed, and etching the interlayer insulating film to expose the tungsten plug on the drain region to form a contact hole; And forming a metal wiring so that the contact hole is buried.

In the present invention, when a junction line is formed by using the WLI method, a spacer is formed on a sidewall of the gate electrode, and the WLI process is performed by a self-aligning method, thereby minimizing a gap between the gate and the contact.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3D are cross-sectional views of a device for explaining a method of manufacturing a flash memory device according to the present invention.

3A, a tunnel oxide film 31 and a first polysilicon layer 33 are sequentially formed on a semiconductor substrate 31 on which an isolation film is formed, and a dielectric film (not shown) is formed on the first polysilicon layer 33 34 and a second polysilicon layer 35 are sequentially formed. Thereafter, the second polysilicon layer 35 and the dielectric film 34 are etched by the gate etching process to form the control gate 35, and then an insulating material is formed on the entire structure and the spacer is etched to form the second poly A spacer insulating film 36 is formed on the sidewall of the silicon layer 35. [

Here, the insulating material is formed by depositing an oxide film to a thickness of 300 to 1500 ANGSTROM.

Referring to FIG. 3B, the first polysilicon layer 33 and the tunnel oxide film 32 are etched by using the mask used for forming the spacer insulating film 36 to form the floating gate 33, The semiconductor substrate 31 in the region to be formed is exposed. Since the etching selectivity between the oxide film and the polysilicon is large in the first polysilicon layer 33 etching process, the loss of the spacer insulating film 36 is negligible. Thereafter, the source S and the drain D are formed by a source / drain ion implantation process and a thermal oxidation process is performed so that a sidewall oxide film 37 of 100 to 500 ANGSTROM is grown on the side wall of the patterned floating gate 33 do. The sidewall oxide film 37 serves to insulate the tungsten plug formed in the subsequent process from the floating gate 33.

Referring to FIG. 3C, a barrier metal layer (not shown) and tungsten are deposited over the entire structure. Thereafter, the tungsten layer and the barrier metal layer are etched to form a tungsten plug 38. In this case, tungsten in the form of a line continues to exist along the source and the drain.

Next, tungsten in the form of a line formed on the drain side is partly opened by using a drain separation mask, and then an etching process is performed. This process is shown in Fig.

FIG. 4 is a layout view illustrating a drain separation process in a manufacturing process of a flash memory device according to the present invention.

In FIG. 4, a portion (portion A) of tungsten in the form of a line is exposed on the drain side, and then an etching process is performed, thereby forming a drain contact pad.

3D, an interlayer insulating film 39 is formed and planarized on the entire structure in which the tungsten plug 38 is formed, and then the tungsten plug 38 formed on the drain region in the etching process using the metal 1 contact mask is exposed Thereby forming a contact hole. Then, the metal wiring 40 is formed so that the contact hole is buried.

As described above, since the junction line using the WLI method is formed by the self-aligning method, the cell size can be minimized and thereby the gate length can be sufficiently secured.

 As described above, according to the present invention, when a junction line is formed by a W Local Interconnecting (WLI) method, a WLI is formed by a self-aligning method, thereby minimizing the gap between the gate and the contact. As a result, the gate length can be sufficiently secured, and punch through phenomenon during programming can be prevented, thereby improving program efficiency. In addition, the number of net dies can be increased, and the production cost can be reduced.

Claims (3)

Sequentially forming a tunnel oxide film, a first polysilicon layer, a dielectric film, and a second polysilicon layer on a semiconductor substrate having a device isolation film formed thereon; Forming a control gate by etching the second polysilicon layer and the dielectric film by a gate etching process, forming an insulating material on the entire structure, and etching the spacer to form a spacer insulating film on the sidewall of the patterned second polysilicon layer ; Etching the first polysilicon layer and the tunnel oxide film to form a floating gate, and simultaneously exposing the semiconductor substrate in a region where the source and drain are to be formed; Forming a source and an drain, and forming a sidewall oxide film on a sidewall of the floating gate; Depositing a barrier metal layer and tungsten on the entire structure, and then etching the tungsten layer and the barrier metal layer to form a tungsten plug; Forming a drain contact pad on the drain side by partially opening and etching the line-shaped tungsten on the drain side, thereby forming a drain contact pad; Forming an interlayer insulating film on the entire structure in which the tungsten plug is formed, and etching the interlayer insulating film to expose the tungsten plug on the drain region to form a contact hole; And And forming a metal wiring to fill the contact hole. The method according to claim 1, Wherein the insulating material is formed by depositing an oxide film to a thickness of 300 to 1500 ANGSTROM. The method according to claim 1, Wherein the sidewall oxide film is formed to a thickness of 100 to 500 ANGSTROM.

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