KR20050080705A - Flash memory device having gate contact plug and fabrication method thereof - Google Patents

Abstract

Provided is a flash memory device having a gate contact plug. The flash memory device includes an isolation layer formed in a predetermined region of a semiconductor substrate to define an active region. A gate electrode is disposed on the semiconductor substrate while crossing the device isolation layer and the active region. An opening is formed on the gate electrode to expose a gate contact hole region in the width of the gate electrode. An interlayer insulating film covering the gate electrode and the hard mask pattern is disposed. A gate contact plug penetrating the interlayer insulating film and connected to the gate contact hole region is disposed. The gate electrode is formed as follows. After the gate electrode film and the hard mask film are sequentially formed on the device isolation film and the active region, the hard mask film is patterned to form a hard mask pattern. Subsequently, the gate electrode layer is etched using the hard mask pattern as an etching mask to form a gate electrode. The gate electrode is formed to cross the device isolation layer and the active region. Thereafter, the hard mask pattern is patterned to expose a gate contact hole region at the gate electrode width.

Description

Flash memory device having a gate contact plug and a method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a flash memory device having a gate contact plug and a method of manufacturing the same.

In the Noah type flash memory semiconductor structure, a hard mask etching process is used for cell gate patterning. The reason for using the hard mask process is that the cell gate patterning requires etching of several layers such as tungsten silicide, polysilicon, ONO (oxide / nitride / oxide), and polysilicon, which results in insufficient photoresist margin during patterning. Become a factor. Therefore, only a hard mask on the tungsten silicide is etched using a thin photoresist to remove the photoresist. The lower layers are then etched using the patterned hard mask as an etch mask. This satisfies two factors: photoresist selectivity margin and improved pattern accuracy. In this process, however, a hard mask of a certain thickness remains on the silicide. Therefore, in the current borderless contact etching process, a nitride film used as a contact etch stop layer is formed, an interlayer insulating film is formed, and then contact hole etching is performed. The contact hole is formed on the active region and the gate electrode at the same time. The contact hole is formed on the gate electrode to form a hard mask oxide film, a nitride film, and an interlayer insulating film. The remaining hard mask on the gate electrode becomes an element that lacks the contact hole etching margin. Therefore, before forming the contact hole, a step of removing the hard mask of the portion where the contact hole is to be formed in advance is necessary. The step of removing the hard mask in advance before forming the contact hole has been presented in Korean Patent Laid-Open No. 2003-0044195.

1A is a plan view illustrating a flash memory device manufactured by removing the hard mask before forming a contact hole.

FIG. 1B is a cross-sectional view taken along line II ′ of a flash memory device manufactured by removing the hard mask of FIG. 1A before forming a contact hole. FIG.

1A and 1B, an isolation layer 110 is disposed in a predetermined region of the semiconductor substrate 100 to define an active region. The device isolation layer 110 has a trench device isolation structure. A gate electrode 120 crossing the device isolation layer 110 and the active region is disposed on the semiconductor substrate including the device isolation layer 110. A hard mask pattern 125 is disposed on the gate electrode 120 to expose a partial region H of the gate contact hole region of the gate electrode 120. A conformal nitride film 130 is disposed on the entire surface of the semiconductor substrate including the gate electrode 120 and the hard mask pattern 125. An interlayer insulating layer 135 is disposed on the nitride layer 130. A gate contact plug 140 penetrating the interlayer insulating layer 135 and the nitride layer 130 and connecting to the upper portion of the gate electrode 120 is disposed. A contact plug 150 penetrates the interlayer insulating layer 135 and the nitride layer 130 and connects with the active region of the semiconductor substrate 100. The common source line S is disposed at one side of the gate electrode 120.

In the prior art, only a partial region H of the gate contact hole region on the gate electrode 120 is etched to secure the contact formation margin. However, the contact plug is formed on the gate electrode 120 because the remaining hard mask pattern surrounding the gate contact plug 140 and the nitride film A covering the remaining hard mask pattern are disposed on the gate electrode 120. The width that can be formed becomes narrow.

In addition, as the device is gradually miniaturized, it is difficult to etch the hard mask only in a portion of the gate contact hole region on the gate electrode. Therefore, there is a need for a method for forming a gate contact plug suitable for high integration.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a flash memory device suitable for securing a contact formation margin of a gate contact hole forming portion and a method of manufacturing the same.

Embodiments of the present invention provide a flash memory device having a gate contact plug. The flash memory device includes an isolation layer formed in a predetermined region of a semiconductor substrate to define an active region. A gate electrode is disposed on the semiconductor substrate while crossing the device isolation layer and the active region. An opening is formed on the gate electrode to expose a gate contact hole region in the width of the gate electrode. An interlayer insulating film covering the gate electrode and the hard mask pattern is disposed. A gate contact plug penetrating the interlayer insulating film and connected to the gate contact hole region is disposed.

The gate electrode preferably has a structure in which a floating gate conductor film, a dielectric film, and a control gate conductor film are sequentially stacked.

Preferably, the common source junction region is disposed on one side of the gate electrode.

Other embodiments of the present invention provide a method of manufacturing a flash memory device having a gate contact plug. This method includes forming a device isolation film defining an active region on a semiconductor substrate. A gate electrode film and a hard mask film are sequentially formed on the device isolation layer and the active region. The hard mask layer is patterned to form a hard mask pattern. The gate electrode layer is etched using the hard mask pattern as an etching mask to form a gate electrode. The gate electrode is formed to cross the device isolation layer and the active region. The hard mask pattern is patterned to have an opening in the gate contact hole region at the gate electrode width. An interlayer insulating film is formed on the semiconductor substrate having the gate electrode and the hard mask pattern. A gate contact plug is formed to penetrate the interlayer insulating film and to be connected to the gate contact hole region.

The gate electrode may be formed by sequentially stacking a floating gate conductor film, a dielectric film, and a control gate conductor film.

Patterning the hard mask pattern may further include patterning a common source junction region on one side of the gate electrode.

It is preferable to form the hard mask film as an oxide film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience of description. Like numbers refer to like elements throughout.

2 is a plan view of a flash memory device according to an exemplary embodiment of the present invention.

3A to 3G are cross-sectional views taken along the line II-II 'of FIG. 2 for describing a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

2 and 3A, an isolation layer 15 is formed on the semiconductor substrate 10 to define an active region. The device isolation film 15 is preferably formed by a trench device isolation method. A gate oxide film 20 is formed on the active region of the semiconductor substrate 10.

2 and 3B, a first conductor layer 25 is formed on the gate oxide layer 20 and the device isolation layer 15. The first conductor layer 25 may be formed of polysilicon. A dielectric film 30 is formed on the first conductor film 25. The dielectric film 30 is preferably formed of an ONO (oxide film / nitride film / oxide film) film. A second conductor film 35 is formed on the dielectric film 30. The second conductor layer 35 may be formed of polysilicon. The third conductor film 40 is formed on the second conductor film 35. The third conductor film 40 may be formed of tungsten silicide. A hard mask film is formed on the third conductor film 40. The hard mask layer is patterned to form a hard mask pattern 45 that crosses the device isolation layer and the active region. The hard mask pattern 45 is preferably formed of an oxide film.

2 and 3C, the third conductor layer 40, the second conductor layer 35, the dielectric layer 30, and the first conductor layer 25 using the hard mask pattern 45 as an etching mask. ) Is sequentially etched to form a gate electrode including a third conductor pattern 40a, a second conductor pattern 35a, a dielectric film pattern 30a, and a first conductor pattern 25a crossing the device isolation layer and the active region. To form 43. The first conductor pattern 25a becomes a floating gate electrode, and the second and third conductor patterns 35a and 40a become a control gate electrode.

2 and 3D, a photoresist film is formed on the entire surface of the semiconductor substrate having the gate electrode 43. The photoresist film is patterned to form a photoresist pattern 50 having a first opening 52 and a second opening 53. Accordingly, the first opening 52 exposes the upper portion of the gate oxide film 20 and the device isolation layer 15 on one side of the gate electrode 43, as shown in FIG. 3D. In a subsequent process, a common source line S is formed in a region exposed through the first opening 52, and the first opening 52 is not formed and is covered with the photoresist pattern 50. A drain junction region is formed in the active region. The second opening 53 defines a region in which the hard mask pattern 45 is to be etched together in an etching process for forming a common source line S. Accordingly, the second opening 53 exposes the top surface of the hard mask pattern 45 in the region B in which the gate contact hole is to be formed.

2 and 3E, in order to form a common source line S as described above, the device isolation layer exposed through the first opening 52 by an anisotropic etching method using an oxide film etching recipe ( 15 and the gate oxide film 20 are etched. In this case, the oxide film etching recipe preferably has an etching selectivity with respect to the semiconductor substrate 10. Accordingly, the gate oxide layer 20 and the device isolation layer 15 are etched under the first opening 52 to expose the upper surface of the active region and the inner wall of the trench. In the etching process using the oxide film etching recipe, the hard mask patterns 45 exposed through the second openings 53 are etched together. Accordingly, the top surface of the gate electrode 43 of the gate contact hole region B is exposed. Accordingly, all of the hard mask patterns 45 on the gate electrode 43 of the gate contact hole region B are etched, and the hard mask patterns 45 of the portion C outside the gate contact hole region remain. Will be.

2 and 3F, after removing the photoresist pattern 50, a conformal first interlayer insulating layer 55 is formed on the entire surface of the semiconductor substrate 10. A second interlayer insulating film 60 is formed on the first interlayer insulating film 55. The first interlayer dielectric layer 55 may be formed of a material layer having an etch selectivity with respect to the second interlayer dielectric layer 60. The second interlayer insulating film 60 is preferably formed of an oxide film.

2 and 3G, the active region of the gate contact hole and the drain junction region exposing the top surface of the gate electrode 43 by sequentially patterning the second and first interlayer insulating layers 60 and 55. A drain contact hole is formed to expose the drain. A gate contact plug 65 and a drain contact plug 70 filling the gate contact hole and the drain contact hole are formed. In particular, in the case of the gate contact hole, the gate contact hole can be formed by the width of the gate electrode 43 of the gate contact hole region B, thereby reducing the contact failure due to the miniaturization of the device.

Referring to FIGS. 2 and 3G again, a flash memory device according to an exemplary embodiment of the present invention will be described.

2 and 3G, an isolation layer 15 is disposed in a predetermined region of the semiconductor substrate 10 to define an active region. The device isolation layer 15 preferably has a trench device isolation structure. A gate electrode 43 crossing the device isolation layer 15 and the active region is disposed on the semiconductor substrate including the device isolation layer 15. The gate electrode 43 is formed of a first conductor pattern 25a, a dielectric layer pattern 30a, a second conductor pattern 35a, and a third conductor pattern 40a sequentially formed on the device isolation layer 15. Is done. The first and second conductor patterns 25a and 35a may be polysilicon. The dielectric film pattern 30a is preferably an ONO (oxide film / nitride film / oxide film) film. Preferably, the third conductor pattern 40a is tungsten silicide. The first conductor pattern 25a becomes a floating gate electrode, and the second and third conductor patterns 35a and 40a become a control gate electrode. The hard mask pattern C exposing the gate contact hole region B is disposed on the gate electrode 43. Therefore, the hard mask pattern C is disposed to cross the active region and the device isolation layer.

The upper surface of the active region and the inner wall of the trench are formed to expose a common source line S on one side of the gate electrode 43. A conformal first interlayer insulating film 55 is disposed on the entire surface of the semiconductor substrate including the gate electrode 43. A second interlayer insulating layer 60 is disposed on the first interlayer insulating layer 55. The first interlayer dielectric layer 55 may be a material layer having an etch selectivity with respect to the second interlayer dielectric layer 60. The second interlayer insulating film 60 is preferably an oxide film. A gate contact plug 65 penetrating the second and first interlayer insulating films 60 and 55 and connecting to the upper surface of the gate electrode 43 is disposed. A drain contact plug 70 penetrates through the second and first interlayer insulating films 60 and 55 and connects with an active region of the semiconductor substrate 10.

According to the present invention as described above, the gate contact hole can be formed by the width of the gate electrode by etching the hard mask pattern of the gate contact hole forming portion by the width of the gate electrode, thereby reducing contact defects due to the miniaturization of the device. You can do it. Therefore, the degree of integration of the flash memory device can be improved.

1A is a plan view illustrating a flash memory device according to the related art.

FIG. 1B is a cross-sectional view taken along line II ′ of the flash memory device of FIG. 1A.

2 is a plan view of a flash memory device according to an exemplary embodiment of the present invention.

3A to 3G are cross-sectional views taken along the line II-II 'of FIG. 2 for describing a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

Claims (8)

Semiconductor substrates; An isolation layer formed in a predetermined region of the semiconductor substrate to define an active region; A gate electrode disposed on the semiconductor substrate while crossing the device isolation layer and the active region; A hard mask pattern having an opening on the gate electrode to expose a gate contact hole region at a width of the gate electrode; An interlayer insulating layer covering the gate electrode and the hard mask pattern; And And a gate contact plug penetrating the interlayer insulating layer and connected to the gate contact hole region. The method of claim 1, And the gate electrode has a structure in which a floating gate conductor film, a dielectric film, and a control gate conductor film are sequentially stacked. The method of claim 1, And a common source junction region on one side of the gate electrode. The method of claim 1, And the hard mask pattern is an oxide film. Forming a device isolation film defining an active region on the semiconductor substrate, A gate electrode film and a hard mask film are sequentially formed on the device isolation layer and the active region; Patterning the hard mask layer to form a hard mask pattern; The gate electrode layer is etched using the hard mask pattern as an etch mask to form a gate electrode crossing the device isolation layer and the active region, Patterning the hard mask pattern to have an opening in a gate contact hole region at the gate electrode width, An interlayer insulating film is formed on the semiconductor substrate having the gate electrode and the hard mask pattern; And forming a gate contact plug that penetrates the interlayer insulating layer and connects to the gate contact hole region. The method of claim 5, And the gate electrode is formed by sequentially stacking a floating gate conductor film, a dielectric film, and a control gate conductor film. The method of claim 5, Patterning a common source junction region on one side of the gate electrode while patterning a hard mask pattern. The method of claim 5, And forming said hard mask film as an oxide film.