KR970077688A - Gate forming method of nonvolatile memory device - Google Patents

Gate forming method of nonvolatile memory device Download PDF

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Publication number
KR970077688A
KR970077688A KR1019960018240A KR19960018240A KR970077688A KR 970077688 A KR970077688 A KR 970077688A KR 1019960018240 A KR1019960018240 A KR 1019960018240A KR 19960018240 A KR19960018240 A KR 19960018240A KR 970077688 A KR970077688 A KR 970077688A
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KR
South Korea
Prior art keywords
etching
layer
mask
control gate
pattern
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Application number
KR1019960018240A
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Korean (ko)
Inventor
서강일
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960018240A priority Critical patent/KR970077688A/en
Publication of KR970077688A publication Critical patent/KR970077688A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)

Abstract

불휘발성 메모리소자의 자기 정합 구조의 게이트를 형성하는 방법에 대해 기재되어 있다. 이는, 반도체기판상에 터널산화막, 플로팅게이트층, 층간절연막, 컨트롤게이트층 및 마스크용 산화막이 순차적으로 적층되어 형성된 결과물 상에, 컨트롤게이트를 패터닝하기 위한 포토레지스트 패턴을 형성하는 단계와, 포토레지스트 패턴을 식각 마스크로 사용하여 상기 마스크용 산화막을 식각한 후, 포토레지스트 패턴을 제거하는 단계와, 마스크용 산화막을 마스크로 사용하여 상기 컨트롤게이트층을 식각하여 컨트롤게이트 패턴을 형성하는 단계와, 컨트롤게이트 패턴의 측벽에 보호막을 형성하는 단계 및 층간절연막 및 플로팅게이트층을 차례로 식각하는 단계를 구비하는 것을 특징으로 한다.A method of forming a gate of a self-aligned structure of a nonvolatile memory device is described. This method includes forming a photoresist pattern for patterning a control gate on a product formed by sequentially stacking a tunnel oxide film, a floating gate layer, an interlayer insulating film, a control gate layer, and an oxide film for a mask on a semiconductor substrate. Etching the mask oxide film using a pattern as an etch mask, removing the photoresist pattern, and etching the control gate layer using the mask oxide film as a mask to form a control gate pattern; and Forming a passivation layer on sidewalls of the gate pattern and etching the interlayer insulating layer and the floating gate layer in sequence.

따라서, 후속되는 층간절연막 식각 및 플로팅게이트층 식각시에 식각 가스에 의한 폴리사이드의 측벽이 침해되는 노칭현상을 방지할 수 있고, 측벽 보호막은 식각 설비에서 인-사이튜로 형성할 수 있으므로 공정상의 어려움이 없이 효율적으로 자기 정합 구조의 게이트를 형성할 수 있다.Therefore, it is possible to prevent notching phenomenon that the sidewalls of the polysides are invaded by the etching gas during the subsequent interlayer insulating layer etching and the floating gate layer etching, and the sidewall protective layer can be formed in-situ in the etching facility. It is possible to efficiently form the gate of the self-matching structure without difficulty.

Description

불휘발성 메모리소자의 게이트 형성방법Gate forming method of nonvolatile memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명에 의한 불휘발성 메모리소자의 게이트 형성방법을 설명하기 위한 단면도들이다.2A to 2C are cross-sectional views illustrating a gate forming method of a nonvolatile memory device according to the present invention.

Claims (2)

반도체기판 상에 터널산화막, 플로팅게이트층, 층간절연막, 컨트롤게이트층 및 마스크용 산화막이 순차적으로 적층되어 형성된 결과물 상에, 컨트롤게이트를 패터닝하기 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각 마스크로 사용하여 상기 마스크용 산화막을 식각한 후, 포토레지스트 패턴을 제거하는 단계; 상기 마스크용 산화막을 마스크로 사용하여 상기 컨트롤게이트층을 식각하여 컨트롤게이트 패턴을 형성하는 단계; 상기 컨트롤게이트 패턴의 측벽에 보호막을 형성하는 단계; 및 상기 층간절연막 및 플로팅게이트층을 차례로 식각하는 단계를 구비하는 것을 특징으로 하는 불휘발성 메모리소자의 게이트 형성방법.Forming a photoresist pattern for patterning the control gate on a resultant product formed by sequentially stacking a tunnel oxide film, a floating gate layer, an interlayer insulating film, a control gate layer, and an oxide film for a mask on a semiconductor substrate; Etching the mask oxide layer using the photoresist pattern as an etching mask, and then removing the photoresist pattern; Etching the control gate layer using the mask oxide layer as a mask to form a control gate pattern; Forming a passivation layer on sidewalls of the control gate pattern; And sequentially etching the interlayer insulating layer and the floating gate layer. 제1항에 있어서, 상기 보호막을 형성하는 단계는 상기 컨트롤게이트층을 식각하는 단계와 인-사이튜로 진행되는 것을 특징으로 하는 불휘발성 메모리소자의 게이트 형성방법.The method of claim 1, wherein the forming of the passivation layer is performed in-situ with etching the control gate layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960018240A 1996-05-28 1996-05-28 Gate forming method of nonvolatile memory device KR970077688A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960018240A KR970077688A (en) 1996-05-28 1996-05-28 Gate forming method of nonvolatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960018240A KR970077688A (en) 1996-05-28 1996-05-28 Gate forming method of nonvolatile memory device

Publications (1)

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KR970077688A true KR970077688A (en) 1997-12-12

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100395755B1 (en) * 2001-06-28 2003-08-21 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
KR100415084B1 (en) * 2001-06-15 2004-01-13 주식회사 하이닉스반도체 Method for fabricating flash memory device
KR100590380B1 (en) * 1999-12-28 2006-06-15 주식회사 하이닉스반도체 Method of manufacturing a flash memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100590380B1 (en) * 1999-12-28 2006-06-15 주식회사 하이닉스반도체 Method of manufacturing a flash memory device
KR100415084B1 (en) * 2001-06-15 2004-01-13 주식회사 하이닉스반도체 Method for fabricating flash memory device
KR100395755B1 (en) * 2001-06-28 2003-08-21 삼성전자주식회사 Non-volatile memory device and method of fabricating the same

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