CN110190058A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN110190058A CN110190058A CN201910447934.2A CN201910447934A CN110190058A CN 110190058 A CN110190058 A CN 110190058A CN 201910447934 A CN201910447934 A CN 201910447934A CN 110190058 A CN110190058 A CN 110190058A
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- side wall
- memory block
- gate structure
- substrate
- external zones
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method, the manufacturing method of the semiconductor devices includes: to provide a substrate with external zones and memory block, and the external zones and memory block have been respectively formed at least one gate structure；Side wall is formed on the side wall of the gate structure；The side wall of the segment thickness on the side wall of the gate structure on the memory block is at least removed, so that the spacing between the side wall between the adjacent gate structure increases；And interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covers the gate structure and the side wall.Technical solution of the present invention reduces the depth-to-width ratio between the side wall between adjacent gate structure, so that the quantity in the cavity in interlayer dielectric layer between side wall between adjacent gate structure reduces and size reduces, so that product yield is improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
It, generally can be using height after the side wall technique of storage unit is completed in the production process of semiconductor devices
Density plasma CVD (HDP CVD) technique carries out the filling of interlayer dielectric layer (ILD).But with product
It is continuously updated the replacement, each characteristic size constantly reduces in storage unit, and the depth-to-width ratio between adjacent side wall is also increasing,
Existing high density plasma CVD technique is caused to can no longer meet the filling demand of interlayer dielectric layer in turn,
It is filled in the interlayer dielectric layer between adjacent side wall and often generates cavity, and the presence in these cavities, so that later in sides adjacent
It bridges between the conductive contact plug formed in interlayer dielectric layer between wall and parallel connection occurs, cause semiconductor devices short-circuit,
And then product yield is caused to decline.
Therefore, the depth-to-width ratio between adjacent side wall how is reduced, to avoid semiconductor devices short circuit, and then it is good to improve product
The problem of rate is current urgent need to resolve.
Summary of the invention
The purpose of the present invention is to provide a kind of semiconductor devices and its manufacturing methods, so that between adjacent gate structure
Side wall between depth-to-width ratio reduce so that the sky in the interlayer dielectric layer between side wall between adjacent gate structure
The quantity in hole is reduced and size reduces, so that product yield is improved.
To achieve the above object, the present invention provides a kind of manufacturing methods of semiconductor devices, comprising:
A substrate with external zones and memory block is provided, and the external zones and memory block have been respectively formed at least one
Gate structure；
Lightly doped district is formed in the substrate of the gate structure two sides, and the lightly doped district part is positioned at described
The lower section of gate structure；
Side wall is formed on the side wall of the gate structure；
The side wall of the segment thickness on the side wall of the gate structure on the memory block is at least removed, so that
Spacing between the side wall between the adjacent gate structure increases；
Using the gate structure and the side wall for removing the segment thickness as exposure mask, source electrode and drain electrode is formed in described
In the substrate of the gate structure two sides of memory block, and the adjacent gate structure of the memory block is shared described
Source electrode or the drain electrode, the lightly doped district partly overlap with the source electrode and the drain electrode respectively；And
Interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covers the gate structure and the side wall.
Optionally, the step of removing the side wall of the segment thickness include:
Patterned photoresist layer is formed on the substrate, the patterned photoresist layer exposes the storage
Area；And
Using the patterned photoresist layer as exposure mask, the side wall of the segment thickness on the memory block is only removed,
So that the spacing between the side wall between the adjacent gate structure on the memory block increases；
Alternatively,
The side wall for removing the external zones and the segment thickness on the memory block simultaneously, so that the external zones
Spacing between the side wall and the external zones and institute between the adjacent gate structure on the memory block
The spacing stated between the side wall between the adjacent gate structure on the intersection two sides of memory block increases.
Optionally, the substrate of the gate structure two sides of the source electrode and the drain electrode in the memory block is formed
In step include:
With the gate structure on the patterned photoresist layer and the memory block and remove the part thickness
The side wall of degree is exposure mask, carries out ion to the substrate of the memory block of the patterned photoresist layer exposure and mixes
It is miscellaneous, to form source electrode and drain electrode in the substrate of the gate structure two sides of the memory block；And
Remove the patterned photoresist layer.
Optionally, in the lining for forming the gate structure two sides of the source electrode and the drain electrode in the memory block
After in bottom and the interlayer dielectric layer is being formed before on the substrate, forms source electrode and drain electrode in the institute of the external zones
It states in the substrate of gate structure two sides.
Optionally, using the side wall of cleaning process removal segment thickness.
Optionally, the side wall is made of the first silicon oxide layer, silicon nitride layer and the second silicon oxide layer from inside to outside, is adopted
Second silicon oxide layer for removing part or all of thickness is cleaned with hydrogen fluoride solution.
Optionally, the thickness of first silicon oxide layer, silicon nitride layer and the second silicon oxide layer be followed successively by 10nm~15nm,
10nm~15nm and 30nm~40nm, the amount of the hydrogen fluoride solution can clean the side wall thicknesses of removal 40nm~50nm, so that
Second silicon oxide layer is obtained to be completely removed.
Optionally, the gate structure is being formed before on the external zones and the memory block, be initially formed tunnelling oxygen
Change layer on the external zones and the memory block；Isolating oxide layer is also formed between the gate structure and the side wall.
The present invention also provides a kind of semiconductor devices, using the manufacturing method of the semiconductor devices provided by the invention
Manufacture, comprising:
Substrate has external zones and memory block；
Gate structure and side wall are formed on the external zones and memory block, and the side wall is located at the gate structure
On side wall；
Lightly doped district, in the substrate of the gate structure two sides, and the lightly doped district part is positioned at described
The lower section of gate structure；
Source electrode and drain electrode, in the substrate of the external zones and memory block, and the source electrode and the drain electrode point
Not Wei Yu the gate structure two sides the substrate in, the adjacent gate structure of the memory block shares the source
Pole or the drain electrode, the lightly doped district partly overlap with the source electrode and the drain electrode respectively；And
Interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer covers the gate structure and the side wall.
Optionally, between the adjacent side wall between two adjacent gate structures on the memory block
Spacing is greater than or equal between the adjacent side wall between two adjacent gate structures on the external zones
Spacing.
Compared with prior art, technical solution of the present invention has the advantages that
1, the manufacturing method of semiconductor devices of the invention, by providing a substrate with external zones and memory block, and
At least remove memory block on gate structure side wall on segment thickness side wall so that the adjacent gate structure it
Between the side wall between spacing increase so that the depth-to-width ratio between side wall between adjacent gate structure reduces,
So that the quantity in the cavity in interlayer dielectric layer between side wall between adjacent gate structure reduces and size reduces, thus
So that product yield is improved.
2, semiconductor devices of the invention is manufactured by using the manufacturing method of semiconductor devices of the invention, so that phase
The depth-to-width ratio between side wall between adjacent gate structure reduces, so that between the side wall between adjacent gate structure
The quantity in the cavity in interlayer dielectric layer is reduced and size reduces, so that product yield is improved.
Detailed description of the invention
Fig. 1 is the flow chart of the manufacturing method of the semiconductor devices of one embodiment of the invention；
Fig. 2 a~2j is the device schematic diagram in the manufacturing method of semiconductor devices shown in FIG. 1；
Fig. 3 is the schematic diagram in interlayer dielectric layer with the semiconductor devices in cavity.
Wherein, the reference numerals are as follows for attached drawing 1~3:
10- substrate；11- external zones；The memory block 12-；13- first grid structure；14- second grid structure；141- floating gate
Layer；Dielectric layer between 142- grid；143- control grid layer；15- fleet plough groove isolation structure；16- tunnel oxide；17- lightly doped district；
18- side wall；The first silicon oxide layer of 181-；182- silicon nitride layer；The second silicon oxide layer of 183-；The patterned photoresist layer of 19-；
20- source electrode；21- drain electrode；22- interlayer dielectric layer；H1- height；W1~W7- spacing；The cavity V1-.
Specific embodiment
To keep the purpose of the present invention, advantages and features clearer, below in conjunction with 1~3 pair of attached drawing proposed by the present invention half
Conductor device and its manufacturing method are described in further detail.It should be noted that attached drawing is all made of very simplified form and
Using non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
One embodiment of the invention provides a kind of manufacturing method of semiconductor devices, and refering to fig. 1, Fig. 1 is that the present invention one is implemented
The flow chart of the manufacturing method of the semiconductor devices of example, the manufacturing method of the semiconductor devices include:
Step S1, a substrate with external zones and memory block is provided, and the external zones and memory block have been respectively formed on
At least one gate structure；
Step S2, lightly doped district is formed in the substrate of the gate structure two sides, and the lightly doped district part
Positioned at the lower section of the gate structure；
Step S3, side wall is formed on the side wall of the gate structure；
Step S4, the side of the segment thickness on the side wall of the gate structure on the memory block is at least removed
Wall, so that the spacing between the side wall between the adjacent gate structure increases；
Step S5, using the side wall of the gate structure and the removal segment thickness as exposure mask, source electrode and leakage are formed
Pole is in the substrate of the gate structure two sides of the memory block, and the adjacent gate structure of the memory block
The source electrode or the drain electrode are shared, the lightly doped district partly overlaps with the source electrode and the drain electrode respectively；
Step S6, interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer covers the gate structure and institute
State side wall.
Introduce the manufacturing method of semiconductor devices provided in this embodiment, Fig. 2 a in more detail referring next to Fig. 2 a~2j
~2j is the device schematic diagram in the manufacturing method of semiconductor devices shown in FIG. 1, and Fig. 2 a~2j is also the vertical of semiconductor devices
To schematic cross-section.
A substrate 10 with external zones 11 and memory block 12 is provided according to step S1 refering to Fig. 2 a and Fig. 2 b, and described
External zones 11 and memory block 12 have been respectively formed at least one gate structure, the gate structure formed on the external zones 11
For first grid structure 13, the gate structure formed on the memory block 12 is second grid structure 14.Wherein, described to deposit
Usually there are multiple (a plurality of) second grid structures 14 to correspond to finally formed storage array in storage area 12, and described deposits
Each second grid structure 14 in storage area 12 includes dielectric layer 142 and control between the floating gate layer 141 of bottom-up formation, grid
Grid layer 143.The gate structure is being formed before on the external zones 11 and the memory block 12, tunnelling oxygen can be initially formed
Change layer 16 on the external zones 11 and the memory block 12.The first grid structure 13 on the external zones 11 and described
The second grid structure 14 on memory block 12 can be formed using following technique: deposit institute on the tunnel oxide 16
State dielectric layer 142 between floating gate layer 141 and grid；Dielectric layer 142 and floating gate layer 141 between the grid are etched, the memory block is only retained
Dielectric layer 142 and floating gate layer 141 between the part grid on 12, and dielectric layer between the remaining grid on the memory block 12
142 and the stacked structure of floating gate layer 141 can be arranged in array；On the external zones 11 and the memory block 12 described in covering
Control grid layer 143 etches the control grid layer 143 and the tunnel oxide 16 to the upper surface of the substrate 10, thus exists
The first grid structure 13 is formed on the external zones 11 and the second grid structure is formed on the memory block 12
14, at this point, the height of the second grid structure 14 on the memory block 12 is higher than the first grid structure on the external zones 11
The depth-to-width ratio of 13 height, the interval on the memory block 12 between the adjacent second grid structure 14 is greater than the periphery
The depth-to-width ratio at the interval in area 11 between the adjacent first grid structure 13.Certainly, in other embodiments of the invention,
The second grid structure 14 on the memory block 12 and the first grid structure 13 on the external zones 11 can also be with
It is completely independent production, i.e., in the process, in the second grid structure 14 and the external zones 11 on the memory block 12
The first grid structure 13 in do not have using with along with depositing operation formation film layer.In the other embodiment of the present invention
In, the second grid structure 14 on the memory block 12 and the first grid structure 13 on the external zones 11 are not
The gate structure of limitation in this present embodiment can be gate structure well known to those of skill in the art in the art.
In addition, the intersection in the external zones 11 and the memory block 12 is also formed with fleet plough groove isolation structure 15, institute
Fleet plough groove isolation structure 15 is stated for the device formed on the external zones 11 and the device formed on the memory block 12 is electric
Sexual isolation is come, and forms the fleet plough groove isolation structure 15 in the intersection of the external zones 11 and the memory block 12 the step of
It include: the etching substrate 10, to form a groove (not shown) in the intersection of the external zones 11 and the memory block 12；
It fills in another isolating oxide layer (not shown) Yu Suoshu groove, to form the fleet plough groove isolation structure 15, the shallow trench
The top surface of isolation structure 15 is higher than the top surface of the substrate 10 of the external zones 11 and the memory block 12.In addition, institute
State external zones 11 and the memory block 12 by other regions in other fleet plough groove isolation structures and semiconductor devices carry out every
From.
Lightly doped district 17 is formed in the substrate 10 of the gate structure two sides according to step S2 refering to Fig. 2 c, and
17 part of lightly doped district is located at the lower section of the gate structure.That is, the first grid on the external zones 11
The substrate 10 of 13 two sides of pole structure neutralizes the substrate of 14 two sides of second grid structure on the memory block 12
The lightly doped district 17 is all formed in 10.The lightly doped district 17 is formed in the lining of the external zones 11 and memory block 12
Step in bottom 10 may include: with the first grid structure 13 and the second grid structure 14 for exposure mask, using multiple
The mode of ion implanting carries out ion doping to the substrate 10 of the external zones 11 and memory block 12, respectively described outer
Enclose the second gate in the substrate 10 of 13 two sides of first grid structure in area 11 and on the memory block 12
The lightly doped district 17 is formed in the substrate 10 of 14 two sides of pole structure.Improve the storage by the lightly doped district 17
The performance of the MOS transistor device formed in area 12 and the external zones 11.
Refering to Fig. 2 d, according to step S3, side wall 18 is formed on the side wall of the gate structure, that is, forming side wall 18 in institute
On the side wall for stating first grid structure 13 and the second grid structure 14.The first grid structure 13 and the side wall 18 it
Between and the second grid structure 14 and the side wall 18 between be also formed with isolating oxide layer (not shown).The present embodiment
In, the side wall 18 can be by the first silicon oxide layer from inside to outside (i.e. from the side wall of the gate structure from inside to outside)
181, silicon nitride layer 182 and the second silicon oxide layer 183 composition, first silicon oxide layer 181, silicon nitride layer 182 and the second oxygen
The thickness of SiClx layer 183 successively can for 10nm~15nm (for example, 11nm, 14nm etc.), 10nm~15nm (for example, 11nm,
14nm etc.) and 30nm~40nm (for example, 32nm, 35nm, 38nm etc.).In other embodiments, the material of the side wall 18 can be with
It is that well known to a person skilled in the art one or more of other materials for nitrogen-oxygen-silicon, silicon nitride or silicon carbide etc., and not
It is limited to double-layer structure or single layer structure, and well known to a person skilled in the art other laminated construction.It can be seen that from Fig. 2 d,
Two adjacent second grid structures at the height H1 of the top surface apart from the substrate 10, on the memory block 12
The spacing between the adjacent side wall 18 between 14 is W1, on 11 intersection two sides of the memory block 12 and the external zones
Two adjacent second grid structures 14 and the first grid structure 13 between the adjacent side wall 18 between
Spacing be W2.
Refering to Fig. 2 e to Fig. 2 g, according to step S4, the gate structure at least removed on the memory block 12 is (i.e. described
Second grid structure 14) side wall on segment thickness the side wall 18 so that the side between neighboring gate structures
Spacing between wall 18 increases.
The step of removing the side wall 18 of the segment thickness includes: to be initially formed patterned photoresist layer 19 in described
On substrate 10, the patterned photoresist layer 19 exposes the memory block 12, then with the patterned photoresist layer 19
For exposure mask, the side wall 18 of the segment thickness on the memory block 12 is only removed, so that adjacent on the memory block 12
12 intersection of spacing and the external zones 11 and the memory block between the side wall 18 between second grid structure 14
It is described (between the i.e. described first grid structure 13 and the second grid structure 14) between neighboring gate structures on two sides
Spacing between side wall 18 increases, reduce as a result, second grid structure 14 on the memory block 12 with the side wall 18 it
Between interval depth-to-width ratio, to be conducive to improve the subsequent filling capacity when the middle depositional coating here, and the external zones
The thickness of the side wall 18 on 11 is uninfluenced, as shown in figure 2 e and 2f.Wherein, the patterned photoresist layer 19 can be after
Continuation of insurance is stayed, and subsequent step is used for.It can be seen that from Fig. 2 e, second silicon oxide layer of the segment thickness on the memory block 12
183 are removed, so that two adjacent institutes at the height H1 of the top surface apart from the substrate 10, on the memory block 12
Stating the spacing between the adjacent side wall 18 between second grid structure 14 becomes W3, the memory block 12 and the periphery
Two adjacent second grid structures 14 on 11 intersection two sides of area and adjacent between the first grid structure 13
The side wall 18 between spacing become W4, and spacing W3 is greater than spacing W1, and spacing W4 is greater than spacing W2；It can from Fig. 2 f
Out, second silicon oxide layer 183 of the full depth on the memory block 12 is removed, so that apart from the substrate 10
It is adjacent described between two adjacent second grid structures 14 on the memory block 12 at the height H1 of top surface
Spacing between side wall 18 becomes W5, two adjacent described on 11 intersection two sides of the memory block 12 and the external zones
The spacing between the adjacent side wall 18 between second grid structure 14 and the first grid structure 13 becomes W6, and
Away from W5 > spacing W3 > spacing W1 and spacing W6 > spacing W4 > spacing W2.
Alternatively, the step of removing the side wall 18 of the segment thickness includes: while removing the external zones 11 and institute
The side wall 18 of the segment thickness on memory block 12 is stated, so that the adjacent first grid structure on the external zones 11
It is described between the spacing between the side wall 18 between 13, the adjacent second grid structure 14 on the memory block 12
The adjacent first grid structure in spacing and the external zones 11 and 12 intersection two sides of the memory block between side wall 18
The spacing between the side wall 18 between 13 and second grid structure 14 increases, and as shown in Figure 2 g, can be seen that from Fig. 2 g,
Second silicon oxide layer 183 of full depth on the memory block 12 is removed, the segment thickness on the external zones 11
Second silicon oxide layer 183 be removed so that at the height H1 of the top surface apart from the substrate 10, the memory block
The spacing between the adjacent side wall 18 between two adjacent second grid structures 14 on 12 is W5, described to deposit
Two adjacent second grid structures 14 and first grid structure on 11 intersection two sides of storage area 12 and the external zones
The spacing between the adjacent side wall 18 between 13 is W7, and spacing W5 > spacing W3 > spacing W1 and spacing W7 > spacing
W6 > spacing W4 > spacing W2.
The step of from the side wall 18 of the above-mentioned removal segment thickness it is found that the side wall 18 by from inside to outside
When one silica layer 181, silicon nitride layer 182 and the second silicon oxide layer 183 form, described the of part or all of thickness is only removed
Silicon dioxide layer 183, first silicon oxide layer 181 and the silicon nitride layer 182 are not removed, to guarantee semiconductor devices
Dielectric pressure resistance performance.
It can be using the side wall 18 of cleaning process removal segment thickness.When the side wall 18 is by first from inside to outside
It, can be using hydrogen fluoride solution cleaning removal part when silicon oxide layer 181, silicon nitride layer 182 and the second silicon oxide layer 183 form
Or second silicon oxide layer 183 of full depth.When first silicon oxide layer 181, silicon nitride layer 182 and the second silica
The thickness of layer 183 is followed successively by 10nm~15nm (for example, 11nm, 14nm etc.), 10nm~15nm (for example, 11nm, 14nm etc.)
When with 30nm~40nm (for example, 32nm, 35nm, 38nm etc.), the amount of the hydrogen fluoride solution can clean removal 40nm~50nm
The side wall thicknesses of (for example, 42nm, 45nm, 48nm etc.) so that second silicon oxide layer 183 is completely removed, and then make
The spacing obtained between the side wall 18 between neighboring gate structures is sufficiently large.
Refering to Fig. 2 h and Fig. 2 i, according to step S5, with the side wall of the gate structure and the removal segment thickness
18 be exposure mask, forms source electrode 20 and drain electrode 21 in the gate structure (the i.e. described second grid structure 14) of the memory block 12
In the substrate 10 of two sides, and the adjacent gate structure (the i.e. described second grid structure 14) of the memory block 12 is altogether
With the source electrode 20 or the drain electrode 21, the lightly doped district 17 partly overlaps with the source electrode 20 and the drain electrode 21 respectively.
When only removing the side wall 18 of the segment thickness on the memory block 12 in step s 4, the source electrode is formed
20 and 21 step in the substrate 10 of 14 two sides of second grid structure of the memory block 12 of drain electrode include:
With the patterned photoresist layer 19 in step S4 and the second grid structure 14 on the memory block 12 and go
Except the side wall 18 of the segment thickness is exposure mask, the memory block 12 exposed to the patterned photoresist layer 19
The substrate 10 carries out ion doping, in the substrate 10 of 14 two sides of second grid structure of the memory block 12
Source electrode 20 and drain electrode 21 are formed, as shown in fig. 2h, in the memory block 12, the adjacent second grid structure 14 shares one
A source electrode 20, and the lightly doped district 17 partly overlaps with the source electrode 20 and the drain electrode 21 respectively；The pattern is removed again
The photoresist layer 19 of change, can remove the patterned photoresist layer 19 using cineration technics specifically can pass through oxygen
It is reacted Deng with the carbon in photoresist, hydrogen, oxygen, nitrogen, generates the discharge of the volatile materials such as carbon dioxide, water, nitrogen, with
The patterned photoresist layer 19 is removed.
When the side wall for removing the segment thickness on the external zones 11 and the memory block 12 simultaneously in step s 4
When 18, the lining of 14 two sides of second grid structure of the source electrode 20 and the drain electrode 21 in the memory block 12 is formed
Step in bottom 10 includes: to be initially formed on patterned photoresist layer (not shown) Yu Suoshu substrate 10, a patterning
Photoresist layer expose the memory block 12；Again with the institute on described one patterned photoresist layer and the memory block 12
Stating second grid structure 14 and removing the side wall 18 of the segment thickness is exposure mask, to described one patterned photoresist layer
The substrate 10 of the exposed memory block 12 carries out ion doping, in the second grid structure of the memory block 12
Source electrode 20 and drain electrode 21 are formed in the substrate 10 of 14 two sides.Therefore, the patterned photoresist layer 19 and a figure
The photoresist layer of case shelters the external zones 11, prevents in 14 two sides of second grid structure of the memory block 12
The substrate 10 in formed the source electrode 20 and it is described drain electrode 21 when the external zones 11 is had an impact, moreover, even if going
Except the side wall 18 of the segment thickness on the memory block 12 will not produce the formation of the source electrode 20 and the drain electrode 21
It is raw to influence.
In addition, forming the source electrode 20 and the drain electrode 21 in 14 liang of the second grid structure of the memory block 12
After in the substrate 10 of side and the interlayer dielectric layer 22 is being formed before on the substrate 10, forms source electrode 20 and leakage
Pole 21 is in the substrate 10 of 13 two sides of first grid structure of the external zones 11, as shown in fig. 2i, the periphery
Institute is formed on the dosage of ion implanting and type and the memory block 12 when forming the source electrode 20 and the drain electrode 21 in area 11
It states different when source electrode 20 and the drain electrode 21.And in the external zones 11, the lightly doped district 17 respectively with the source electrode 20
It partly overlaps with the drain electrode 21.Certainly, the source electrode 20 and drain electrode 21 are being formed in the first grid of the external zones 11
During in the substrate 10 of 13 two sides of pole structure, the memory block 12 is also needed by another patterned photoresist layer (not
Diagram) masking, and after completion remove another patterned photoresist layer.
It is formed on (ILD) Yu Suoshu of interlayer dielectric layer 22 substrate 10, the inter-level dielectric refering to Fig. 2 j according to step S6
22 covering of the layer gate structure (the i.e. described first grid structure 13 and the second grid structure 14) and the side wall 18.?
The interlayer dielectric layer 22 is formed before on the substrate 10, first the substrate 10 is made annealing treatment, to remove in shape
At the source electrode 20 in the substrate 10 of the memory block 12 and the external zones 11 and caused half when the drain electrode 21
The fracture or damage of conductor lattice.Although moreover, eliminating the side wall 18 of segment thickness, quilt in above-mentioned steps S4
The dielectric resistance to pressure of the side wall 18 (second silicon oxide layer 183 of i.e. part or all of thickness) of the segment thickness of removal
It can be with the dielectric pressure resistance performance of the interlayer dielectric layer 22 formed in step S6 very close to therefore, so that even if eliminating portion
The side wall 18 for dividing thickness, will not lead to the pressure-resistant reduced performance of semiconductor devices.High-density plasma can be used
Chemical vapor deposition process (HDP CVD) or high-aspect-ratio technique (HARP) form the interlayer dielectric layer 22 in the substrate 10
On, wherein high density plasma CVD technique is to synchronize to be precipitated (silane and oxygen in the same reaction chamber
Solid/liquid/gas reactions) and etching technics (sputtering of argon gas and oxygen), can be formed at a lower temperature the interlayer dielectric layer 22 in
On the substrate 10, and high-aspect-ratio technique is that chemical vapor deposition is carried out by thermal process, so will not bang because of plasma
Hit the damage to each layer structure on the substrate 10 of generation.
The interlayer dielectric layer 22 is formed after on the substrate 10, will continue to be formed in the interlayer dielectric layer 22
Multiple contact holes (not shown) can fill conductive contact plug (not shown) in each contact hole, wherein a part of institute
State in the interlayer dielectric layer 22 of the contact hole between the side wall 18 between neighboring gate structures (contact hole
Bottom-exposed goes out the surface of the substrate 10), the bottom of the conductive contact plug of this corresponding part and the source electrode 20 or
The electrical top contact of the drain electrode 21.During interlayer dielectric layer 22 described due to formation in the prior art, neighboring gates
Spacing very little (i.e. depth-to-width ratio is very big) between the side wall 18 between structure, so that the side between neighboring gate structures
It is easy to generate cavity in the interlayer dielectric layer 22 between wall 18, is that there is cavity in interlayer dielectric layer refering to Fig. 3, Fig. 3
Semiconductor devices schematic diagram, as can be seen from Figure 3, empty V1 is primarily generated at neighboring gate structures (the i.e. described first grid
Pole structure 13 and the second grid structure 14) between the side wall 18 between the interlayer dielectric layer 22 in.Work as generation
Cavity it is larger when, cavity may be by the interlayer dielectric layer between the side wall 18 between neighboring gate structures
Adjacent contact hole connection in 22, so that the conductive contact plug of filling in the contact hole bridges and occurs simultaneously
It is short-circuit to lead to semiconductor devices, and then product yield is caused to decline for connection.And in above-mentioned steps S4 of the invention, first pass through to
The side wall 18 of the segment thickness on the side wall of the second grid structure 14 on the memory block 12 is eliminated less, so that
Spacing between the side wall 18 between adjacent second grid structure 14 and the periphery on at least described memory block 12
It is described between adjacent first grid structure 13 and second grid structure 14 on 12 intersection two sides of area 11 and the memory block
Spacing between side wall 18 increases, i.e., so that the side between adjacent second grid structure 14 on at least described memory block 12
The adjacent first grid structure in depth-to-width ratio and the external zones 11 and 12 intersection two sides of the memory block between wall 18
Depth-to-width ratio between the side wall 18 between 13 and second grid structure 14 reduces, so that between neighboring gate structures
The quantity in the cavity generated in the interlayer dielectric layer 22 between the side wall 18 is reduced and size reduces, so that partly leading
The probability of body shorted devices reduces, and product yield is improved；And make high density plasma CVD technique
The process capability of board be improved, and make being delayed using node for high-aspect-ratio technique.
In addition, each step in the manufacturing method of above-mentioned semiconductor devices is not limited only to above-mentioned formation sequence, respectively
The sequencing adaptability of a step is adjusted.
In conclusion the manufacturing method of semiconductor devices provided by the invention, comprising: providing one has external zones and storage
The substrate in area, and the external zones and memory block have been respectively formed at least one gate structure；Lightly doped district is formed in the grid
In the substrate of pole structure two sides, and the lightly doped district part is located at the lower section of the gate structure；Side wall is formed in institute
It states on the side wall of gate structure；At least remove the described of the segment thickness on the side wall of the gate structure on the memory block
Side wall, so that the spacing between the side wall between the adjacent gate structure increases；With the gate structure and go
Except the side wall of the segment thickness is exposure mask, source electrode and drain electrode is formed in the gate structure two sides of the memory block
In the substrate, and the adjacent gate structure of the memory block shares the source electrode or the drain electrode, described to be lightly doped
Area partly overlaps with the source electrode and the drain electrode respectively；And interlayer dielectric layer is formed on the substrate, the interlayer is situated between
Matter layer covers the gate structure and the side wall.The manufacturing method of semiconductor devices of the invention makes adjacent gate structure
Between side wall between depth-to-width ratio reduce so that in the interlayer dielectric layer between side wall between adjacent gate structure
Cavity quantity reduce and size reduce so that product yield is improved.
One embodiment of the invention provides what a kind of manufacturing method using above-mentioned semiconductor devices of the invention manufactured
Semiconductor devices can be seen that the semiconductor devices includes substrate 10, gate structure (the i.e. first grid refering to Fig. 2 j from Fig. 2 j
Pole structure 13 and second grid structure 14), side wall 18, lightly doped district 17, source electrode 20, drain electrode 21 and interlayer dielectric layer 22, it is described
Substrate 10 has external zones 11 and memory block 12；The gate structure and the side wall 18 are formed in the external zones 11 and storage
In area 12, the side wall 18 is located on the side wall of the gate structure；The lightly doped district 17 is located at the gate structure two sides
The substrate 10 in, and 17 part of the lightly doped district is located at the lower section of the gate structure；The source electrode 20 and drain electrode 21
In the substrate 10 of the external zones 11 and memory block 12, and the source electrode 20 and the drain electrode 21 be located at it is described
In the substrate 10 of the two sides of gate structure, the adjacent gate structure of the memory block 12 share the source electrode 20 or
The drain electrode 21, the lightly doped district 17 partly overlap with the source electrode 20 and the drain electrode 21 respectively；And the interlayer is situated between
Matter layer 22 is formed on the substrate 10, and the interlayer dielectric layer 22 covers the gate structure and the side wall 18.
Semiconductor devices provided in this embodiment is described in detail referring next to Fig. 2 j:
The substrate 10 has external zones 11 and memory block 12.In the intersection of the external zones 11 and the memory block 12
Be also formed with fleet plough groove isolation structure 15, device of the fleet plough groove isolation structure 15 for that will be formed on the external zones 11 and
The device electric formed on the memory block 12 is kept apart, and the top surface of the fleet plough groove isolation structure 15 is higher than the periphery
The top surface of the substrate 10 in area 11 and the memory block 12.In addition, the external zones 11 and the memory block 12 pass through it
Its fleet plough groove isolation structure is isolated with other regions in semiconductor devices.
The gate structure and the side wall 18 are formed on the external zones 11 and memory block 12, and the side wall 18 is located at
On the side wall of the gate structure, the gate structure formed on the external zones 11 is first grid structure 13, described to deposit
The gate structure formed in storage area 12 is second grid structure 14.It is also formed between the substrate 10 and the gate structure
There is tunnel oxide 16；Isolating oxide layer (not shown) is also formed between the gate structure and the side wall 18.It is described to deposit
Usually there are multiple (a plurality of) second grid structures 14 to correspond to finally formed storage array in storage area 12, and described deposits
Each second grid structure 14 in storage area 12 includes 142 and of dielectric layer between the floating gate layer 141 of bottom-up formation, grid
Control grid layer 143.Also, the height of the second grid structure 14 on the memory block 12 is higher than first on the external zones 11
The height of gate structure 13, the interval between the side wall 18 on the memory block 12 between adjacent second grid structure 14
Depth-to-width ratio is greater than the depth-to-width ratio at the interval between the side wall 18 on the external zones 11 between adjacent first grid structure 13.
The lightly doped district 17 is located in the substrate 10 of the gate structure two sides, and 17 part of the lightly doped district
Positioned at the lower section of the gate structure.Improve shape on the memory block 12 and the external zones 11 by the lightly doped district 17
At MOS transistor device performance.
The source electrode 20 and drain electrode 21 are located in the external zones 11 and the substrate 10 of memory block 12, and the source electrode
20 and it is described drain electrode 21 be located at the gate structure two sides the substrate 10 in, the adjacent institute of the memory block 12
State second grid structure 14 share the source electrode 20 or it is described drain electrode 21, the lightly doped district 17 respectively with the source electrode 20 and institute
Drain electrode 21 is stated to partly overlap；The side wall 18 can be by from inside to outside (i.e. from the side wall of the gate structure from inside to outside)
First silicon oxide layer 181, silicon nitride layer 182 and the second silicon oxide layer 183 composition, first silicon oxide layer 181 and silicon nitride
The thickness of layer 182 successively can for 10nm~15nm (for example, 11nm, 14nm etc.) and 10nm~15nm (for example, 11nm,
14nm etc.), the thickness of second silicon oxide layer 183 can be less than 30nm.The material of the side wall 18 be also possible to nitrogen-oxygen-silicon,
Well known to a person skilled in the art one or more of other materials for silicon nitride or silicon carbide etc., and are not limited to bilayer
Structure or single layer structure, and well known to a person skilled in the art other laminated construction.
In addition, the adjacent side wall between two adjacent second grid structures 14 on the memory block 12
Spacing between 18 can be greater than or equal between two adjacent first grid structures 13 on the external zones 11
Spacing between the adjacent side wall 18.
The interlayer dielectric layer 22 is formed on the substrate 10, the interlayer dielectric layer 22 cover the gate structure and
The side wall 18.And multiple contact holes (not shown) is also formed in the interlayer dielectric layer 22, in each contact hole
Filled with conductive contact plug (not shown), wherein a part of contact hole is described between neighboring gate structures
In the interlayer dielectric layer 22 between side wall 18 (surface that the bottom-exposed of the contact hole goes out the substrate 10), this is corresponded to
The bottom of the partial conductive contact plug and the source electrode 20 or the electrical top contact of the drain electrode 21.Due to neighboring gates
Spacing very little (i.e. depth-to-width ratio is very big) between the side wall 18 between structure, so that the side between neighboring gate structures
It is easy to generate cavity in the interlayer dielectric layer 22 between wall 18, as shown in figure 3, cavity V1 is primarily generated at neighboring gates
In the interlayer dielectric layer 22 between the side wall 18 between structure.When the cavity of generation is larger, cavity may be incited somebody to action
Adjacent contact hole connection in the interlayer dielectric layer 22 between the side wall 18 between neighboring gate structures, into
And to fill conductive contact plug bridge joint in the contact hole and parallel connection occurs, cause semiconductor devices short-circuit, in turn
Product yield is caused to decline.And since the manufacturing method using semiconductor devices of the invention manufactures the semiconductor devices, make
Spacing between the side wall 18 between adjacent second grid structure 14 on at least described memory block 12 and described outer
Enclose the institute between the adjacent first grid structure 13 and second grid structure 14 on 12 intersection two sides of area 11 and the memory block
Spacing between side wall 18 is stated to increase, i.e., so that it is described between adjacent second grid structure 14 on at least described memory block 12
The adjacent first grid knot in depth-to-width ratio and the external zones 11 and 12 intersection two sides of the memory block between side wall 18
Depth-to-width ratio between the side wall 18 between structure 13 and second grid structure 14 reduces, so that between neighboring gate structures
The side wall 18 between the interlayer dielectric layer 22 in the quantity in cavity that generates reduce and size reduces so that half
The probability of conductor device short circuit reduces, and product yield is improved.
In conclusion semiconductor devices provided by the invention, comprising: substrate has external zones and memory block；Gate structure
And side wall, it is formed on the external zones and memory block, the side wall is located on the side wall of the gate structure；Lightly doped district,
In the substrate of the gate structure two sides, and the lightly doped district part is located at the lower section of the gate structure；Source
Pole and drain electrode, in the substrate of the external zones and memory block, and the source electrode and the drain electrode be located at it is described
In the substrate of the two sides of gate structure, the adjacent gate structure of the memory block shares the source electrode or the leakage
Pole, the lightly doped district partly overlap with the source electrode and the drain electrode respectively；And interlayer dielectric layer, it is formed in the lining
On bottom, the interlayer dielectric layer covers the gate structure and the side wall.Semiconductor devices of the invention makes adjacent grid
Depth-to-width ratio between side wall between the structure of pole reduces, so that the interlayer between the side wall between adjacent gate structure is situated between
The quantity in the cavity in matter layer is reduced and size reduces, so that product yield is improved.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of manufacturing method of semiconductor devices characterized by comprising
A substrate with external zones and memory block is provided, and the external zones and memory block have been respectively formed at least one grid
Structure；
Lightly doped district is formed in the substrate of the gate structure two sides, and the lightly doped district part is located at the grid
The lower section of structure；
Side wall is formed on the side wall of the gate structure；
The side wall at least removing the segment thickness on the side wall of the gate structure on the memory block, so that adjacent
The gate structure between the side wall between spacing increase；
Using the gate structure and the side wall for removing the segment thickness as exposure mask, source electrode and drain electrode is formed in the storage
In the substrate of the gate structure two sides in area, and the adjacent gate structure of the memory block shares the source electrode
Or the drain electrode, the lightly doped district partly overlap with the source electrode and the drain electrode respectively；And
Interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covers the gate structure and the side wall.
2. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that remove the described of the segment thickness
The step of side wall includes:
Patterned photoresist layer is formed on the substrate, the patterned photoresist layer exposes the memory block；With
And
Using the patterned photoresist layer as exposure mask, the side wall of the segment thickness on the memory block is only removed, so that
The spacing obtained between the side wall between the adjacent gate structure on the memory block increases；
Alternatively,
The side wall for removing the external zones and the segment thickness on the memory block simultaneously, so that the external zones and institute
It states spacing and the external zones between the side wall between the adjacent gate structure on memory block and described deposits
The spacing between the side wall between the adjacent gate structure on storage area intersection two sides increases.
3. the manufacturing method of semiconductor devices as claimed in claim 2, which is characterized in that form the source electrode and the drain electrode
Step in the substrate of the gate structure two sides of the memory block includes:
With the gate structure on the patterned photoresist layer and the memory block and remove the segment thickness
The side wall is exposure mask, carries out ion doping to the substrate of the memory block of the patterned photoresist layer exposure,
To form source electrode and drain electrode in the substrate of the gate structure two sides of the memory block；And
Remove the patterned photoresist layer.
4. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that forming the source electrode and the leakage
After pole is in the substrate of the gate structure two sides of the memory block and the interlayer dielectric layer is being formed in described
Before on substrate, source electrode and drain electrode is formed in the substrate of the gate structure two sides of the external zones.
5. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that thick using cleaning process removal part
The side wall of degree.
6. the manufacturing method of semiconductor devices as claimed in claim 5, which is characterized in that the side wall is by from inside to outside
One silica layer, silicon nitride layer and the second silicon oxide layer composition remove part or all of thickness using hydrogen fluoride solution cleaning
Second silicon oxide layer.
7. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that first silicon oxide layer, nitridation
The thickness of silicon layer and the second silicon oxide layer is followed successively by 10nm~15nm, 10nm~15nm and 30nm~40nm, and the hydrogen fluoride is molten
The amount of liquid can clean the side wall thicknesses of removal 40nm~50nm, so that second silicon oxide layer is completely removed.
8. the manufacturing method of the semiconductor devices as described in any one of claims 1 to 7, which is characterized in that described in formation
Gate structure is initially formed tunnel oxide in the external zones and the storage before on the external zones and the memory block
Qu Shang；Isolating oxide layer is also formed between the gate structure and the side wall.
9. a kind of semiconductor devices, which is characterized in that using the system of semiconductor devices described in any item of the claim 1 to 8
Make method manufacture, comprising:
Substrate has external zones and memory block；
Gate structure and side wall are formed on the external zones and memory block, and the side wall is located at the side wall of the gate structure
On；
Lightly doped district, in the substrate of the gate structure two sides, and the lightly doped district part is located at the grid
The lower section of structure；
Source electrode and drain electrode, in the substrate of the external zones and memory block, and the source electrode and drain electrode difference position
In the substrate of the two sides of the gate structure, the adjacent gate structure of the memory block share the source electrode or
The drain electrode, the lightly doped district partly overlap with the source electrode and the drain electrode respectively；And
Interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer covers the gate structure and the side wall.
10. semiconductor devices as claimed in claim 9, which is characterized in that two adjacent grid on the memory block
The spacing between the adjacent side wall between the structure of pole is greater than or equal to two adjacent grid on the external zones
The spacing between the adjacent side wall between the structure of pole.
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