KR100811280B1 - Method for fabricating of non-volatile memory device - Google Patents

Abstract

A method for fabricating a non-volatile memory device is provided to improve reliability and a distribution level of the non-volatile memory device by improving a wing spacer forming method. A tunnel layer pattern(312), a first conductive layer pattern(310), and a hard mask layer pattern are formed on a semiconductor substrate(300). A trench is formed in the semiconductor substrate. An isolation layer is formed to bury the trench. A wing spacer(320) is formed to cover the isolation layer and a part of a lateral surface of the hard mask layer pattern. An insulating layer pattern is formed to bury the wing spacer. The first conductive layer pattern is exposed by removing the hard mask layer pattern. A floating gate electrode(328) including the first and second conductive layer patterns is formed by forming the second conductive layer pattern having the same height as the height of the insulating layer pattern. The wing spacer is exposed by removing the insulating layer pattern. A shielding layer(336) is formed on the wing spacer and the floating gate electrode. A control gate electrode(342) is formed on the shielding layer.

Description

Nonvolatile memory device and method for manufacturing the same {Method for fabricating of non-volatile memory device}

1 and 2 illustrate a nonvolatile memory device and a problem in the related art.

3 to 14 are views for explaining a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a nonvolatile memory device.

NAND type flash memory devices are nonvolatile memory devices that can be electrically programmed and erased, and are widely used in electronic components that require information retention even when power is cut off. . The unit cell of the NAND type nonvolatile memory device has a basic structure consisting of a control gate and a floating gate, and performs a function of writing and erasing information depending on whether or not the floating gate is charged.

1 and 2 illustrate a nonvolatile memory device and a problem in the related art.

First, referring to FIG. 1, a nonvolatile memory device includes a structure in which a tunneling layer 102, a floating gate 104, a shielding layer 106, and a control gate 108 are stacked on a semiconductor substrate 100. Non-volatile memory having such a structure is a program and erase (Rease) operation is performed by the Fowler-Nordheim (FN) tunneling method. However, as the program and erase operations are repeatedly performed, a certain amount of electric charges are trapped at the interface of the semiconductor substrate 100 and the tunneling layer 102, and thus the distribution of the cell threshold voltage may be drastically reduced. In addition, the charge accumulation rate of the trap is also accelerated, and chip failure may occur.

Furthermore, the floating gate 104 and the semiconductor substrate 100 are driven by the high voltage applied to the control gate 108 and the high electric field applied to the well bias during the repetitive operation of program and erase. As the electric field is generated, a fail bit cell is generated in the repetitive operation of program and erase. In addition, data errors are increased due to widening of a high integration level, such as a multi-level chip (MLC), and thus chip defects may be accelerated and defects that are critical to reliability may occur. The effect of the electric field is larger when the cell size (cell size) is smaller.

Accordingly, a method of forming a wing spacer on the side of the gate to reduce the influence of the electric field has been proposed. To this end, a floating gate is formed on a semiconductor substrate, the insulating film for wing spacers is deposited on the floating gate, and the insulating film is selectively etched to partially cover the floating gate side to form wing spacers on both sides, and then the floating gate is formed. A covering shield layer is formed. However, when the floating gate is formed in this way and then the wing spacer is formed, as illustrated in FIG. 2, there is a problem in that a defect occurs in the floating gate profile.

Referring to FIG. 2, when the floating gate 200 is formed and then the wing spacer is formed, a phenomenon (A) in which the upper portion of the floating gate 200 is severely cut off and rounded in the process of forming the wing spacer, or As the sidewall of the 200 is excessively attacked and bent inward, the phenomenon B may be broken like a jar. As such, the profile of the floating gate 200 may be changed in the process of forming the wing spacers, thereby lowering the electrical characteristics of the nonvolatile memory device, and the data retention capability may also be reduced. Here, the parts not described in the drawing are the shielding layer 208 and the low resistance layer 210 in which the oxide film 202, the nitride film 204, and the oxide film 206 are stacked.

As the device is highly integrated, a design rule is reduced and the attack problem of the floating gate 200 has emerged as the most fatal problem in manufacturing a nonvolatile memory device. Accordingly, there is a need for a method capable of improving the attack problem of the floating gate to improve the reliability, repeatability, and distribution of the floating gate.

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a nonvolatile memory device capable of stably forming wing spacers while improving the reliability of the device by improving the attack problem of the floating gate and improving the electrical repeatability of the device. To provide.

In order to achieve the above technical problem, a method of manufacturing a nonvolatile memory device according to the present invention, forming a tunnel layer pattern, a first conductive film pattern and a hard mask film pattern to expose a predetermined region of the semiconductor substrate; Forming a trench in the semiconductor substrate with the films as a mask; Forming an isolation layer filling the trench; Forming a wing spacer covering a portion of side surfaces of the device isolation layer and the hard mask layer pattern; Forming an insulating layer pattern filling the wing spacers; Removing the hard mask layer pattern to expose the first conductive layer pattern; Forming a floating gate electrode including a first conductive layer pattern and a second conductive layer pattern by forming a second conductive layer pattern having the same height as the insulating layer pattern; Removing the insulating layer pattern to expose the wing spacers; Forming a shielding layer on the wing spacer and the floating gate electrode; And forming a control gate electrode on the shielding layer.

In the present invention, the first conductive film pattern may be formed as a laminated structure of an undoped polysilicon film, a dope polysilicon film or an undoped polysilicon film, and a dope polysilicon film.

The hard mask layer pattern may be formed of a nitride layer.

The device isolation layer may have a structure in which at least one of a spin on glass (SOG) film or a high density plasma oxide (HDP) film is stacked.

The wing spacer may include a high thermal oxide (HTO) or TEOS film (Tetra ethyl oxide silicon).

The insulating layer pattern may be formed of a material having an etching selectivity with respect to the wing spacers.

The hard mask layer pattern may be removed using a wet etching solution based on phosphoric acid (H ₃ PO ₄ ) at a process temperature of 0-250 ° C.

The shielding layer may be formed to include a structure in which an oxide film, a nitride film, and an oxide film are stacked.

The control gate electrode may be formed by stacking a metal film on a polysilicon film or a polysilicon film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

3 to 14 are views for explaining a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, a tunneling film 302 having a predetermined thickness is formed on the semiconductor substrate 300. Next, the first conductive film 304 and the hard mask film 306 are sequentially formed on the tunneling film 302.

The tunneling film 302 serves to allow charge carriers such as electrons or holes to be tunneled and injected into the floating gate under a constant bias. The tunneling film 302 may be formed by depositing or growing an oxide film having a predetermined thickness. In addition, the first conductive layer 304 may be formed of an undoped polysilicon layer to have a thickness of 10-500 Å. The hard mask layer 306 serves as an etching mask in an etching process for forming trenches in the subsequent semiconductor substrate 300. The hard mask film 306 may be formed of a nitride film, and may be formed to have a thickness of 100-4000 mm 3. On the other hand, the hard mask film 306 is formed at a temperature of 550 ℃ or more to crystallize the first conductive film 304 disposed below.

Referring to FIG. 4, the hard mask layer 306 is patterned to form a hard mask layer pattern 308 that defines a region in which a trench is to be formed. Subsequently, the first conductive layer 304 and the tunneling layer 302 are etched using the hard mask layer pattern 308 as an etch mask to form the first conductive layer pattern 310 and the tunneling layer pattern 312. Next, the trenches 314 having a predetermined depth are formed in the semiconductor substrate 300 using an etching mask. The trench 314 may be formed using a self align method.

Referring to FIG. 5, a first insulating film is deposited to sufficiently fill the trench 314 on the resultant trench 314, and then a planarization process, for example, chemical mechanical polishing (CMP). A process is performed to form the device isolation film 316. In this case, the insulating layer filling the trench 314 may include at least one oxide material, for example, a spin on glass (SOG) film or a high density plasma oxide (HDP).

Referring to FIG. 6, the entire surface of the device isolation film 316 formed on the semiconductor substrate 300 is etched to etch the device isolation film 316 by a predetermined thickness d from the exposed surface of the device isolation film. ) The etching of the device isolation layer 316 and the recess may be performed by wet etching using an etching solution.

Referring to FIG. 7, a second insulating layer 318 is deposited on the recessed device isolation layer 316. Next, a planarization process, for example, chemical mechanical polishing (CMP) or etchback process, is performed on the second insulating film 318 to planarize the surface of the second insulating film 318. Subsequently, the entire planarized second insulating film is etched to etch and recess a predetermined thickness from the exposed surface. The second insulating layer 318 may be formed of a dense material having a high film quality, and may be formed of a high density plasma oxide film (HDP).

Referring to FIG. 8, a wing spacer 320 is formed to cover a portion of the side surface of the hard mask layer pattern 308 and the second insulating layer 318.

Specifically, a spacer film is deposited on the semiconductor substrate 300 including the recessed second insulating film 318. The spacer film then forms a wing spacer that protects the side of the floating gate electrode. The spacer layer may include a high thermal oxide (HTO) or TEOS layer (Tetra ethyl oxide silicon) and may have a thickness of 10-1000 Å. Next, the spacer layer is selectively etched to form a wing spacer 320 covering a portion of the side surface of the hard mask layer pattern 308 and the second insulating layer 318.

In the exemplary embodiment of the present invention, the wing spacer is first formed before the floating gate electrode is formed, so that a phenomenon in which the upper portion of the floating gate electrode is severely cut and rounded in the process of forming the wing spacer (A, FIG. 2) occurs, or the floating gate electrode The sidewalls of the substrate may be excessively attacked and bent inward to prevent the occurrence of a jar-shaped phenomenon (B, FIG. 2).

Referring to FIG. 9, a third insulating layer 322 filling the wing spacer 320 is formed.

The third insulating layer 322 may be formed of a material having an etch selectivity with respect to the wing spacer 320, for example, an SOG film or a Phosphorus silicate glass (PSG) film. Subsequently, a planarization process such as a chemical mechanical polishing (CMP) process or an etch back process is performed on the third insulating film 322 until the surface of the hard mask film pattern 308 is exposed.

Referring to FIG. 10, the hard mask layer pattern 308 is removed by performing wet etching on the semiconductor substrate 300. As the hard mask layer pattern 308 is removed by the wet etching process, the surface of the first conductive layer pattern 310 is exposed. The wet etching process may be performed using a wet etching solution based on phosphoric acid (H ₃ PO ₄ ) at a process temperature of 0-250 ° C. Here, the third insulating layer 322 and the wing spacer 320 remain without being removed.

Referring to FIG. 11, the hard mask layer pattern 308 is removed to deposit a second conductive layer 324 filling the exposed portion of the first conductive layer pattern 310. The second conductive film 324 may be formed in a laminated structure of an undoped polysilicon film, a dope polysilicon film, or an undoped polysilicon film and a dope polysilicon film at a temperature of 500-1000 ° C.

Referring to FIG. 12, a planarization process is performed on the second conductive film 324 to form a second conductive film pattern 326 so that the first conductive film pattern 310 and the second conductive film pattern 326 are stacked. A floating gate electrode 328 having a structured structure is formed. The planarization process may be performed using a chemical mechanical polishing (CMP) process or an etch back process.

As such, by forming the floating gate electrode 328 in a state where the wing spacer 320 is formed first, the upper portion of the floating gate electrode is severely cut off or rounded in the process of forming the wing spacer, or the sidewall of the floating gate electrode is attacked. You can prevent it.

Referring to FIG. 13, the third insulating layer 322 is removed by performing wet etching on the semiconductor substrate 300. The wing spacer 320 is exposed while the third insulating layer 322 is removed by the wet etching. Here, in the process of etching the third insulating film 322, the third insulating film 322 is different from the wing spacer 320 and the etching selectivity is not removed, the etching is performed when the surface of the wing spacer 322 is exposed Is stopped.

Referring to FIG. 14, a shielding layer 336 is formed on the exposed wing spacer 320 and the floating gate electrode 328 to prevent the transfer of charge from the floating gate electrode 328 to the upper electrode to be subsequently formed. . The shielding layer 336 may be formed of an insulating film, and in the exemplary embodiment of the present invention, the shielding layer 336 is formed of an ONO structure in which an oxide 330, a nitride 332, and an oxide 334 are stacked. .

Next, a material layer for forming the control gate electrode 342 is deposited on the shielding layer 336. The control gate electrode 342 may be formed of the polysilicon film 338 or, in some cases, by laminating the metal film 340 on the polysilicon film 338. When the control gate electrode 342 is formed of the polysilicon film 338, a low resistance film made of, for example, tungsten silicide (WSi) on the polysilicon film 338 to reduce the resistance of the gate line (not shown). ) May be formed.

In the nonvolatile memory device according to the present invention, the wing spacers are first formed before the floating gate electrodes are formed, thereby preventing the top of the floating gate electrodes from being severely cut off and rounded. In addition, since the floating gate electrode is formed after the wing spacer is formed, the sidewall of the floating gate electrode may be prevented from being attacked.

As described above, according to the method of manufacturing the nonvolatile memory device according to the present invention, the wing spacer forming method can be improved to improve the reliability and distribution level of the nonvolatile memory device. In addition, electrical repeatability of the nonvolatile memory device may be improved. In addition, the wing spacers can be stably formed.

Claims (9)

Forming a tunnel layer pattern, a first conductive layer pattern, and a hard mask layer pattern exposing a predetermined region of the semiconductor substrate; Forming a trench in the semiconductor substrate with the films as a mask; Forming an isolation layer filling the trench; Forming a wing spacer covering a portion of side surfaces of the device isolation layer and the hard mask layer pattern; Forming an insulating layer pattern filling the wing spacers; Removing the hard mask layer pattern to expose the first conductive layer pattern; Forming a floating gate electrode including a first conductive layer pattern and a second conductive layer pattern by forming a second conductive layer pattern having the same height as the insulating layer pattern; Removing the insulating layer pattern to expose the wing spacers; Forming a shielding layer on the wing spacer and the floating gate electrode; And And forming a control gate electrode on the shielding layer. The method of claim 1, The first conductive film pattern is a undoped polysilicon film, a doped polysilicon film or a undoped polysilicon film, and a method of manufacturing a nonvolatile memory device, characterized in that formed in a laminated structure of the dope polysilicon film. The method of claim 1, The hard mask film pattern is a method of manufacturing a nonvolatile memory device, characterized in that formed by the nitride film. The method of claim 1, The device isolation film is a method of manufacturing a nonvolatile memory device, characterized in that the SOG (Spin on glass) film or a high density plasma oxide (HDP; high density plasma oxide) of at least one film is formed in a stacked structure. The method of claim 1, The wing spacer may include a high thermal oxide (HTO) film or a TEOS film (Tetra ethyl oxide silicon). The method of claim 1, And the insulating layer pattern is formed of a material having an etch selectivity with respect to the wing spacers. The method of claim 1, The hard mask layer pattern is removed using a wet etching solution based on phosphoric acid (H ₃ PO ₄ ) at a process temperature of 0-250 ℃. The method of claim 1, And the shielding layer is formed to include a structure in which an oxide film, a nitride film, and an oxide film are stacked. The method of claim 1, The control gate electrode may be formed by stacking a metal film on a polysilicon film or a polysilicon film.

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