KR20080060347A - Method for manufacturing non-volatile memory device - Google Patents

Abstract

A method for manufacturing a non-volatile memory device is provided to prevent generation of leakage current by securing a constant interval between control gates. A gate insulating layer(31), a conductive layer(32) for gate electrode, and a pad nitride layer are formed on a substrate(30). A trench is formed by etching the pad nitride layer, the conductive layer, the gate insulating layer, and a part of the substrate. A first insulating layer for isolation layer is buried into the trench. A void generated from the first insulating layer manufacturing process is exposed to the outside by recessing the first insulating layer. The pad nitride layer is removed. A second insulating layer for isolation layer is formed within the void. An effective height of the isolation layer is controlled by recessing the first and second insulating layers.

Description

Non-volatile memory device manufacturing method {METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICE}

1A to 1F are cross-sectional views illustrating a method of fabricating a flash memory device using an advanced self aligned-shallow trench isolation (ASA-STI) scheme according to the related art.

2 is a Transmission Electron Microscope (TEM) photograph showing a flash memory device formed according to the prior art.

3A to 3E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

30 substrate 31 gate insulating film

32: conductive film for floating gate 33: buffer oxide film

34 pad nitride film 35 SOD film

36, 38, 38A, 38B: HDP film 37, 37A: device isolation film

V: void

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device manufacturing technology, and more particularly to a non-volatile memory device, and more particularly to a flash memory device manufacturing method.

Recently, the demand for flash memory devices that can be electrically programmed and erased among nonvolatile memory devices and that does not require a refresh function for rewriting data at regular intervals is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

On the other hand, as the design rule is reduced due to the high integration of flash memory devices, a shallow trench isolation (STI) scheme for separating various devices has been newly proposed. ASA-STI (Advanced Self Aligned Shallow Trench Isolation) is the most popular STI scheme. The ASA-STI scheme has been applied to the formation of floating gates of flash memory devices due to the reduction of the overlay margin between the active region and the floating gate. Hereinafter, a general ASA-STI scheme will be described with reference to FIGS. 1A to 1F.

1A to 1F are cross-sectional views illustrating a method of manufacturing a flash memory device using the ASA-STI scheme according to the prior art.

First, as shown in FIG. 1A, a tunnel oxide film 11, a floating silicon polysilicon film 12, a buffer oxide film 13, and a pad nitride film 14 are sequentially formed on the semiconductor substrate 10.

Subsequently, a portion of the pad nitride film 14, the buffer oxide film 13, the polysilicon film 12, the tunnel oxide film 11, and the substrate 10 is etched to form a trench having a predetermined depth. Next, a spin on dielectric 15 (hereinafter referred to as an SOD film) is deposited on the device isolation insulating film to fill the trench.

Subsequently, as shown in FIG. 1B, a chemical mechanical polishing (hereinafter referred to as CMP) process is performed to remove the SOD film 15 (see FIG. 1A) on the pad nitride film 14. As a result, an isolated SOD film 15A is formed in the trench.

Subsequently, as shown in FIG. 1C, a wet etching process is performed to recess the SOD film 15B to a predetermined depth. For example, the SOD film 15B is recessed to the bottom of the tunnel oxide film 11. In the wet etching process, the inlet of the trench is partially covered by the foreign material R buried in the wafer surface as in the same figure.

Subsequently, as shown in FIG. 1D, a USG (Un-doped Silicate Glass) film is deposited on the SOD film 15B recessed so that the trench is buried as an insulating film for device isolation in a high density plasma manner. (Hereinafter referred to as HDP film) is deposited. Here, the reason for depositing the HDP film 16 again after recessing the SOD film 15B is that the SOD film 15B has a material property that the wet etching rate is fast and nonuniform, so that the effective height of the device isolation film is applied when the wet etching process is applied. This is because there is a problem in that the (Effective Field Oxide Height, EFH) is non-uniform, so that there is a problem in forming a device isolation film as a single film of the SOD film 15B.

Subsequently, as shown in FIG. 1E, a CMP process is performed to remove the HDP film 16 (see FIG. 1D) on the pad nitride film 14. As a result, an isolated HDP film 16A is formed in the trench.

Subsequently, as shown in FIG. 1F, after the wet etching process is performed to recess the HDP film 16B to a predetermined depth, the pad nitride film 14 is removed. Thereafter, the wet etching process is performed again to recess the HDP film 16B to a predetermined depth, thereby finally controlling the effective height of the device isolation film. As a result, the device isolation film 17 having the stacked structure of the SOD film 15B and the HDP film 16B is completed. In particular, during the wet etching process of the HDP film 16B, the buffer oxide film 13 is removed together.

However, the following problems occur when applying the flash memory device manufacturing method according to the prior art described above.

First, as shown in FIG. 1D, voids V are generated when the HDP film 16 is deposited. This is because a part of the trench inlet is covered by the foreign substance R generated as shown in FIG. 1C, and the HDP layer 16 may not be evenly embedded. In particular, the voids V increase in size during the subsequent wet etching process as shown in FIG. 1F.

FIG. 2 is a transmission electron microscope (TEM) photograph showing a flash memory device in which a dielectric film 18 and a control gate 19 are formed on an entire structure including a device isolation film 17 in which voids V are generated. to be.

As shown in FIG. 2, when voids V are present in the device isolation layer 17, the voids V deteriorate an insulating property of the device isolation layer, and thus, short the adjacent active shorts. cause. In addition, when the void V is increased in this manner, a certain interval between the substrate 10 and the control gate 19 of the active region may not be maintained, thereby causing a leakage current.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and has the following objects.

First, it is an object of the present invention to provide a method of manufacturing a nonvolatile memory device capable of preventing voids from occurring when the device isolation layer is formed to prevent short circuit between neighboring actives.

Second, another object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of suppressing generation of leakage current by suppressing generation of voids when forming an isolation layer.

According to an aspect of the present invention, a gate insulating film, a conductive film for a gate electrode, and a pad nitride film are formed on a substrate, and the pad nitride film, the conductive film, the gate insulating film, and a portion of the substrate are etched. Forming a trench, forming a first insulating film for a device isolation film embedded in the trench, recessing the first insulating film to expose voids generated when the first insulating film is formed; Removing the pad nitride film, forming a second insulating film for the device isolation film embedded in the void, and controlling the effective height of the device isolation film by recessing the first and second insulating films. A method of manufacturing a volatile memory device is provided.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3A to 3E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention. As a representative example, a method of manufacturing a flash memory device will be described.

First, as shown in FIG. 3A, a gate insulating film 31, a conductive film 32 for a gate electrode (eg, a floating gate), a buffer oxide film 33, and a pad nitride film 34 are sequentially formed on the substrate 30. ). Here, the gate insulating layer 31 functions as a tunnel oxide layer of a general flash memory device and may be formed of an oxide layer material including an oxide layer or a nitride layer. In addition, the conductive film 32 is preferably formed of doped or undoped polysilicon.

Subsequently, portions of the pad nitride film 34, the buffer oxide film 33, the conductive film 32, the gate insulating film 31, and the substrate 30 are etched to form trenches (not shown) having a predetermined depth.

Subsequently, although not shown in the drawing, a monthly oxide film may be further formed on the inner surface of the trench. It is formed to compensate for damage to the inner wall and the bottom surface of the trench during the etching process, to round the upper edge portion, and to reduce the critical dimension (CD) of the active region.

Subsequently, a SOD film 35 is deposited as an insulating film for device isolation so that the trench is buried.

Subsequently, a wet etching process is performed to recess the SOD film 35 to a predetermined depth. For example, the SOD film 35 is recessed to the bottom of the gate insulating film 31.

Subsequently, the HDP film 36 is again deposited on the SOD film 35 using the device isolation insulating film to fill the trench. Here, the reason for depositing the HDP film 36 again after recessing the SOD film 35 is that the SOD film 35 has a material property that the wet etch rate is fast and nonuniform, so that the effective height of the device isolation film is applied when the wet etching process is applied. This is because there is a problem in that the (Effective Field Oxide Height, EFH) is uneven, so that there is a problem in forming a device isolation film as a single film of the SOD film 35.

Next, the CMP process is performed to remove the HDP film 36 on the pad nitride film 34. As a result, an isolation layer 37 is formed in the trench. However, when the HDP film 36 is deposited, voids V occur as in the same plane. This is because, as described above, the inlet of the trench is partially covered by the foreign matter on the wafer surface during the wet etching of the SOD film 35.

Subsequently, as shown in FIG. 3B, a wet etching process using an oxide etching solution is performed to recess the device isolation layer 37 to a predetermined depth. For example, the device isolation layer 37 is recessed by about 200 to about 500 mW by a wet etching process using a buffered oxide etchant (BOE) or HF. As a result, the void V is exposed to the outside.

Subsequently, a wet etching process using a phosphoric acid solution (H ₃ PO ₄ ) is performed to remove the pad nitride layer 34 (see FIG. 3A).

Subsequently, as shown in FIG. 3C, an HDP film 38 is deposited over the entire structure so that the voids V are embedded. Here, the HDP film 38 is preferably deposited to a thickness of 50 ~ 200Å by using a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition) method.

Subsequently, as shown in FIG. 3D, a CMP process is performed to remove all the oxide material on the conductive film 32. That is, the CMP process using polysilicon, which is a constituent material of the conductive film 32, as a polishing stop film is performed to remove the HDP films 36 and 38 and the buffer oxide film 33 on the conductive film 32. As a result, the HDP film 38A is formed in the void V in an isolated form.

In particular, in such a CMP process, a slurry having a high polishing selectivity of an oxide film relative to polysilicon is used. For example, a slurry using ceria, which has a slow polishing rate on a silicon material, is used as an abrasive, and it is preferable to adjust the pH of the slurry to about 6-8. In addition, in order to significantly reduce the polishing rate for polysilicon, it is preferable to adjust the dilution ratio of the deionized water (DIW) to the abrasive to 1:10 to 1: 100.

Subsequently, as shown in FIG. 3E, an etching process is performed to recess the device isolation layer 37A to a predetermined depth. Through this, the effective height of the device isolation film can be appropriately controlled. Here, the etching process may be performed in a wet or dry manner.

In the etching process for controlling the effective height of the device isolation film, since the void is already embedded by the HDP film 38B as shown in FIG. 3D, the size of the device is increased as the void is exposed to the outside. You will not. Accordingly, the device isolation film 37A can perform an insulating role between normally active neighbors and prevent short between neighboring actives.

In addition, a certain distance may be secured between the substrate 30 in the active region and a control gate (not shown) to be formed through a subsequent process to prevent leakage current.

Subsequently, although not shown in the drawings, a dielectric film and a control gate are formed over the entire structure according to a general flash memory device manufacturing technique.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects are obtained.

First, according to the present invention, by forming a separate device isolation layer that fills voids in advance before controlling the effective height of the device isolation film in which voids are generated, the voids are exposed to the outside during an etching process for controlling the effective height of the device isolation film. Can be prevented. Therefore, shorts between neighboring actives can be prevented.

Second, according to the present invention, by forming the device isolation layer filling the voids as described above, during the etching process for controlling the effective height of the device isolation layer, the voids are prevented from being exposed to the outside, thereby controlling the substrate to be formed subsequently with the active region. A certain distance between the gates can be secured. Through this, leakage current generation of the device can be prevented.

Claims (12)

Forming a gate insulating film, a conductive film for the gate electrode, and a pad nitride film on the substrate; Etching a portion of the pad nitride film, the conductive film, the gate insulating film, and the substrate to form a trench; Forming a first insulating film for a device isolation layer embedded in the trench; Recessing the first insulating layer to expose voids generated when the first insulating layer is formed; Removing the pad nitride film; Forming a second insulating film for a device isolation film embedded in the void; And Recessing the first and second insulating layers to control an effective height of the device isolation layer Nonvolatile memory device manufacturing method comprising a. The method of claim 1, And forming a buffer oxide film between the conductive film and the pad nitride film. The method of claim 1, Before forming the first insulating film, Depositing a third insulating film for an isolation layer to fill the trench; And Recessing the third insulating film to the bottom of the gate insulating film Non-volatile memory device manufacturing method further comprising. The method of claim 3, wherein The third insulating film is a spin-on insulating film manufacturing method of a nonvolatile memory device. The method according to any one of claims 1 to 4, Forming the second insulating film, Depositing the second insulating film over the entire structure so that the voids are buried; And Performing a chemical mechanical polishing process to remove the first and second insulating films on the conductive film Nonvolatile memory device manufacturing method comprising a. The method of claim 5, wherein The chemical mechanical polishing process is performed using a slurry having a high polishing selectivity of the first and second insulating films with respect to the conductive film. The method of claim 6, The chemical mechanical polishing process is a non-volatile memory device manufacturing method made by adjusting the pH of the slurry to 6 ~ 8. The method of claim 6, The conductive film is formed of polysilicon. The method of claim 8, The first and second insulating layers are formed of an HDP USG (Un-doped Silicate Glass) film which is deposited by a high density plasma method. The method of claim 9, In the chemical mechanical polishing process, ceria having a slower polishing rate with respect to the polysilicon than the HDP USG film is used as an abrasive. The method of claim 10, The chemical mechanical polishing process is a non-volatile memory device manufacturing method by adjusting the dilution ratio of the deionized water (deionized water) to the abrasive to 1:10 ~ 1: 100. The method according to any one of claims 1 to 4, Recessing the second insulating film, A method of manufacturing a nonvolatile memory device by performing a wet or dry etching process.

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