KR20080063891A - Method for manufacturing storagenode contact in semiconductor device - Google Patents

Abstract

A method for forming a storage node contact of a semiconductor device is provided to perform a hard mask etching process and an SNC(Storage Node Contact) etching process in-situ in a dielectric etching chamber by employing a nitride based hard mask instead of a poly silicon layer. A first dielectric(33) is formed on an upper portion of a structure where a landing plug contact(34) is formed. A bitline pattern, where a bitline conductive layer and a bit line hard mask(37) are laminated in turn, is formed on a surface of the first dielectric. A second dielectric(35) is formed on the whole surface until a gap of the bitline pattern is filled. The second dielectric is planarized until an upper portion of the bit line pattern is exposed. A hard mask is deposited on an upper portion of the second dielectric by using a nitride based material. The hard mask is etched to form a hard mask pattern. The second dielectric is partially etched in the same chamber with the hard mask pattern formation process in-situ to form a first opening unit(41) by using the hard mask pattern as an etching barrier layer. A width of the first opening unit is expanded in the chamber. A capping layer(42) is formed to change an upper profile of the bitline pattern exposed by the first opening unit into a rectangle profile. A spacer(32) is formed on the capping layer. A spacer etching is performed on the spacer until the surface of the landing plug contact is exposed to form a second opening unit(44). A storage node contact is formed to be gap-filled in a storage node contact hole comprised of the first and second opening units.

Description

METHODS FOR MANUFACTURING STORAGENODE CONTACT IN SEMICONDUCTOR DEVICE}

1A to 1C illustrate a method of forming a storage node contact using a line type self-aligned contact etching according to the prior art.

2A and 2B are SEM photographs showing a bitline profile according to the prior art.

3A to 3F illustrate a method of manufacturing a storage node contact according to an embodiment of the present invention.

4A and 4B are SEM photographs showing a bit line profile according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

30: gate conductive layer 31: gate hard mask

32: gate spacer 33: first interlayer insulating film

34: landing plug contact 35: second interlayer insulating film

36: bit line conductive layer 37: bit line hard mask

38: third interlayer insulating film 39a: hard mask polysilicon pattern

41: primary opening 42: protective film

43: etching stop film 44: secondary opening

45: storage node contact

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of forming a floating gate of a flash memory device having a double layer structure.

Recently, the demand for flash memory devices that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

NAND flash memory devices (NAND-) in which a plurality of memory cells are connected in series (ie, structures in which drains or sources are shared with each other) to form a string for high integration of memory devices. type flash memory device) has been developed. Unlike NOR-type flash memory devices, NAND flash memory devices are memory devices that read information sequentially. The NAND flash memory device is programmed and erased by controlling the threshold voltage (Vt) of the memory cell while injecting or emitting electrons into a floating gate using an F-N tunneling method.

Currently, a scheme for isolating devices in a 70nm NAND flash memory device uses a thin polysilicon film that functions as a lower layer of the floating gate to ensure the quality of the gate insulating film (or tunnel oxide film). Self-aligned Shallow Trench Isolation (SA-STI) process, which first defines the profile of the lower floating gate, and then performs device isolation, is widely used.

Hereinafter, the SA-STI process generally applied to NAND flash memory devices will be described.

First, as shown in FIG. 1A, a gate insulating film 11 and a poly silicon layer (hereinafter, referred to as a first polysilicon film) 12 as a lower layer for a floating gate are formed on a semiconductor substrate 10. And a pad nitride layer 13 are sequentially formed.

Subsequently, as illustrated in FIG. 1B, the pad nitride film 13, the first polysilicon film 12, the gate insulating film 11, and the substrate 10 are sequentially etched by performing a photo process and an etching process. As a result, a plurality of trenches 14 having a constant slope are formed in the substrate 10 to define an active region and a field region.

Subsequently, as illustrated in FIG. 1C, the HDP (High Density Plasma) oxide film is deposited so that the trench 14 is embedded and then planarized by performing a chemical mechanical polishing (CMP) process. As a result, an isolation layer 15 is formed in the trench 14.

Next, the pad nitride film 13 is removed to protrude a part of the device isolation film 15.

Next, as shown in FIG. 1D, a pre-cleaning process 16 is performed to remove a native oxide (not shown) formed on the first polysilicon film 12.

Next, as shown in FIG. 1E, a polysilicon film 17 (hereinafter referred to as a second polysilicon film), which is an upper layer of the floating gate, is deposited on the entire structure including the first polysilicon 12.

Subsequently, the second polysilicon layer 17 is etched by performing a photo process and an etching process to form floating gates (not shown) that are adjacent to each other by the device isolation layer 15.

As described above, in the SA-STI process according to the related art, the deposition process of the first polysilicon film 12 and the second polysilicon film 17 is not continuously performed in-situ. As discontinuously progressing to ex-situ, a natural oxide film is formed on the surface of the first polysilicon film 12 exposed after the pad nitride film 13 is removed. In order to remove the natural oxide film as shown in FIG. 1D, the pre-cleaning process 16 is performed. However, there is a limitation in removing the natural oxide film, and the chemical oxide film (chemical oxide film) is formed on the surface by a cleaning solution during the cleaning process. oxide) is formed.

Due to such a natural oxide film, electrons are trapped during device operation. The mechanism by which electrons are trapped in the natural oxide film is shown in FIG. 2.

As shown in FIG. 2, electrons are trapped in the natural oxide film, and a bit fail in which a threshold voltage falls due to the trapped electrons is generated. In addition, the natural oxide film may act as a parasitic capacitor to cause a drop in the initial applied voltage. As described above, the adverse effect of the natural oxide film deteriorates the overall uniformity in the distribution of important cell threshold voltages among the characteristics of the flash memory device, thereby deteriorating the device characteristics.

FIG. 3 is a diagram illustrating a cell threshold voltage for a number of cells during an erase operation of a flash memory device, and shows a cell in which the cell threshold voltage has dropped.

FIG. 4 is a diagram illustrating an interface between the first polysilicon film 12 and the second polysilicon film 17 by HR TEM after the process of FIG. 1E. A natural oxide layer is formed at about 18 GPa. When the delay time until the deposition of the second polysilicon film 17 after the pre-cleaning process 16 performed in FIG. 1D occurs, the thickness of the natural oxide film is further increased. As described above, even though the pre-cleaning process 16 is performed in FIG. 1D, the reason why the natural oxide film exists is that the chemical oxide film remains without being removed to a thickness of ˜5 GPa.

FIG. 5 is a diagram illustrating a secondary ion mass spectrometry (SIMS) profile to confirm a phosphorus (P) doping profile according to whether or not the pre-cleaning process 16 is performed in FIG. 1D.

Referring to FIG. 5, # 01 is a wafer deposited by a deposition process without a thermal budget, and the P concentration in the bulk of the second polysilicon 17 represents about 3.2E20 atoms / cc. The P diffusion into the first polysilicon film 12 has not yet occurred. Here, the second polysilicon film 17 is formed of a P doped polysilicon film.

# 02 is a wafer which has undergone the pre-cleaning process 16. When the natural oxide film thickness of the interface between the first and second polysilicon films 12 and 17 is 18 k as described above, the first polysilicon film 12 The P concentration in the film is almost the same as the P concentration in the second polysilicon film 17. The P distribution separated at the interface of the natural oxide film also shows almost similar values.

# 03 shows a P distribution in the interface between the first and second polysilicon films 12 and 17 when the natural oxide film is ˜30 μs or more. The P concentration in the first polysilicon film 12 is about 5.6E19 atoms / cc. Only half of 1.1E20 atoms / cc in the second polysilicon film 17.

As described with reference to FIG. 5, as the thickness of the natural oxide film increases in the interface between the first and second polysilicon films 12 and 17, the P doping profile shows a large difference. The doping level difference between the two polysilicon films 12 and 17 is obtained.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and has the following objects.

First, the present invention provides a method for forming a storage node contact of a semiconductor device capable of in-situ etching by omitting the KO process by changing the polyhard mask, which is a SAC problem, to a nitride film-based material during the line type storage node contact forming process. Its purpose is to.

Another object of the present invention is to provide a method for forming a storage node contact of a semiconductor device capable of securing a stable bit line spacer forming process by depositing a capping layer on an upper portion of a bit line during a storage node contact process.

According to an aspect of the present invention, there is provided a method of forming a first insulating layer on an upper structure of a landing plug contact, and forming a bit line conductive layer and a bit line hard mask on a predetermined surface of the first insulating layer. Forming a stacked bit line pattern in a sequence; forming a second insulating film on the entire surface until the bit line pattern is filled; and planarizing the second insulating film until an upper portion of the bit line pattern is exposed. Depositing a hard mask using a nitride based material on the second insulating layer, forming a hard mask pattern by etching the hard mask, and forming the hard mask pattern as an etch barrier layer. Forming a first opening by partially etching the second insulating layer in the same chamber in-situ with a mask pattern forming process; Expanding a width of the primary opening in the space, forming a protective film for changing a top profile of the bit line pattern exposed by the primary opening into a rectangular profile, and forming a spacer on the protective film; Forming a secondary opening by performing spacer etching on the spacer until the surface of the landing plug contact is exposed, and forming a storage node contact embedded in a storage node contact hole formed of the first and second openings; It provides a method for forming a storage node contact of a semiconductor device comprising the step.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if a layer is said to be "on" another layer or substrate it may be formed directly on another layer or substrate. Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3A to 3F are cross-sectional views illustrating a method of forming a storage node contact of a semiconductor device according to an embodiment of the present invention. The left side of the figure is a diagram cut in the direction crossing the bit line pattern, and the right side is a figure cut in the direction parallel to the bit line pattern. Hereinafter, the cross-sectional views of the process in two directions are shown together for detailed description.

First, as shown in FIG. 3A, a first interlayer insulating film 33 is formed on a gate pattern having the gate conductive layer 30, the gate hard mask 31, and the gate spacer 32, and then the first interlayer. The insulating film 33 is planarized through CMP.

Subsequently, the first interlayer insulating film 33 between the gate patterns is selectively etched, and a landing plug contact 34 is formed thereon.

Next, a second interlayer insulating film 35 is deposited on the entire surface including the landing plug contact 34.

Subsequently, a bit line pattern having a shape intersecting with the gate pattern is formed on a predetermined surface of the second interlayer insulating film 35. At this time, the bit line pattern is stacked in the order of the bit line conductive layer 36 and the bit line hard mask 37, the bit line conductive layer 36 is a single material or a plurality of materials selected from W, Ti, WN or WSi. The bit line hard mask 37 is formed of SiON or SiN.

Subsequently, the third interlayer insulating film 38 is deposited on the entire surface of the bit line pattern by using an HDP (High Density Plasma) oxide film to fill the gap between the bit line patterns, and then planarized through CMP to the upper part of the bit line pattern.

Subsequently, the hard mask 39 is formed of a nitride film such as Si ₃ N ₄ and SiO _N having a high etching selectivity with SRON (Silicon Rich Oxinitride) or an oxide film on the planarized third interlayer insulating film 38. A contact mask 40 of (Line type) is formed.

As shown in FIG. 3B, the hard mask 39 is etched using the contact mask 40 as an etch barrier layer using an etching chamber for dielectric to form a line type hard mask pattern 39a. Afterwards, the hard mask pattern 39a is partially etched into the etch barrier layer in-situ to form a primary opening 41, and a wet etch is continuously performed. The width of the difference opening 41 is expanded.

The etch recipe for forming the hard mask pattern 39a includes a fluorine source gas such as a pressure of 10 to 100 mTorr, a power of 100 to 2000 W, a CxFy of 1 to 100 sccm, and a CxHyFz of 1 to 100 sccm. , 1-100 sccm of O ₂ , 1-100 sccm of N ₂ , and 1-1000 sccm of Ar reaction gas. Here, x, y, z are natural numbers or rational numbers including a decimal point. In addition, during the first partial etching, the etching process proceeds to an etching condition having a selectivity to the nitride film. In the wet etching process of expanding the width of the primary opening 41, the etching condition is a hydrofluoric acid solution of 20: 1 to 300: 1, that is, BOE (Buffered Oxide Etchant) or DHF (Dilute HF).

Thereafter, the contact mask 40 is removed.

Subsequently, as shown in FIG. 3C, the passivation layer 42 is formed on the entire surface including the primary opening 41 having a widened width. In this case, the passivation layer 42 may be deposited to an appropriate thickness on the bit line pattern. Preferably, the passivation layer 42 is formed of an oxide layer or a nitride layer. Preferably, the film is formed using a USG (Undoped Silicate Glrass) film at a thickness of 1000 mW or less, preferably 400 to 900 mW. The USG film is an oxide film having poor step coverage. When the USG film is deposited, a USG film having a large thickness is deposited on the bit line pattern to correct the profile. That is, the profile of the bit line hard mask 37 has a thin upper profile and a thick trapezoidal profile at the bottom, while depositing the protective layer 42 becomes a rectangular profile due to the protective effect. In other words, the protective film 42 is introduced for the purpose of profile correction.

On the other hand, the protective film 42 may be formed of a nitride film material having a weak step coverage.

As shown in FIG. 3D, a nitride film spacer 43 for the purpose of reinforcing the spacers on the sidewalls of the bit line patterns is formed on the entire surface including the protective film 42 to a thickness of 50 to 500 mW. Here, the nitride film spacer 43 is made of SiON or SiN.

As shown in FIG. 3E, the SNC spacer is etched to open the secondary opening 44. At this time, the loss of the bit line hard mask 37 is greatly reduced due to the passivation layer 42 deposited on the bit line pattern. That is, the protective film 42 functions as a sacrificial film.

The secondary openings 44 may etch the third interlayer insulating film 38 and the second interlayer insulating film 35 under the first opening 41 while etching the spacers of the nitride film spacer 43. 44). Here, the secondary opening 44 exposes the landing plug contact 34, and when the secondary opening 44 is formed, the protective layer 42 is etched in situ at the same time as the etching of the interlayer insulating layers. The spacers 43 remain on the sidewalls of the bit line hard mask 37 in the form of contact spacers.

The primary opening 41 and the secondary opening 44 become storage node contact holes, and an etching process for forming the primary opening 41 is referred to as 'primary storage node contact etching', and the secondary opening 44 ) The etching process for forming is called 'secondary storage node contact etching'.

As a result of the secondary storage node contact etching, the upper profile of the bit line pattern is a rectangular profile (see 'X'). As such, the stable oxide film thickness (see 'Y') can be secured by changing the stable profile of the rectangular profile X by changing the spire profile of the bit line hard mask. The oxide spacer thickness Y is further increased by the thickness of the capping film 42.

) 프로파일이 발생하지 않는다. 이로 써, 후속 CMP 공정시 이웃한 스토리지노드콘택간 분리 CD가 크게 증가한다.In addition, the etch loss of the bit line hard mask is prevented by the passivation layer 42, and thus the unevenness (formation) generated after the first and second storage node contact etching is performed.

) Profile does not occur. This significantly increases the separation CD between neighboring storage node contacts during subsequent CMP processes.

As shown in FIG. 3F, polysilicon is deposited until the storage node contact hole including the primary opening 41 and the secondary opening 44 is filled, and then etched back to storage embedded in the storage node contact hole. The node contact 45 is formed. At this time, the hard mask pattern 39a is polished and removed.

In the case of applying the storage node contact forming method of the semiconductor device according to the exemplary embodiment described above, the bit line profiles are as shown in FIGS. 4A and 4B. Here, FIG. 4A is a view corresponding to FIG. 2A, which is a profile after forming the passivation layer 42, and FIG. 4B is a view corresponding to FIG. 2B, illustrating a profile after SNC spacer etching.

As shown in FIGS. 4A and 4B, not only the loss of the bit line is improved as compared with FIGS. 2A and 2B, but the sidewall spacers are secured to a sufficient thickness on both sidewalls of the bit line.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, in the present invention, a hard mask etching process and an SNC etching process can be performed in-situ in an insulating film etching chamber by applying a nitride film-based hard mask instead of a polysilicon film, and a key open mask ) Forming process and etching process can be omitted.

Second, in the present invention, an oxide film spacer is stably implemented by forming a rectangular profile on an upper portion of the bit line pattern by applying a protective film having a poor coating on the upper portion of the bit line pattern.

In addition, due to the effect of the protective film, the loss of the bit line hard mask during the subsequent nitride spacer and the second storage node contact etching process is greatly reduced.

In addition, the uneven profile generated in the upper part of the bit line after the etching process for forming the storage node contact hole is greatly improved, and the process margin is greatly increased during the subsequent CMP process.

In addition, the left and right asymmetric spacers have improved the spacer disappearance phenomenon found in some bit line patterns, and it is possible to increase the residual thickness of the bit line hard mask of the bit line pattern to secure the storage node contact separation margin. .

In addition, by securing the profile of the upper part of the bit line pattern in a stable rectangular profile, it is possible to secure a sufficient separation CD during the CMP process of the storage node contact.

Claims (9)

Forming a first insulating layer on the structure of the landing plug contact; Forming a bit line pattern stacked in the order of the bit line conductive layer and the bit line hard mask on a predetermined surface of the first insulating layer; Forming a second insulating film over the entire surface until the bit line pattern is filled; Planarizing the second insulating layer until an upper portion of the bit line pattern is exposed; Depositing a hard mask on the second insulating layer by using a nitride film-based material; Etching the hard mask to form a hard mask pattern; Forming a first opening by first etching the second insulating layer in the same chamber in-situ with the hard mask pattern forming process using the hard mask pattern as an etch barrier layer; Expanding the width of the primary opening in the chamber; Forming a protective film for converting the upper profile of the bit line pattern exposed by the primary opening into a rectangular profile; Forming a spacer on the passivation layer; Forming a secondary opening by performing spacer etching on the spacer until the surface of the landing plug contact is exposed; And Forming a storage node contact embedded in the storage node contact hole formed by the first and second openings; Storage node contact forming method of a semiconductor device comprising a. The method of claim 1, The hard mask is a storage node contact forming method of a semiconductor device, characterized in that formed by SRON film, Si ₃ N ₄ or SiON film. The method of claim 2, The forming of the hard mask pattern may include using a fluorine-based source gas such as CxFy or CxHyFz, and an O ₂ , N ₂ or Ar reaction gas. Here, x, y, z are natural or rational numbers. The method of claim 3, The amount of inflow of CxFy, CxHyFz is 1 ~ 100sccm, the inflow of O ₂ , N ₂ is 1 ~ 100sccm, the inflow of Ar is 1 ~ 1000sccm characterized in that the storage node contact forming method of the semiconductor device. The method of claim 4, wherein Forming the hard mask is a method of forming a storage node contact of a semiconductor device, characterized in that the pressure of 10 ~ 100mTorr, 100 ~ 2000W power. The method according to any one of claims 1 to 5, Forming the protective film, And forming an oxide film or nitride film-based material having a poor coating property such that a rectangular profile appears on the bit line pattern. The method of claim 6, The protective film is a storage node contact forming method of a semiconductor device, characterized in that formed by the USG film. The method of claim 7, wherein The protective film is a storage node contact forming method of a semiconductor device, characterized in that formed in the thickness of 500 ~ 900Å. The method of claim 8, The hard mask is formed by SRON.

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