KR100799113B1 - Method for manufacturing of non volatile memory cell - Google Patents

Abstract

A method for manufacturing a nonvolatile memory call is provided to form electrically separated floating gates by using a first dielectric gap-filled in a step and a second dielectric formed on both sidewalls of the first dielectric. A gate dielectric(105) is formed on a substrate exposed to both sides of an isolation layer(104). A conductive layer for a floating gate is formed along a step of an upper surface of the isolation layer including the gate dielectric. A first dielectric(170A) is formed. The first dielectric is gap-filled in a step of the conductive layer. The conductive layer exposed between the first dielectric is etched with a certain thickness. A second dielectric(109A) is formed on both sidewalls of the first dielectric so that the both sidewalls of the first dielectric have a vertical profile. The conductive layer is etched through an etching process using the first and second dielectrics as hard masks to expose the isolation layer.

Description

Non-volatile memory cell manufacturing method {METHOD FOR MANUFACTURING OF NON VOLATILE MEMORY CELL}

1A to 1E are cross-sectional views illustrating a method of manufacturing a flash memory cell applying a known ASA-STI process.

2A through 2J are cross-sectional views illustrating a method of manufacturing a flash memory cell according to an exemplary embodiment of the present invention.

   <Explanation of symbols for the main parts of the drawings>

100 substrate 101 pad oxide film

102: pad nitride film 103: trench

104: device isolation film 105: gate insulating film

106: conductive films 107, 107A: first insulating film

108, 110, 112: etching process 109, 109A: second insulating film

111: hard mask 106A: floating gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory device manufacturing technology, and more particularly to a nonvolatile memory device, and more particularly to a flash memory cell manufacturing method.

Semiconductor memories are classified into volatile memory, in which stored information is lost when electricity supply is interrupted, and non-volatile memory, which can maintain information even when electricity supply is interrupted. Nonvolatile memories include erasable programmable read only memory (EPROM), electrically EPROM (EEPROM), and flash memory.

Recently, the demand for flash memory devices that can be electrically programmed and erased, and that does not require a refresh function that rewrites data at regular intervals is increasing. .

On the other hand, in order to realize miniaturization of semiconductor memory devices and large capacity of flash memory devices, the cell formation technology of flash memory devices has undergone various changes.

For example, in an 80 nm class flash memory device, a flash memory cell is formed in a general stack structure, for example, a structure in which a floating gate, a dielectric layer, and a control gate are sequentially stacked on a substrate. There is a limit to high integration. Accordingly, recently, a method of forming a flash memory cell by applying an advanced self aligned-shallow trench isolation (ASA-STI) process has been proposed to implement a flash memory device having a higher density than 70 nm.

1A to 1E are cross-sectional views illustrating a method of manufacturing a flash memory cell applying a known ASA-STI process.

First, as shown in FIG. 1A, after the pad oxide film 11 and the pad nitride film 12 are sequentially deposited on the substrate 10, the pad nitride film 12, the pad oxide film 11, and the substrate 10 may be deposited. A portion is etched to form a trench 13.

Subsequently, as shown in FIG. 1B, the device isolation layer 14 embedded in the trench 13 (see FIG. 1A) is formed.

Subsequently, as shown in FIG. 1C, the pad is etched using a phosphoric acid (H ₃ PO ₄ ) solution to remove the pad nitride layer 12 (see FIG. 1B), followed by a wet etch process using an oxide film etching solution. The oxide film 11 (see FIG. 1B) is removed.

Subsequently, a gate oxide film 15 is formed on the exposed substrate 10.

Subsequently, as shown in FIG. 1D, a floating silicon polysilicon film 16 is deposited on the device isolation film 14 including the gate oxide film 15.

Subsequently, as shown in FIG. 1E, a predetermined photoresist pattern 17 is formed on the polysilicon film 16 (see FIG. 1D), and then an etching process 18 using the same as an etching mask is performed. The polysilicon film 16 is etched. This forms a plurality of floating gates 16A in which neighboring ones are separated from each other.

However, when manufacturing a flash memory cell by applying the known ASA-STI process, the following problems may occur.

For example, due to the lack of an alignment margin in the mask process for forming the photoresist pattern 17, adjacent floating gates 16A mis-align (M ') regions with respect to the device isolation layer 14. Are formed). As a result, the distance between the substrate 10 in the active region is different from the edges of the neighboring floating gates 16A (D ₁ ? D ₂ ), thereby degrading device characteristics. In extreme cases, short circuits between neighboring flash memory cells are caused.

Accordingly, an object of the present invention is to provide a method of manufacturing a nonvolatile memory cell that can prevent a neighboring floating gate from being misaligned with a device isolation layer.

According to an aspect of the present invention, a gate insulating film is formed on a substrate exposed to both sides of a device isolation layer, and a floating gate conductive layer is formed along a top surface of the device isolation layer including the gate insulating layer. Forming a film, forming a first insulating film embedded in the stepped portion of the conductive film generated during formation of the conductive film, etching the conductive film exposed between the first insulating film to a predetermined thickness, and Forming a second insulating film on both sidewalls of the first insulating film so that both sidewalls of the insulating film have a vertical profile, and etching the conductive film using an etching process using the first and second insulating films as a hard mask to expose the device isolation layer. It provides a method of manufacturing a nonvolatile memory cell comprising etching the film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same components.

Example

2A through 2J are cross-sectional views illustrating a method of manufacturing a flash memory cell according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, the substrate 100 cleaned by pretreatment cleaning is prepared. Here, the pretreatment washing process is performed with DHF (Diluted HF) and then SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O), or BOE (Buffer Oxide Etchant) and then SC-1. It may be performed sequentially.

Subsequently, an ion implantation process for forming a well and an ion implantation process for adjusting a threshold voltage may be performed.

Subsequently, the pad oxide film 101 and the pad nitride film 102 are sequentially formed on the substrate 100.

Subsequently, a mask process and a known shallow trench isolation (STI) etching process are performed to form a trench 103 having a predetermined depth by etching the pad nitride layer 102, the pad oxide layer 101, and a portion of the substrate 100.

Subsequently, as shown in FIG. 2B, the device isolation film 104 is deposited on the pad nitride film 102 to fill the trench 103 (see FIG. 2A). Here, the device isolation film 104 uses an oxide film material that has been proven to have excellent buried characteristics. Typically, an HDP oxide film deposited by a high density plasma (HDP) chemical vapor deposition (CVD) method is used.

Subsequently, a chemical mechanical polishing (hereinafter referred to as CMP) process is performed to remove the oxide material on the pad nitride film 102. In other words, the CMP process is performed using the pad nitride film 102 as a polishing stop film to remove the device isolation film 104 on the pad nitride film 102.

Subsequently, as shown in FIG. 2C, a wet etching process is performed to remove the pad nitride film 102 (see FIG. 2B) and the pad oxide film 101 (see FIG. 2B). For example, the pad nitride layer 102 is first removed using a phosphoric acid solution (H ₃ PO ₄ ), and the pad oxide layer 101 is removed using a buffered oxide etchant (HF) solution.

The reason why the pad oxide film 101 is removed is that the pad oxide film 101 is partially damaged when the pad nitride film 102 is removed. Thus, when the pad oxide film 101 is used as a gate insulating film, the pad oxide film 101 is deteriorated.

Subsequently, the gate insulating layer 105 is formed on the substrate 100 exposed to both sides of the device isolation layer 104. For example, an oxidation process is performed to form a gate insulating film 105 of an oxide film material. In this oxidation process, a part of the device isolation layer 104 may be oxidized by O ₂ gas injected during the oxidation process.

Subsequently, as shown in FIG. 2D, a floating gate conductive film 106 is deposited on the device isolation film 104 including the gate insulating film 105. For example, the conductive film 106 preferably uses a doped or undoped polysilicon film.

Next, the first insulating film 107 for hard mask is deposited on the conductive film 106. For example, an oxide film-based material is deposited on the first insulating film 107.

Next, as shown in FIG. 2E, a CMP process is performed to remove the first insulating film 107A on the conductive film 106. That is, the CMP process using the conductive film 106 as the polishing stop film is performed to remove all of the oxide film-based material on the conductive film 106. As a result, the first insulating film 107A having the form embedded in the stepped portion of the conductive film 106 generated during the deposition of the conductive film 106 is formed.

In particular, in the CMP process, the difference in polishing selectivity between the polysilicon film constituting the conductive film 106 and the oxide film constituting the first insulating film 107A is used. To this end, the CMP process uses a slurry having a property that the polishing rate for the oxide film is significantly faster than the polishing rate for polysilicon. For example, the slurry used at this time should use ceria as an abrasive and have a pH of about 6-8.

Subsequently, as illustrated in FIG. 2F, an etching process 108 using the first insulating film 107A as an etching mask is performed to etch a conductive thickness 106 exposed between the first insulating films 107A. For example, the conductive film 106 is etched at about 100 to 500 mW. That is, the etching process 108 is performed by using an etching selectivity between the oxide film material constituting the first insulating film 107A and the polysilicon material constituting the conductive film 106.

Next, as shown in FIG. 2G, a second insulating film 109 for spacers is deposited on the conductive film 106 including the first insulating film 107A. For example, an oxide film-based material is deposited on the second insulating film 109.

Subsequently, as illustrated in FIG. 2H, an etch back process 110 is performed to etch the second insulating layer 109 (see FIG. 2G). As a result, the second insulating layer 109A in the form of a spacer remains on both sidewalls of the first insulating layer 107A, and thus both sidewalls of the first insulating layer 107A have a vertical profile. The first insulating layer 107A and the second insulating layer 109A formed as described above function as one hard mask 111, thereby adjusting the line width of the floating gate 106A (see FIG. 2I) to be formed subsequently. .

Subsequently, as illustrated in FIG. 2I, an etching process 112 using the hard mask 111 as an etch mask is performed to etch the conductive film 106 (see FIG. 2H) exposed between the hard masks 111. As a result, a plurality of floating gates 106A are automatically formed and separated from each other based on the device isolation film 104. In this case, the neighboring floating gates 106A are formed to be spaced apart from each other by the same width D as the substrate 100 in the active region. That is, the floating gate 106A is formed to be automatically aligned.

Subsequently, as shown in FIG. 2J, a wet etching process using an oxide film etching solution is performed to remove the hard mask 111 (see FIG. 2I).

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the first insulating film and the first insulating film embedded in the step portion generated during the deposition of the conductive film for the floating gate without using the photoresist pattern as an etching mask in the etching process for forming the floating gate. By using the second insulating film formed on both side walls of the insulating film as a hard mask, a floating gate can be formed which is automatically aligned with the device isolation film as a starting point and electrically separated from each other.

Therefore, the floating gates adjacent to each other based on the device isolation film are spaced apart from each other by the same width and have the same width from the substrate in the active region, thereby improving device characteristics.

As a result, the occurrence of a short circuit between neighboring floating gates can be prevented.

Claims (10)

Forming a gate insulating film on the substrate exposed to both sides of the device isolation film; Forming a conductive film for a floating gate along a step of an upper surface of the device isolation film including the gate insulating film; Forming a first insulating film embedded in a stepped portion of the conductive film generated when the conductive film is formed; Etching a thickness of the conductive film exposed between the first insulating films; Forming a second insulating film on both side walls of the first insulating film such that both side walls of the first insulating film have a vertical profile; And Etching the conductive layer through an etching process using the first and second insulating layers as hard masks to expose the device isolation layer. Nonvolatile memory cell manufacturing method comprising a. The method of claim 1, After etching the conductive film, And removing the first and second insulating layers. The method of claim 1, Before forming the gate insulating film, Forming a pad nitride film on the substrate; Etching a portion of the pad nitride layer and the substrate to form a trench; Forming the device isolation layer embedded in the trench; And Removing the pad nitride film Nonvolatile memory cell manufacturing method further comprising. The method according to any one of claims 1 to 3, Forming the first insulating film, Depositing the first insulating film on the conductive film; And Performing a chemical mechanical polishing process to remove the first insulating film on the conductive film Nonvolatile memory cell manufacturing method comprising a. The method of claim 4, wherein The chemical mechanical polishing process uses a slurry having a faster polishing rate of the first insulating film than the conductive film. The method of claim 5, wherein The slurry is a non-volatile memory cell manufacturing method characterized in that the ceria is used as an abrasive and the pH is 6 ~ 8. The method according to any one of claims 1 to 3, Forming the second insulating film, Depositing the second insulating film on the conductive film including the first insulating film; And Performing an etch back process so that the second insulating film remains on both sidewalls of the first insulating film Nonvolatile memory cell manufacturing method comprising a. The method according to any one of claims 1 to 3, And the first and second insulating layers are formed of an oxide-based material. The method according to any one of claims 1 to 3, And the conductive film is formed of a doped or undoped polysilicon film. The method according to any one of claims 1 to 3, Etching the conductive film exposed between the first insulating film, A method of manufacturing a nonvolatile memory cell in which the loss thickness of the conductive film is set to 100 to 500 GPa.

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