KR20040042058A - Method for manufacturing of flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a non-volatile memory device is provided to prevent the characteristic deterioration of a lower interlayer dielectric and restrain the gate junction short due to over-bridge phenomena by forming a control gate using an etch-back process after a gate poly depositing process instead of a photolithography. CONSTITUTION: A floating gate(203) is formed above a cell region(A) of a semiconductor substrate. An oxide layer is non-uniformly formed on the resultant structure. A polysilicon layer is deposited on the predetermined portion of the resultant structure. An implanting process is carried out on the resultant structure. A control gate(205) is formed above the cell region by carrying out an etch back process on the resultant structure. Then, a transistor gate is formed. An LDD(Light Doped Drain), a spacer, and an N+/P+ junction are formed in sequence. A self-aligned silicide layer is selectively formed on the resultant structure.

Description

Method of manufacturing nonvolatile memory device {METHOD FOR MANUFACTURING OF FLASH MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and to a method of manufacturing a nonvolatile memory device for preventing short circuit of the gate junction due to IPD degradation characteristics generated during the manufacture of a self-aligned select transistor and an over bridge occurring when a silicide process is applied. will be.

Nonvolatile memory devices are classified into two cell types, which are divided into ETOX (Electrically Erasible & Programmable Read Only Memory) types and Split gate types.

Since the ETOX type uses Hot Carrier Injection during programming, the program current is very large, and the program and readout disturbs are worse than the Split gate type. In addition, although it has the Over-Erase problem which is the biggest problem in reliability, the cell size is very small compared to the split gate type.

The split gate type cell flash memory device has a large cell size, but almost no over-erasure problem, and thus there is a select transistor in a single cell to maintain a constant threshold voltage. Therefore, even if there is a decrease in the cell transistor, the select transistor can be recognized externally. There is an advantage to that.

1A to 1L illustrate a manufacturing process of a nonvolatile memory device according to the prior art.

Referring to FIG. 1A, first, a cell isolation layer A and a ferry or logic region B are formed, and a device isolation layer 101 is formed by a device isolation process using a conventional LOCOS process to separate the two regions.

Referring to FIG. 1B, a tunnel oxide layer 102 is formed on a resultant device on which the device isolation layer 101 is formed, and then an IPD (Inter-Poly Dielectric) layer is deposited on the floating gate poly 103 and the dielectric layer 104. A mask insulating film 105 is deposited.

In this case, the tunnel oxide film 102 is formed to a thickness of 60 ~ 150Å by the thermal oxidation process, the floating gate poly 103 is deposited to a thickness of 1500 ~ 5000Å by the doped poly or implant doping.

In addition, the dielectric film 104 is formed of Oxide-Nitride-Oxide (hereinafter referred to as ONO), and the insulating film for hard mask 105 uses Oxide / Nitride or Oxynitride to facilitate patterning of the floating gate.

Referring to FIG. 1C, the floating gate FG is formed through a photolithography process using a photoresist (not shown). In this case, the photoresist may be used as an etch stop film of the gate poly 103, and all the films of the ferry or logic region B may be etched.

Referring to FIG. 1D, the sidewall 106 is formed of an inter-poly dielectric (IPD) in the floating gate FG. At this time, the sidewall 106 is also formed in ONO.

Referring to FIG. 1E, an oxide film 107 to be used as a gate oxide film in the high voltage region and the cell select transistor region is formed thick by a thermal oxidation process or a CVD method.

Referring to FIG. 1F, after the photoresist pattern 108 is formed only in the cell region A, an etching process is performed on the oxide layer 107 of the ferry and logic regions B to form a thin oxide layer 107 having a thickness of 20 to 90 kPa. Form ').

Referring to Fig. 1G, a polysilicon film 109 is deposited to a thickness of 1500 to 4000 GPa.

The polysilicon 109 uses undoped polysilicon in sub-micron technology to make the logic and peripheral circuit PMOS gates P +.

Referring to FIG. 1H, a cell gate doping process is performed after forming the photoresist pattern 110 for the cell control gate pattern. At this time, when using an NMOS cell, a boron is injected into the PMOS cell with phosphorus or arsenic.

Referring to FIG. 1I, the control gate CG of the cell region A is patterned using the photoresist pattern 110 for cell control gate pattern as an etch stop layer. In this case, the polysilicon spacer serves as a gate of the selection transistor.

Referring to FIG. 1J, a photolithography and an etching process for forming the transistor gate TG are performed in the ferry and logic regions B. In this case, the cell region is protected by the photoresist 111 during the etching process.

Referring to FIG. 1K, after forming the transistor gate TG and forming the LDD 112 or the LDD junction 113, sidewall spacers 114 are formed in each gate. Subsequently, N + / P + junction 115 is formed.

Referring to FIG. 1L, a self-aligned silicide layer 116 is formed in the logic region B through a silicide process.

2 is a diagram illustrating a problem in manufacturing a nonvolatile memory device according to the prior art.

As shown here, since the photoresist pattern 110 is used to form the control gate CG, peak points and slopes are generated in the poly spacer, which causes active and gate shorts. Due to this, there is a problem in that the word line and active and word line contacts of the cell increase rapidly.

In addition, the manufacturing method of the nonvolatile memory device according to the prior art causes the following problems.

First, when IPD (inter-poly dielectric) deposition of flash memory device is degraded by photo and etching process and used as capping film, it becomes difficult to control the thickness of IPD, which reduces the coupling ratio of cells in chip. There was.

Second, an unwanted etch stop layer is formed by the residues generated in the photoresist and the etching layer during the control gate etching, making it difficult to form a normal patch. Foreign matter is generated by such an abnormal pattern, thereby lowering the yield of the chip.

Third, the implant shadow effect is generated by the photoresist during the control gate doping, which causes gate doping of the select transistor to be difficult.

In order to solve the above problems, the present invention forms the control gate and the spacer through the etchback process after the gate poly deposition, instead of the method of forming the cell control gate through the photo / etch process. An object of the present invention is to provide a method of manufacturing a nonvolatile memory device for preventing a short circuit of a gate junction caused by an over bridge occurring during a silicide process.

1A to 1L illustrate a manufacturing process of a nonvolatile memory device according to the prior art.

2 is a diagram illustrating a problem in manufacturing a nonvolatile memory device according to the prior art.

3A to 3 are process diagrams illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

-Explanation of symbols for the main parts of the drawings-

201: device isolation layer 202: tunnel oxide film

203: Poly 204 for floating gate: IPD dielectric film

205: poly for control gate 206: insulating film for hard mask

207: IPD sidewall spacer 208: oxide film

210: polysilicon 209: silicide film

According to the present invention, a floating gate is formed in a cell region of a semiconductor substrate in which a cell and a logic region are separated and a predetermined lower layer structure is formed, and a logic and a cell region in which a phase floating gate is formed are thick. Forming an oxide layer and etching the thick oxide layer in the logic region to make the oxide layer in the logic region thin, depositing polysilicon on the resultant product on which the thin oxide layer is formed, and then performing an implant process, and performing the implant process. Forming a control gate in the cell through an etchback process and then forming a transistor gate, and forming N ⁺ / P ⁺ junction with LDD and spacer on the resultant transistor gate Non-volatile memory comprising forming a silicide film Party to the preparation method.

At this time, the thickness of the thin oxide film formed in the logic region is preferably such that the thickness of 20 ~ 90Å.

In addition, in the implant process, it is preferable to inject P or As into the PMOS cell when the NMOS cell is used.

As described above, the present invention forms the control gate and the spacer through the etch back process rather than the photo / etch process when forming the control gate pattern, so that the shape of the gate has a normal pattern and can prevent deterioration of characteristics of the underlying interlayer dielectric film. .

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

3A to 3 are process diagrams illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

Referring to FIG. 3A, after forming the cell region A and the ferry or logic region B on the semiconductor substrate, the device isolation layer 201 is formed through a conventional LOCOS process for separating the two regions.

Referring to FIG. 3B, the tunnel oxide film 202, the floating gate poly 203, and the dielectric film 204 may be formed of an inter-poly dielectric (IPD) and a control gate poly 205 and a hard mask insulating film 206. Deposition in turn.

At this time, the tunnel oxide film 202 is formed to a thickness of 60 ~ 150Å by the thermal oxidation process, the floating gate poly 203 is formed by doping with a doped poly or implant to a thickness of 1500 ~ 5000Å.

In addition, the IPD dielectric film 204 is formed of a general ONO, the control gate poly 205 uses doped poly or undoped polysilicon, and the hard mask insulating film 206 facilitates the patterning of the floating gate. Oxide / Nitride and Oxynitride are used for this purpose.

Referring to FIG. 3C, the floating gate FG is formed in the cell region A through a photolithography and an etching process.

Referring to FIG. 3D, an IPD film to be used as a sidewall of the floating gate FG is deposited and an IPD sidewall spacer 207 is formed through an etching process. At this time, the IPD sidewall spacer is also formed of a general ONO.

Referring to FIG. 3E, an oxide film 208 to be used as a gate oxide film of a high voltage region and a cell select transistor is deposited thickly using a thermal oxidation process or a CVD method.

Referring to FIG. 3F, the oxide film deposited in the logic region of the thickly deposited oxide film 208 is subjected to the photolithography and etching process using the photoresist pattern 209 to form a thin oxide film 208 ′ having a thickness of 20 to 90 μm. do.

Referring to FIG. 3G, polysilicon 210 is deposited to a thickness of 1500 to 4000 microseconds. Submicron technology uses undoped polysilicon to make P ⁺ gates of logic and peripheral circuits P ⁺ .

Referring to FIG. 3H, an implant process is performed to dope the gate of the selection transistor using the photoresist pattern 211. At this time, when using an NMOS cell, a boron is injected into the PMOS cell with phosphorus or arsenic.

Referring to FIG. 3I, the spacer 210 ′ is formed through an etch back process to form the control gate CG in the cell.

Referring to FIG. 3J, a photolithography and an etching process for forming the transistor gate TG are performed.

Referring to FIG. 3K, after the transistor gate TG is formed, an LDD 213 and an LDD junction 214 are formed, and sidewall spacers 215 are formed in each gate, and then an N + / P + junction is formed. .

Referring to FIG. 3L, a self-aligned silicide layer 211 is formed in the cell region A and the logic region B by performing a silicide process. In this case, in the silicide process, the residual insulating film 206 between the poly film 206 of the control gate CG and the selection gate SG poly 210 is generally etched through a wet etching process, and thus, the silicide film 211 is etched. The control gate CG and the selection gate SG are connected to each other.

As described above, the present invention forms a self-aligned silicide layer through a general subsequent process and silicide process after forming the control gate in the cell through the etch back process rather than the general photo / etch process, thereby preventing the degradation of IPD characteristics. There is an advantage.

In addition, since the cell control gate pattern is formed through an etchback process, peak points and slopes are formed in the control gate poly spacer without forming a peak point and slope, thereby preventing the gate junction short caused by the silicide over bridge. Since silicides can be applied, this has the advantage of reducing the word line resistance, reducing the contact resistance and reducing the chip area to improve the yield.

Claims (4)

Forming a floating gate in a cell region of the semiconductor substrate in which the cell and logic regions are separated and a predetermined lower deposition structure is formed; Forming a thick oxide layer in the logic and cell region in which the phase floating gate is formed, and etching the thick oxide layer in the logic region to make the oxide layer in the logic region thin; Depositing polysilicon on the resultant thin oxide film and then performing an implant process; Forming a control gate in a cell through an etch back process on the resultant of the implant process, and forming a transistor gate; Forming an N ⁺ / P ⁺ junction with the LDD and the spacer on the resultant product on which the transistor gate is formed, and then forming a self-aligned silicide layer Method of manufacturing a nonvolatile memory device comprising a. The method of claim 1, wherein a thickness of the thin oxide film formed in the logic region is about 20 μs to about 90 μs. The method of claim 1, wherein the thick oxide film is formed by a thermal oxidation process or a CVD method. The method of claim 1, wherein the implant process implants P or As and B ions into the PMOS cell when using an NMOS cell.