KR100723764B1 - Method of manufacturing a flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, wherein a gap between cells is formed while forming a floating gate using one conductive layer without using a SA-STI process, which is not applicable to a highly integrated semiconductor device manufacturing process. It is possible to secure enough to minimize the cell-to-cell interference, and by adjusting the EFH by etching the device isolation film in the cell region by a predetermined thickness, the coupling area can be improved by increasing the contact area between the dielectric film and the floating gate. In addition, in the process of controlling the EFH by etching the device isolation layer to a predetermined depth, the conductive layer spacers are formed on the sidewalls of the floating gate to damage the tunnel oxide film, the semiconductor substrate, or the floating gate. This can be prevented.

NAND Flash, EFH, Device Isolation, Conductive Layer spacer

Description

Method of manufacturing a flash memory device

1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to an embodiment of the present invention.

2 (a) to 2 (e) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11 and 21: semiconductor substrate 12 and 22: tunnel oxide film

13 and 23: first conductive layers 14 and 24: hard mask films

15 and 25 trench 16 and 26 insulating film

16A and 26A: device isolation film 17 and 28: dielectric film

18 and 29: second conductive layer 28: conductive layer spacer

The present invention relates to a method of manufacturing a flash memory device, in particular, to minimize the interference effect between adjacent cells, especially in a highly integrated semiconductor device, and to improve the coupling ratio by adjusting the EFH by etching the device isolation film a predetermined thickness. A method of manufacturing a memory device.

 NAND-type flash memory devices perform data programs by injecting electrons into floating gates using a Fowler-Nordheim (FN) tunneling phenomenon to provide a large capacity and high integration.

A NAND type flash memory device is composed of a plurality of cell blocks, and a cell block includes a plurality of cell strings, cell strings, drains, and cell strings that form a string by connecting a plurality of cells for storing data in series. And a drain select transistor and a source select transistor respectively formed between the sources. Here, the cell of the NAND type flash memory device forms a device isolation film in a predetermined region on the semiconductor substrate, and then forms a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on the semiconductor substrate, and on both sides of the gate. It is comprised by forming a junction part in. Here, the device isolation layer and the floating gate are formed by a shallow trench isolation (STI) process, a self aligned shallow trench isolation (SA-STI) process, or a self aligned floating gate (SAFG) process.

However, as the size of the NAND-type flash memory device is reduced, the distance between cells decreases, and accordingly, the interference effect between adjacent cells in which the state of the cell changes due to the operation of the adjacent cells is the biggest problem. For example, during programming, the threshold voltage of the program cell is increased by being affected by the threshold voltage of the neighboring cell by the floating gate interference effect. Therefore, the threshold voltage distribution of the program cell is widely varied, which causes the chip to fail. This inter-cell interference effect problem is more important in a multilevel cell. In order to minimize the effect of interference between adjacent cells, sufficient spacing between cells should be ensured. However, there is a limit in ensuring sufficient spacing between cells due to the high integration of the device.

Meanwhile, in the SA-STI process, which is used most recently, a floating gate is formed of the first and second polysilicon layers, and the second polysilicon layer is patterned using a floating gate mask. However, due to high integration of semiconductor devices, alignment margins are reduced as the cell size is reduced, so that the process using the floating gate mask can no longer be used.

An object of the present invention is to form a floating gate with one conductive layer without using the SA-STI process, which is limited in use due to the high integration of semiconductor devices, and to minimize the interference effect between adjacent cells by ensuring sufficient spacing between cells. The present invention provides a method of manufacturing a flash memory device.

Another object of the present invention is to form a floating gate without using the SA-STI process, and to sufficiently increase the inter-cell spacing to increase the contact area with the dielectric film while minimizing the interference effect between adjacent cells, thereby improving the coupling ratio. The present invention provides a method of manufacturing a flash memory device.

Another object of the present invention is to provide a method of manufacturing a flash memory device capable of preventing damage to a tunnel oxide film, a semiconductor substrate, or a floating gate in the process of improving the coupling ratio by etching to a predetermined thickness of the device isolation film.

According to an embodiment of the present disclosure, a method of manufacturing a flash memory device may include (a) forming a floating gate pattern by stacking a tunnel oxide layer and a first conductive layer on a first region of a semiconductor substrate, and forming a floating gate pattern on the second region of the semiconductor substrate. Forming a trench type isolation layer; (b) etching the device isolation layer to a predetermined thickness; And (c) forming a dielectric film and a second conductive layer over the entire structure and then patterning to form a floating gate and a control gate.

Step (a) may include sequentially forming the tunnel oxide film, the first conductive layer, and the hard mask film on the semiconductor substrate; Forming a floating gate pattern by etching a predetermined region of the hard mask layer, the first conductive layer, and the tunnel oxide layer by a photolithography and an etching process using an isolation mask, and then etching the semiconductor substrate to a predetermined depth to form a trench ; Forming an insulating film on an entire structure to fill the trench; And polishing the insulating layer to expose the hard mask layer, and then removing the hard mask layer to form the device isolation layer.

The first conductive layer is formed by stacking an undoped polysilicon film and a dope polysilicon film to a thickness of 700 to 1500 kPa, and the undoped polysilicon film is formed to a thickness of 1/2 of the first conductive layer.

The step (b) is performed by a wet etching process using BOE.

In addition, according to another embodiment of the present disclosure, a method of manufacturing a flash memory device may include (a) forming a floating gate pattern by stacking a tunnel oxide layer and a first conductive layer on a first region of a semiconductor substrate, and forming a floating gate pattern on the second region of the semiconductor substrate. Forming a trench type isolation layer in the region; (b) first etching a thickness of the device isolation layer; (c) forming a conductive layer spacer on sidewalls of the first conductive layer; (d) etching the device isolation layer by a predetermined thickness; And (c) forming a dielectric film and a second conductive layer over the entire structure and then patterning to form a floating gate and a control gate.

Step (a) may include sequentially forming the tunnel oxide film, the first conductive layer, and the hard mask film on the semiconductor substrate; Forming a floating gate pattern by etching a predetermined region of the hard mask layer, the first conductive layer, and the tunnel oxide layer by a photolithography and an etching process using an isolation mask, and then etching the semiconductor substrate to a predetermined depth to form a trench ; Forming an insulating film on the entire structure to fill the trench; And polishing the insulating layer to expose the hard mask layer, and then removing the hard mask layer to form the device isolation layer.

The first conductive layer is formed to a thickness of 700 to 1500 kPa using an undoped polysilicon film.

The conductive layer spacers are formed using a doped polysilicon film with a minimum thickness that does not affect the interference effect between adjacent cells, and preferably, a thickness of 1/2 or less of a gap between cells.

The doped polysilicon layer for forming the conductive layer spacer has a doping concentration of 1E15 to 2E15ions / cm 2 or more.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1A, the tunnel oxide film 12, the first conductive layer 13, and the hard mask film 14 are sequentially formed on the semiconductor substrate 11. The first conductive layer 13 is formed by stacking an undoped polysilicon film and a dope polysilicon film to a thickness of 700 to 1500 Å to prevent the smiling of the tunnel oxide film 12. The undoped polysilicon film is formed of a first conductive layer. It is formed to a thickness of 1/2 of the layer (13). On the other hand, when applied to a single level cell, the first conductive layer 13 is formed to a thickness of 1000 to 1500 mW, and to be applied to a multi-level cell is formed to a thickness of 700 to 1000 mW. In addition, the hard mask film 14 is preferably formed using a nitride film. Then, the hard mask film 14 is patterned by a lithography process and an etching process using an element isolation mask to determine the active region and the field region. The trench 15 is formed by etching the first conductive layer 13, the tunnel oxide layer 12, and the semiconductor substrate 11 to a predetermined depth using the patterned hard mask layer 14 as an etching mask. As the trench 15 is formed, the first conductive layer 13 is patterned to determine the floating gate pattern. That is, the trenches for forming the device isolation film and the floating gate pattern are determined in parallel directions. After that, the insulating film 16 is formed on the entire structure to fill the trench 15.

Referring to FIG. 1B, after the insulating film 16 is polished to expose the hard mask film 14, the hard mask film 14 is removed using phosphoric acid or the like. As a result, the isolation layer 16A having the insulating layer 16 embedded therein is formed in the trench 15.

Referring to FIG. 1C, an effective field oxide height (EFH) is controlled by etching the device isolation layer 16A to a predetermined depth by a wet etching process using a BOE or the like. In this case, the coupling ratio can be increased by increasing the contact area between the dielectric film to be formed later and the first conductive layer 13.

Referring to FIG. 1D, after forming the dielectric film 17 over the entire structure, the second conductive layer 18 is formed. A predetermined region from the second conductive layer 18 to the tunnel oxide film 12 is etched by a lithography process and an etching process using a control gate mask to form a gate in which the floating gate and the control gate are stacked. Here, the first conductive layer 13 serves as a floating gate, and the second conductive layer 18 serves as a control gate.

In the above embodiment, since the first conductive layer 13, the tunnel oxide film 12, and the semiconductor substrate 11 are aligned, the tunnel oxide film 12 and the tunnel oxide film 12A are etched in the process of etching the device isolation layer 16A to control the EFH. The semiconductor substrate 11 may be exposed and damaged. In addition, since the device isolation layer 16A is etched while the side surface of the first conductive layer 13 is exposed, the first conductive layer 13 may also be damaged. Therefore, if the device isolation layer is further etched after the conductive layer spacer is formed on the sidewalls of the first conductive layer 13, the above problem may be prevented. This will be described with reference to FIGS. 2 (a) to 2 (e) as follows.

2 (a) to 2 (e) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to another embodiment of the present invention.

Referring to FIG. 2A, the tunnel oxide film 22, the first conductive layer 23, and the hard mask film 24 are sequentially formed on the semiconductor substrate 21. The first conductive layer 23 is formed to a thickness of 700 to 1500 mW using an undoped polysilicon film, and is formed to a thickness of 1000 to 1500 mW when applied to a single level cell, and 700 to 1000 mW when applied to a multi-level cell. It is formed to the thickness of. In addition, the hard mask film 24 is preferably formed using a nitride film. Then, the hard mask layer 24 is patterned by a lithography process and an etching process using an element isolation mask to determine the active region and the field region. The trench 25 is formed by etching the first conductive layer 23, the tunnel oxide layer 22, and the semiconductor substrate 21 to a predetermined depth using the patterned hard mask layer 24 as an etching mask. As the trench 25 is formed, the first conductive layer 13 is patterned to determine the floating gate pattern. That is, the trenches for forming the device isolation film and the floating gate pattern are determined in parallel directions. After that, the insulating film 26 is formed on the entire structure so that the trench 25 is buried.

Referring to FIG. 2B, the insulating film 26 is polished to expose the hard mask film 24, and then the hard mask film 24 is removed using phosphoric acid or the like. As a result, the isolation layer 26A having the insulating layer 26 embedded therein is formed in the trench 25. In addition, the device isolation layer 26A is etched to a predetermined depth by a wet etching process using a BOE to adjust the effective field oxide height (EFH).

Referring to FIG. 2C, the conductive layer is formed over the entire structure and then etched to form a conductive layer spacer 27 on the sidewall of the first conductive layer 23. Here, the conductive layer spacers 27 are formed to a minimum thickness that does not affect the interference effect between adjacent cells, and is formed using a doped polysilicon film. Preferably, the conductive layer spacers 27 are formed to have a thickness of 1/2 of the cell-to-cell spacing, and have a doping concentration of 1E15 to 2E15ions / cm 2 or more.

Referring to FIG. 2 (d), the device isolation layer 26A is etched deeper by performing a cleaning process in a state where the conductive layer spacers 27 are formed on the sidewalls of the first conductive layer 23.

Referring to FIG. 2E, the second conductive layer 29 is formed after forming the dielectric film 28 over the entire structure. Then, a predetermined region from the second conductive layer 29 to the tunnel oxide layer 22 is etched by a lithography process and an etching process using a control gate mask to form a cell gate in which a floating gate and a control gate are stacked.

As described above, according to the present invention, a floating gate is formed by using one conductive layer without using the SA-STI process, which is not applicable to the manufacturing process of highly integrated semiconductor devices, and sufficient spacing between cells is ensured. The interference effect can be minimized, and the coupling ratio can be improved by increasing the contact area between the dielectric film and the floating gate by adjusting the EFH by etching the device isolation film in the cell region to a predetermined thickness.

In addition, in the process of controlling the EFH by etching the device isolation layer to a predetermined depth, the conductive layer spacers are formed on the sidewalls of the floating gate to damage the tunnel oxide film, the semiconductor substrate, or the floating gate. This can be prevented.

Claims (13)

delete delete delete delete delete Depositing a tunnel oxide film and a first conductive layer on the semiconductor substrate; Etching the first conductive layer, the tunnel oxide layer, and the semiconductor substrate to define an isolation region and an active region; Forming an isolation layer by filling an insulating material in the isolation region; First etching the device isolation layer to expose sidewalls of the first conductive layer; Forming a conductive layer spacer on sidewalls of the first conductive layer; Second etching the device isolation layer so that the height of the device isolation layer is lowered; And And forming a dielectric film and a second conductive layer on the device isolation layer, the conductive layer spacer, and the first conductive layer. The method of claim 6, wherein the forming of the device isolation layer, Sequentially forming the tunnel oxide film, the first conductive layer, and the hard mask film on the semiconductor substrate; Forming a trench by etching the hard mask layer, the first conductive layer, the tunnel oxide layer, and the semiconductor substrate on the device isolation region by a photolithography and an etching process using a device isolation mask; Filling the insulating material so that the trench is buried; And And removing the hard mask layer. The method of claim 6, wherein the first conductive layer is formed to a thickness of 700 to 1500 Å using an undoped polysilicon film. The method of claim 6, wherein the conductive layer spacer is formed using a doped polysilicon film. The method of claim 9, wherein the doped polysilicon film for forming the conductive layer spacer has a doping concentration of 1E15 to 2E15ions / cm 2. The method of claim 6, wherein the first conductive layer is formed by stacking an undoped polysilicon film and a dope polysilicon film to a thickness of 700 to 1500 Å. The method of claim 11, wherein the undoped polysilicon film is formed to a thickness of 1/2 or less of the first conductive layer. The method of claim 6, wherein the etching of the device isolation layer in the first and second portions comprises a wet etching process using a buffered oxide etchant (BOE).

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