KR100716668B1 - Method for forming gate electrode of semiconductor device - Google Patents

Abstract

The present invention provides a gate electrode of a semiconductor device and a method of forming the same, which can increase the surface area between dielectric films by increasing the surface area without increasing the height of the gate electrode, thereby increasing the coupling ratio and improving the characteristics of the device. To this end, the present invention provides a gate electrode of the semiconductor device formed with protrusions protruding in the direction adjacent to both side walls so that neighbors on the device isolation layer defining the active region and the field region are separated from each other. .

Semiconductor element, flash memory element, gate electrode, floating gate, stepped, protrusion, photoresist, flow

Description

TECHNICAL FOR FORMING GATE ELECTRODE OF SEMICONDUCTOR DEVICE

1A to 1E are cross-sectional views illustrating a method of forming a floating gate of a general NAND flash memory device.

2 is a cross-sectional view illustrating a gate electrode of a semiconductor memory device according to an embodiment of the present invention.

3A to 3G are cross-sectional views illustrating a method of forming the gate electrode illustrated in FIG. 2.

   <Explanation of symbols for the main parts of the drawings>

10, 110: substrate

11, 111: gate insulating film

12, 112: first polysilicon film

14: trench

15, 113: device isolation film

16, 114: second polysilicon film

17: floating gate

115,116: Photosensitive film

115a, 116a: photosensitive film pattern

118: home

116b: flow layer

114a: protrusion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a gate electrode of a semiconductor device and a method of forming the same, and more particularly, to a floating gate of a flash memory device and a method of forming the same in a nonvolatile memory device having a stacked gate structure. .

Currently, a scheme for separating a device from a 70nm NAND flash memory device among the nonvolatile memory devices is a part of the floating gate to ensure the quality of the gate insulating film (or tunnel oxide film). The self-aligned shallow trench isolation (SA-STI) process, in which a lower gate electrode profile is first defined using a thin polysilicon layer and then separated, is widely used.

Hereinafter, the SA-STI process generally applied to NAND flash memory devices will be described.

First, as shown in FIG. 1A, a gate insulating film 11 and a poly silicon layer (hereinafter, referred to as a first polysilicon film) 12 as a lower layer for a floating gate are formed on a semiconductor substrate 10. And a pad nitride layer 13 are sequentially formed.

Subsequently, as illustrated in FIG. 1B, the pad nitride film 13, the first polysilicon film 12, the gate insulating film 11, and the substrate 10 are sequentially etched by performing a photo process and an etching process. As a result, a plurality of trenches 14 having a constant slope are formed in the substrate 10 to define an active region and a field region.

Subsequently, as illustrated in FIG. 1C, the HDP (High Density Plasma) oxide film is deposited so that the trench 14 is embedded and then planarized by performing a chemical mechanical polishing (CMP) process. As a result, an isolation layer 15 is formed in the trench 14.

Subsequently, as illustrated in FIG. 1D, the pad nitride layer 13 is removed to protrude a part of the device isolation layer 15.

Subsequently, as shown in FIG. 1E, a polysilicon film 16 (hereinafter referred to as a second polysilicon film), which is an upper layer for floating gates, is deposited on the entire structure including the device isolation film 15.

Subsequently, the second polysilicon film 16 is etched by performing a photo process and an etching process to form floating gates 17 that are separated from each other by the device isolation film 15.

In the SA-STI process, as described above, the gate insulating layer is first formed before the device isolation layer is formed, thereby preventing deterioration of the gate insulating layer due to the occurrence of a conventional moat. In addition, after the isolation layer 15 is formed, the second polysilicon layer 16 may be deposited on the first polysilicon layer 12 to increase the upper surface area of the floating gate 17. Thus, there is an advantage that the coupling ratio of the existing code flash memory device or data flash memory device can be secured as it is.

However, in the SA-STI process according to the related art, the second polysilicon film 16 is etched to have a slope due to the alignment of the second polysilicon film 16 and the limitation of the space therebetween. However, even in this case, there is a limit in increasing the coupling ratio because the space between the gate lines must be secured.

In order to increase the coupling ratio, the contact area between the IPO (Inter Poly Oxide) (hereinafter referred to as a dielectric film) and the floating gate 17 and the control gate (not shown) must be increased. However, in order to increase the contact area with the floating gate 17, the thickness of the second polysilicon layer 16 must be increased, so that the height of the entire floating gate is increased, which causes difficulties in the subsequent process of forming the control gate. Is generated.

Accordingly, the present invention has been made to solve the above problems, and increases the surface area without increasing the height of the gate electrode (floating gate) to increase the contact area between the dielectric film, thereby increasing the coupling ratio It is an object of the present invention to provide a gate electrode of a semiconductor device and a method of forming the same that can improve electrical characteristics of the device.

According to an aspect of the present invention for achieving the above object, the gate of the semiconductor device formed with protrusions protruding in the direction adjacent to both side walls so that neighbors on the device isolation layer defining the active region and the field region are separated from each other Provide an electrode.

In addition, according to another aspect of the present invention for achieving the above object, a first conductive film isolated by a device isolation film defining an active region and a field region, and formed on the first conductive film, the device isolation film Provided is a gate electrode of a semiconductor device including a second conductive film formed with protrusions protruding in a direction adjacent to both side walls such that neighboring ones are separated from each other.

In addition, according to another aspect of the present invention for achieving the above object, a step of providing a substrate on which the device isolation film is formed, the first conductive film isolated by the device isolation film is formed, and on the first conductive film Forming a second conductive film, forming first and second photoresist films flowing at different temperatures on the second conductive film, and etching the first and second photoresist films to form first and second photoresist films. Forming a pattern, etching the second conductive layer so as to remain at a predetermined thickness on the device isolation layer by performing a first etching process using the first and second photoresist layer patterns as an etching mask; Forming a flow layer on an inner wall of a groove formed in the second conductive film by the first etching process by flowing the first or second photoresist pattern through the first and second photoresist layers; Forming a protrusion on both sidewalls of the second conductive layer by etching the second conductive layer through a second photoresist pattern and a second etching process using the flow layer as an etching mask, and the first and second photosensitive layer patterns It provides a method of forming a gate electrode of a semiconductor device comprising the step of removing the flow layer.

In addition, according to another aspect of the present invention for achieving the above object, a step of providing a substrate on which the device isolation film is formed, the first conductive film isolated by the device isolation film is formed, and on the first conductive film Forming a second conductive film, forming the photoresist film, etching the photoresist film to form a photoresist pattern, and performing a first etching process using the photoresist pattern as an etch mask to form an upper portion of the device isolation layer. Etching the second conductive film so as to remain at a predetermined thickness; and forming a flow layer on an inner wall of the groove formed in the second conductive film by the first etching process by flowing the photosensitive film pattern through a flow process. And etching the second conductive layer through a second etching process using the photoresist pattern and the flow layer as an etching mask. It provides the step of forming a projection on both side walls of the conductive film and the photoresist pattern and the gate electrode forming a semiconductor device including a step of removing the layer flow.

In addition, according to another aspect of the present invention for achieving the above object, providing a substrate on which the device isolation film is formed, forming a conductive film on top of the entire structure including the device isolation film, and the top of the conductive film Forming a groove in the conductive film by forming a photoresist pattern in which a portion of the conductive film is exposed, and etching a predetermined portion of the conductive film through a first etching process using the photoresist pattern as an etching mask; Forming a flow layer on the inner wall of the groove by flowing the photoresist pattern through a process; and performing a second etching process using the photoresist pattern and the flow layer as an etching mask during the first etching process of the conductive layer. Forming a protrusion on both sidewalls of the conductive layer by etching the remaining portion by etching a predetermined portion; It provides a method of forming a gate electrode of a semiconductor device comprising the step of removing the film pattern and the flow layer.

In addition, according to another aspect of the present invention for achieving the above object, providing a substrate on which the device isolation film is formed, forming a conductive film on top of the entire structure including the device isolation film, and the top of the conductive film Forming first and second photoresist patterns of materials having different flow temperatures to expose a portion of the conductive film on the substrate, and performing a first etching process using the first and second photoresist patterns as an etching mask. Etching a predetermined portion of the conductive film to form a groove in the conductive film; flowing the first or second photosensitive film pattern through a flow process to form a flow layer on the inner wall of the groove; A predetermined portion of the conductive layer during the first etching process may be formed through a second etching process using the second photoresist layer pattern and the flow layer as an etching mask. Forming a protrusion on both sidewalls of the conductive layer by etching the remaining portions, and removing the first and second photoresist patterns and the flow layer. do.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

FIG. 2 is a cross-sectional view illustrating a gate electrode of a semiconductor device according to an exemplary embodiment of the present invention, for example, a floating gate of a nonvolatile memory device.

Referring to FIG. 2, the floating gate 122 of the nonvolatile memory device according to the embodiment of the present invention has a stacked structure of first and second polysilicon layers 112 and 114, and is a second polysilicon as an upper layer. Both side walls of the film 114 are formed in a stepped structure with protrusions 114a formed thereon.

The first polysilicon film 112 is formed at a height lower than that of the device isolation film 113, and the neighboring ones are separated by the device isolation film 113. The second polysilicon film 114 includes protrusions 114b formed on both side walls of the neighboring ones in directions facing each other. The protrusions 114a of the neighboring second polysilicon layers 114 are separated from each other on the device isolation layer 113.

The floating gate 122 having such a structure may increase the surface area by the increase by the protrusion 114a to increase the contact area with the dielectric film 123 formed along the surface thereof. That is, the protrusion 114b may be formed on the sidewall of the floating gate 122 to increase the surface area, thereby increasing the contact area with the dielectric film 123 to improve the coupling ratio.

Hereinafter, the floating gate forming method according to the embodiment of the present invention shown in FIG. 2 will be described.

First, as shown in FIG. 3A, a semiconductor substrate 110 cleaned by a pretreatment cleaning process is provided. The pretreatment cleaning process is performed with DHF (Diluted HF) followed by SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O), or with BOE (Buffer Oxide Etchant) followed by SC-1 It can be carried out as.

Subsequently, an ion implantation process for forming a well and an ion implantation process for adjusting a threshold voltage are performed. Before performing the ion implantation processes, a sacrificial oxide (not shown) is deposited on the semiconductor substrate 110, and an ion implantation process is performed using the sacrificial oxide film as a screen oxide. As a result, a well region (not shown) is formed in the semiconductor substrate 110. The well region may have a triple N-well formed in a P-type substrate, and a triple structure having a P well formed therein.

Next, a gate insulating film (or tunnel oxide film) 111 is formed on the semiconductor substrate 110. In this case, the gate insulating layer 111 is performed in a wet oxidation process within a temperature range of 750 ° C to 800 ° C.

Subsequently, an annealing process using N ₂ gas within a temperature range of 900 ° C. to 910 ° C. with respect to the gate insulating film 111 formed on the semiconductor substrate 110 as part of minimizing defect density with the semiconductor substrate 110 interface. It may be carried out for 20 to 30 minutes.

Subsequently, a conductive film, for example, a first polysilicon film 112, which is a lower layer of the floating gate, is deposited on the gate insulating layer 111. In this case, the first polysilicon layer 112 may be deposited as an undoped or doped silicon layer having low oxidation resistance. The undoped silicon film is deposited at a low pressure of 0.1torr to 0.3torr within the temperature range of 480 ° C to 550 ° C. In the case of the doped silicon film, a low pressure of 0.1torr to 0.3torr is used in a low pressure chemical vapor deposition (LPCVD) method using a SiH ₄ or Si ₂ H ₆ and PH ₃ gas within a temperature range of 480 ° C to 550 ° C. Deposit.

Next, a pad nitride film (not shown) is deposited on the first polysilicon film 112 as a protective layer. The pad nitride film is preferably deposited sufficiently thick in consideration of the degree of recession during the chemical mechanical polishing (CMP) process for forming a subsequent device isolation layer. The pad nitride layer functions to protect the first polysilicon layer 112 during the CMP process.

Subsequently, a plurality of trenches (not shown) may be formed to etch the pad nitride film, the first polysilicon film 112, the gate insulating film 111, and a portion of the substrate 110 to define an active region and a field region within the substrate 110. To form.

Subsequently, an insulating film for a device isolation film, such as an HDP oxide film, is deposited to fill the trench, and then planarized by performing a CMP process to form an isolated device isolation film 113 in the trench. In this case, the CMP process is performed using the pad nitride layer as an etch stop layer, and planarizes the upper part of the entire structure in which the device isolation layer 113 is formed. This results in a uniform Fox Height (EFH) that is uniform throughout the entire structure to be flattened.

Subsequently, the pad nitride film is removed using phosphoric acid (H ₃ PO ₄ ) (or a nitride film etching solution), and a conductive film, for example, a second polysilicon film 114, which is an upper layer of the floating gate, is formed thereon. In this case, the second polysilicon film 114 may be formed in the same manner as the first polysilicon film 112. However, the thickness may be appropriately changed according to the design of the device.

Subsequently, first and second photoresist layers 115 and 116 are sequentially applied on the second polysilicon layer 114. In this case, the first and second photoresist films 115 and 116 use materials that flow at different temperatures. That is, the first photoresist film 115 uses a material that flows at a lower temperature than the second photoresist film 116. For example, when the flow temperature of the first photosensitive film 115 is 90 ° C, the second photosensitive film 116 is coated with a material in which flow occurs at 80 ° C. In this case, the flow temperature in the subsequent flow process 119 (see FIG. 3D) is preferably performed at 85 ° C., which is an intermediate temperature of the flow temperatures of the first and second photosensitive films 115 and 116.

Subsequently, as illustrated in FIG. 3B, the first and second photoresist films 115 and 116 are etched by performing an exposure and development process using a photo mask. As a result, first and second photoresist layer patterns 115a and 116a through which a part of the second polysilicon layer 114 is exposed are formed. Here, a portion exposed from the second polysilicon layer 114 becomes a portion corresponding to the upper portion of the device isolation layer 113.

3C, the second polysilicon layer 114 is etched by performing an etching process 117 using the first and second photoresist layer patterns 115a and 116a as an etching mask. In this case, the second polysilicon layer 114 is not etched to expose the device isolation layer 113, but the etching condition is controlled to remain at a predetermined thickness on the device isolation layer 113. As a result, the trench 118 is formed in the second polysilicon layer 114, that is, at a portion corresponding to the upper portion of the device isolation layer 113.

Next, as illustrated in FIG. 3D, a flow process 119 is performed to flow the second photosensitive film pattern 116a onto the inner wall of the trench 118. As a result, the photoresist pattern 116a flows on the inner wall of the trench 118 to form the flow layer 116b. At this time, the flow process 119 is performed at an intermediate temperature of the flow temperatures of the first and second photoresist patterns 115a and 116a as described above, so that the second photoresist pattern 116a is more than the first photoresist pattern 115a. It is desirable to allow a lot of flow to occur. That is, if the flow temperature of the first photosensitive film pattern 115a is Tf1 and the flow temperature of the second photosensitive film pattern 116a is Tf2, the flow temperature TF at the flow process 119 is 'Tf2 <TF <Tf1'. Set within the range of '.

Subsequently, as shown in FIG. 3E, an etching process 120 using the first and second photoresist layer patterns 115a and 116a and the flow layer 118 as an etching mask is performed to remain on the device isolation layer 113. The second polysilicon film 114 is etched. As a result, protrusions 114a are formed on both sidewalls of the etched second polysilicon film 114 in a direction in which neighboring ones face each other. As a result, as the etching process 120 is performed while the space is reduced by the flow layer 116b, the second polysilicon film 114 is profiled in a step shape.

On the other hand, the shape of the protrusion 114a is not limited, and the portions that are adjacent to each other are adjacent to each other (vertical, rounding, slope) structure is possible.

Subsequently, as illustrated in FIG. 3F, a strip process is performed to remove the first and second photoresist patterns 115a and 116a and the flow layer 118. This forms a floating gate 122 having a profile as shown in the same figure. That is, the floating gate 122 has a stacked structure of first and second polysilicon films 112 and 114, and a stepped shape in which protrusions 114a are formed on both side walls of the second polysilicon film 114a as an upper layer. It is formed into a structure. As a result, the surface area of the floating gate 122 is increased to correspond to the protrusion 114a.

Subsequently, a dielectric film 123 is deposited along the surface of the second polysilicon film 114. At this time, the dielectric film 123 is formed in a stacked structure formed by properly combining an oxide film and a nitride film. For example, it is formed in ONO (Oxide / Nitride / Oxide), ONON (Oxide / NitrideOxide / Nitride), or ON (Oxide / Nitride) structure.

In the floating gate according to the present invention formed through such a process, the upper threshold dimension (CD2, see FIG. 3F) is the same as the upper threshold dimension (CD1, see FIG. 1E) of the floating gate according to the prior art, and the space between neighboring ones. (S2, see FIG. 3F) It is also possible to keep the same as the conventional space (S1, see FIG. 1E). In other words, the surface area of the floating gate can be increased as much as the protrusion 114a while maintaining the critical dimension and the space of the floating gate.

On the other hand, in the above-described embodiment of the present invention, a laminated photoresist film is used, but if the photoresist film thickness margin is sufficient, the etching process and the flow process may be performed using a single photoresist film. In addition, it is also applicable to the floating forming process using the STI process, not the SA-STI skip. In addition, the present invention may be applied to a floating gate forming process of a NOR flash memory device as well as a NAND flash memory device, and may be applied to a floating gate forming process of a nonvolatile memory device such as an EEPROM or an EPROM. The present invention can also be applied to gate electrodes having a single layer structure in semiconductor devices.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by forming protrusions on both side walls of the floating gate, the contact area between dielectric films can be increased by increasing the surface area of the floating gate while maintaining the height, critical dimension, and space of the floating gate. In this case, the coupling ratio may be increased to improve electrical characteristics of the device.

Claims (28)

delete delete delete delete delete delete Providing a substrate on which a first conductive film is formed so as to be isolated by an element isolation film; Forming a second conductive film on the first conductive film; Forming the photosensitive film; Etching the photoresist to form a photoresist pattern; Performing a first etching process using the photoresist pattern as an etching mask to etch the second conductive layer so as to remain at a predetermined thickness on the device isolation layer; Forming a flow layer on an inner wall of a groove formed in the second conductive film by the first etching process by flowing the photoresist pattern through a flow process; Etching the second conductive layer through a second etching process using the photoresist pattern and the flow layer as an etching mask to form protrusions on both sidewalls of the second conductive layer; And Removing the photoresist pattern and the flow layer Gate electrode forming method of a semiconductor device comprising a. The method of claim 7, wherein The flow process is a gate electrode forming method of a semiconductor device performed within the temperature range in which the photosensitive film pattern flows. The method of claim 8, The second conductive film is a gate electrode forming method of a semiconductor device to form a step. The method of claim 9, And the first and second conductive films are formed of an undoped or doped polysilicon film. The method according to any one of claims 7 to 10, And wherein the protruding portion is formed in a vertical, rounded or sloped structure where neighboring portions face each other. Providing a substrate on which a first conductive film is formed so as to be isolated by an element isolation film; Forming a second conductive film on the first conductive film; Forming first and second photoresist films flowing at different temperatures on the second conductive film; Etching the first and second photoresist layers to form first and second photoresist patterns; Performing a first etching process using the first and second photoresist layer patterns as an etching mask to etch the second conductive layer so as to remain at a predetermined thickness on the device isolation layer; Forming a flow layer on an inner wall of a groove formed in the second conductive film by the first etching process by flowing the first or second photoresist pattern through a flow process; Etching the second conductive layer through a second etching process using the first and second photoresist layer patterns and the flow layer as an etching mask to form protrusions on both sidewalls of the second conductive layer; And Removing the first and second photoresist patterns and the flow layer Gate electrode forming method of a semiconductor device comprising a. The method of claim 12, And the second photoresist film is formed of a material having a higher flow temperature than the first photoresist film. The method according to claim 12 or 13, And the flow step is performed at a temperature within a range between the flow temperatures of the first and second photosensitive film patterns. The method of claim 14, The second conductive film is a gate electrode forming method of a semiconductor device to form a step. The method of claim 15, And the first and second conductive films are formed of an undoped or doped polysilicon film. The method of claim 16, And wherein the protruding portion is formed in a vertical, rounded or sloped structure where neighboring portions face each other. Forming a conductive film on the substrate on which the device isolation film is formed Forming a photoresist pattern on a portion of the conductive film to expose a portion of the conductive film; Forming a groove in the conductive film by etching a portion of the conductive film through a first etching process using the photoresist pattern as an etching mask; Forming a flow layer on the inner wall of the groove by flowing the photoresist pattern through a flow process; Forming protrusions on both sidewalls of the conductive layer by etching a portion of the conductive layer which is etched during the first etching process through a second etching process using the photoresist pattern and the flow layer as an etching mask ; And Removing the photoresist pattern and the flow layer Gate electrode forming method of a semiconductor device comprising a. The method of claim 18, The flow process is a gate electrode forming method of a semiconductor device performed within the temperature range in which the photosensitive film pattern flows. The method of claim 19, The conductive film is a gate electrode forming method of a semiconductor device to form a step. The method of claim 20, And the conductive film is formed of an undoped or doped polysilicon film. The method according to any one of claims 18 to 21, And wherein the protruding portion is formed in a vertical, rounded or sloped structure where neighboring portions face each other. Forming a conductive film on the substrate on which the device isolation film is formed Forming first and second photoresist layer patterns formed of materials having different flow temperatures so that a portion of the conductive layer is exposed on the conductive layer; Forming a groove in the conductive film by etching a predetermined portion of the conductive film through a first etching process using the first and second photoresist pattern as an etching mask; Forming a flow layer on the inner wall of the groove by flowing the first or second photoresist pattern through a flow process; A portion of the conductive layer is etched during the first etching process through the second etching process using the first and second photoresist layer patterns and the flow layer as an etching mask, and the remaining portions are etched on both side walls of the conductive layer. Forming a protrusion; And Removing the first and second photoresist patterns and the flow layer Gate electrode forming method of a semiconductor device comprising a. The method of claim 23, And the second photoresist pattern is formed of a material having a flow temperature higher than that of the first photoresist pattern. The method of claim 23 or 24, And the flow step is performed at a temperature within a range between the flow temperatures of the first and second photosensitive film patterns. The method of claim 25, The conductive film is a gate electrode forming method of a semiconductor device to form a step. The method of claim 26, And the conductive film is formed of an undoped or doped polysilicon film. The method of claim 27, And wherein the protruding portion is formed in a vertical, rounded or sloped structure where neighboring portions face each other.

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