KR20070080765A - Non-volatile flash memory device and method of fabricating the same - Google Patents

Abstract

A non-volatile flash memory device is provided to minimize a parasitic capacitor formed in a direction of a bitline by decreasing the width of a floating gate electrode as compared with a conventional technique. An isolation layer(120b) for defining an active region is formed on a semiconductor substrate(110). A tunnel insulation layer(122) and a floating gate electrode(124) are formed on the active region. A step-type recess is formed in the isolation layer. The semiconductor substrate including the isolation layer with the step-type recess is covered with an inter-gate dielectric(134) and a control gate electrode(136). The inter-gate dielectric and the control gate electrode are extended to the lower surface of the step-type recess lower than the upper surface of the active region. The process for forming the isolation layer can include the following steps. The semiconductor substrate is etched to form a trench by using as an etch mask a hard mask pattern composed of a pad oxide layer and a silicon nitride layer. The trench is filled with a gap-fill insulation layer. The gap-fill insulation layer is planarized by a blanket etch process.

Description

Non-Volatile Flash Memory Device and Method of Fabricating the Same

1 is a plan view for explaining a general nonvolatile flash memory device;

2A and 2B are cross-sectional views taken along the lines A-A and B-B of FIG. 1, respectively, to illustrate a problem of the nonvolatile flash memory device according to the prior art;

3A to 3H are cross-sectional views taken along line B-B of FIG. 1 to illustrate a method of manufacturing a nonvolatile flash memory device according to an embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly to a nonvolatile flash memory device and a method of manufacturing the same.

A non-volatile flash memory device includes a tunnel insulating film, an electrically insulated floating gate, and a control gate constituting a word line. gate) and a gate interlayer insulating film interposed between the floating gate and the control gate. Nonvolatile flash memory devices are characterized by the potential of the floating gate being changed by injecting electrons into the floating gate by FN tunneling or channel hot carriers, or by extracting electrons by FN tunneling. This is a memory element in which a "0" or "1" state is stored.

As the semiconductor device is highly integrated, the design rule decreases, thereby reducing the size of the nonvolatile flash memory device. This causes a phenomenon in which the potential of the floating gate electrode is unnecessarily affected. The causes of such unnecessary effects include the voltages of the control gate electrodes adjacent to each other, the potential of the floating gate electrodes under the adjacent control gate electrodes, and the potential of the floating gate electrodes adjacent to each other under the same control gate electrode. . In particular, the influence of the specific floating gate threshold voltage by the potential of the floating gate electrodes adjacent to each other under the same control gate electrode is a problem in the case of a multi-level cell.

1 is a plan view illustrating a general nonvolatile flash memory device.

Referring to FIG. 1, an isolation layer 20a for defining an active region is disposed on a semiconductor substrate 10. The tunnel insulating film 22 is disposed on the active region between the device isolation films 20a. The floating gate electrode 24 is disposed on the tunnel insulating film 22. The lower portion of the floating gate electrode 24 has the same width as the tunnel insulating film 22, and the upper portion thereof has a wider width than the tunnel insulating film 22. A gate interlayer insulating film (not shown) and a control gate electrode 36 covering the floating gate electrode 24 and the upper surface of the device isolation film 20a are disposed.

2A and 2B are cross-sectional views taken along the lines A-A and B-B of FIG. 1, respectively, to illustrate a problem of the nonvolatile flash memory device according to the prior art.

Referring to FIG. 2A, parasitic capacitors exist between the floating gate electrodes 24 below the control gate electrodes 36 adjacent to each other. The parasitic capacitor is formed in the bit line direction by interference between the control gate electrodes 36 constituting the word line.

Referring to FIG. 2B, parasitic capacitors exist between the floating gate electrodes 24 adjacent to each other with the device isolation layer 20a therebetween under the same control gate electrode 36. The parasitic capacitor is formed in the word line direction by interference between the floating gate electrodes 24 adjacent to each other under the same control gate electrode 36.

Reference numerals 10, 22, and 34, which are not described in Figs. 2A and 2B, are semiconductor substrates, tunnel insulating films, and gate interlayer insulating films, respectively.

In the nonvolatile flash memory device as described above, as the spacing between the floating gate electrodes is reduced due to the high integration of the semiconductor device, the interference between the floating gate electrodes by the parasitic capacitor reaches a level that cannot be ignored. In addition, as the distance between the active region and the control gate electrode becomes narrower, when a program / erase operation in which a high voltage is applied is performed, charge is trapped in the thick edge portion of the tunnel insulation layer due to stress. trapping results in deterioration of the characteristics of the nonvolatile flash memory device and tunneling leakage current. Accordingly, there is a problem that the reliability of the nonvolatile flash memory device is lowered.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a nonvolatile flash memory device capable of securing reliability and a method of manufacturing the same.

The present invention provides a method of manufacturing a nonvolatile flash memory device. According to this method, first, an element isolation film that defines an active region is formed on a semiconductor substrate. A tunnel insulating film and a floating gate electrode are formed on the active region. Stepped recesses are formed in the device isolation film. A nonvolatile flash memory device can be manufactured by forming a gate interlayer insulating film and a control gate electrode covering a semiconductor substrate including a device isolation film having a stepped recess. The gate interlayer insulating film and the control gate electrode are characterized by extending to the lower surface of the stepped recess lower than the upper surface of the active region.

The device isolation layer may be formed by etching a semiconductor substrate using an hard mask pattern including a pad oxide layer and a silicon nitride layer as an etching mask to form a trench, and then filling the trench with a gap fill insulating layer. And etching the entire surface of the gap fill insulating layer to planarize the gap fill insulating layer.

The gap fill insulating film may be formed of silicon oxide, and the entire surface of the gap fill insulating film may be planarized by chemical mechanical polishing.

The method may further include exposing an active region of the semiconductor substrate by removing a hard mask pattern used as an etch mask for forming a trench.

Forming the floating gate electrode forms a tunnel insulating film on the active region and then forms a floating gate conductive film covering the semiconductor substrate including the tunnel insulating film. A mask film is formed on the floating gate conductive film. After forming a photoresist pattern having a wider width than the tunnel insulating film on the mask film, the mask film and the floating gate conductive layer may be etched using the photoresist pattern as an etching mask to form the mask film pattern and the floating gate electrode. .

The mask film may be formed of silicon nitride.

The floating gate electrode may be formed to have a lower structure having the same width as the tunnel insulating film and an upper structure having a wider width than the tunnel insulating film.

Forming a stepped recess in the device isolation film forms spacers on both sides of the floating gate electrode. The device isolation layer may be etched using the floating gate electrode and the spacer as an etching mask, and then the mask layer pattern and the spacer may be removed.

Forming the spacer may include forming an silicon nitride film covering the semiconductor substrate including the floating gate electrode and then anisotropically etching the silicon nitride film.

The present invention also provides a nonvolatile flash memory device. The memory device includes a device isolation film having a stepped recess formed in a predetermined region of a semiconductor substrate to define an active region, a tunnel insulating film formed on the active region, a floating gate electrode formed on the tunnel insulating film, and a floating gate electrode. And a control gate electrode formed on the gate interlayer insulating film and the gate interlayer insulating film covering the substrate, wherein the gate interlayer insulating film and the control gate electrode extend to the inside of the stepped recess.

The floating gate electrode may have a lower structure having the same width as the tunnel insulating layer and an upper structure having a wider width than the tunnel insulating layer.

The device isolation layer may have a top surface having the same height as a top surface of the bottom structure of the floating gate electrode, and may have a stepped recess in a center portion between the top structures of neighboring floating gate electrodes.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. In the drawings, the thicknesses of films and regions are exaggerated for clarity. Also, if it is mentioned that the film is on another film or substrate, it may be formed directly on the other film or substrate or a third film may be interposed therebetween.

3A to 3H are cross-sectional views taken along line B-B of FIG. 1 to explain a method of manufacturing a nonvolatile flash memory device according to an embodiment of the present invention.

Referring to FIG. 3A, a pad oxide film 112 and a silicon nitride film 114 are formed on the semiconductor substrate 110. After the photoresist is formed on the silicon nitride film 114, the photoresist pattern 116 is formed to expose the silicon nitride film 114 of the portion where the trench is to be formed by patterning. The pad oxide layer 112 may be formed by thermal oxidation.

Referring to FIG. 3B, the silicon nitride layer 114 and the pad oxide layer 112 are etched using the photoresist pattern 116 as an etch mask to form the pad oxide layer pattern 112a and the silicon nitride layer pattern 114a. Accordingly, a hard mask pattern including the pad oxide film pattern 112a and the silicon nitride film pattern 114a is provided.

After removing the photoresist pattern 116, the semiconductor substrate 110 is etched using the hard mask pattern as an etch mask to form a trench 118 defining an active region.

Referring to FIG. 3C, a gap-fill insulating film 120 covering the semiconductor substrate 110 including the trench 118 is formed. The gapfill insulating layer 120 may be formed of silicon oxide (SiO ₂ ).

Referring to FIG. 3D, the gap fill insulating layer 120 is etched all over to form a device isolation layer 120a having a flat top surface. The entire process of etching the gap fill insulating layer 120 may be planarized using a chemical mechanical polishing (CMP) method using the silicon nitride film pattern 114a as an etching mask.

After the planarization device isolation layer 120a is formed, the active region of the semiconductor substrate 110 is exposed by removing the silicon nitride layer pattern 114a and the pad oxide layer pattern 112a. The silicon nitride layer pattern 114a may be removed by wet etching using phosphoric acid. The pad oxide layer pattern 112a may be removed using a hydrofluoric acid (HF) + water (H ₂ O) + hydrogen peroxide (H ₂ O ₂ ) + ammonia (NH ₄ OH) mixed solution.

The tunnel insulating layer 122 is formed in the exposed active region of the semiconductor substrate 110. The tunnel insulating layer 122 may be formed by thermal oxidation.

Referring to FIG. 3E, after forming the floating gate conductive layer covering the semiconductor substrate 110 including the tunnel insulating layer 122, a mask layer is formed on the floating gate conductive layer. The floating gate conductive layer may be formed of doped polysilicon. The mask film may be formed of silicon nitride (SiN).

After the photoresist is formed on the mask film, the photoresist pattern 128 having a width larger than that of the tunnel insulating film 122 is formed by patterning.

The floating gate electrode 124 and the mask layer pattern 126 are formed by etching the mask layer and the floating gate conductive layer using the photoresist pattern 128 as an etching mask. Accordingly, the floating gate electrode 126 may be formed to have a lower structure having the same width as the tunnel insulating layer 122 and an upper structure having a wider width than the tunnel insulating layer 122.

Referring to FIG. 3F, after the photoresist pattern 128 is removed, a silicon nitride film covering the semiconductor substrate 110 including the floating gate electrode 124 and the mask layer pattern 126 is formed. Subsequently, the silicon nitride film is anisotropic dry etched to form a spacer 130 on the device isolation layer 120a on both sides of the floating gate electrode 124 and the mask layer pattern 126.

Referring to FIG. 3G, the device isolation layer 120b having a step recess 132 formed in a central portion thereof by anisotropic dry etching the device isolation layer 120a using the spacer 130 and the mask layer pattern 126 as an etch mask. ).

Since the spacer 130 and the mask layer pattern 126 are used as an etching mask, the element isolation layer 120b may have an upper surface having the same height as the upper surface of the lower structure of the floating gate electrode 124. In addition, the device isolation layer 120b may have a stepped recess 132 in a central portion between the upper structures of the floating gate electrodes 124 adjacent to each other.

Referring to FIG. 3H, the spacer 130 and the mask layer pattern 126 are removed by wet etching. The spacer 130 and the mask layer pattern 126 may be removed by wet etching using phosphoric acid.

A non-volatile flash memory device is manufactured by forming a gate interlayer insulating film 134 and a control gate electrode 136 covering a semiconductor substrate 110 including a device isolation film 120b having a stepped recess 132 in a central portion thereof. can do. The gate interlayer insulating layer 134 may be formed of an oxide film, a nitride film, or an oxide film (ONO: Oxide-Nitride-Oxide). The control gate electrode 136 may be formed of doped polysilicon. The gate interlayer insulating layer 134 and the control gate electrode 136 may extend to the inside of the stepped recess 132.

The nonvolatile flash memory device manufactured by the method according to the embodiment of the present invention can reduce the width of the floating gate electrode compared to the prior art, thereby minimizing the parasitic capacitor formed in the bit line direction. In addition, since the control gate electrode extends to the inside of the stepped recess, parasitic capacitors formed in the word line direction may be minimized due to a shielding effect of blocking an electric field between neighboring floating gate electrodes. In addition, by preventing the distance between the active region and the control gate electrode from becoming close, it is possible to prevent the deterioration of characteristics and leakage current of the nonvolatile flash memory device due to stress in a program / erase operation to which a high voltage is applied. Accordingly, it is possible to provide a nonvolatile flash memory device and a method of manufacturing the same, which can ensure reliability.

As described above, according to the present invention, by reducing cell interference between adjacent floating gate electrodes of a nonvolatile flash memory device, a nonvolatile flash memory device and a method of manufacturing the same can be provided.

Claims (13)

Forming an isolation layer defining an active region on the semiconductor substrate; Forming a tunnel insulating film and a floating gate electrode on the active region; Forming a stepped recess in the device isolation layer; And And forming a gate interlayer insulating film and a control gate electrode covering the semiconductor substrate including the device isolation layer having the stepped recess, wherein the gate interlayer insulating film and the control gate electrode are lower than an upper surface of the active region. And extending to the bottom surface of the stepped recess. The method of claim 1, Forming the device isolation layer, Forming a trench by etching the semiconductor substrate using an hard mask pattern including a pad oxide layer and a silicon nitride layer as an etching mask; Filling the trench with a gapfill insulating film; And And etching the entire surface of the gap-fill insulating film to planarize the gap-fill insulating film. The method of claim 2, The gap fill insulating film is formed of silicon oxide, characterized in that the manufacturing method of the nonvolatile flash memory device. The method of claim 2, And etching the entire surface of the gap-fill insulating film to planarize the same, using a chemical mechanical polishing method. The method of claim 2, And removing the hard mask pattern used as an etch mask to form the trench to expose an active region of the semiconductor substrate. The method of claim 1, Forming the tunnel insulating film and the floating gate electrode, Forming a tunnel insulating film on the active region; Forming a floating gate conductive film covering the semiconductor substrate including the tunnel insulating film; Forming a mask film on the floating gate conductive film; Forming a photoresist pattern having a width wider than that of the tunnel insulating film on the mask film; And And etching the mask layer and the floating gate conductive layer using the photoresist pattern as an etch mask to form a mask layer pattern and a floating gate electrode. The method of claim 6, And the mask film is formed of silicon nitride. The method of claim 6, And the floating gate electrode has a lower structure having the same width as the tunnel insulating film and an upper structure having a wider width than the tunnel insulating film. The method of claim 1, Forming a stepped recess in the device isolation layer, Forming spacers on both sides of the floating gate electrode; Etching the device isolation layer using the floating gate electrode and the spacer as an etching mask; And And removing the mask layer pattern and the spacers. The method of claim 9, Forming the spacers, Forming a silicon nitride film covering the semiconductor substrate including the floating gate electrode; And And anisotropically etching the silicon nitride film. An isolation layer formed in a predetermined region of the semiconductor substrate and having a stepped recess defining an active region; A tunnel insulating film formed on the active region; A floating gate electrode formed on the tunnel insulating film; A gate interlayer insulating film covering the semiconductor substrate including the floating gate electrode; And And a control gate electrode formed on the gate interlayer insulating layer, wherein the gate interlayer insulating layer and the control gate electrode extend into the stepped recess. The method of claim 11, And the floating gate electrode has a lower structure having the same width as the tunnel insulating film and an upper structure having a wider width than the tunnel insulating film. The method of claim 11, The device isolation layer has an upper surface having the same height as the upper surface of the lower structure of the floating gate electrode, and has the stepped recess in the center between the upper structures of the floating gate electrodes adjacent to each other. Flash memory devices.

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