CN111968982A - Nor flash memory structure and manufacturing method thereof - Google Patents
Nor flash memory structure and manufacturing method thereof Download PDFInfo
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- CN111968982A CN111968982A CN202011122506.1A CN202011122506A CN111968982A CN 111968982 A CN111968982 A CN 111968982A CN 202011122506 A CN202011122506 A CN 202011122506A CN 111968982 A CN111968982 A CN 111968982A
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
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Abstract
The invention provides a Nor flash memory structure and a manufacturing method thereof. In the Nor flash memory structure, an active region and isolation regions which are arranged in rows and columns along a first direction and a second direction are formed in a semiconductor substrate, two floating gates are arranged between every two adjacent isolation regions in the first direction in parallel, an interelectrode dielectric layer covers the upper surface and the side surface of each floating gate and the surface of the semiconductor substrate between the floating gates arranged along the first direction, a first spacing layer is positioned on the interelectrode dielectric layer and is provided with a first through hole formed in the thickness direction, the first through hole exposes the interelectrode dielectric layer covering the surface of the semiconductor substrate and the side surface of each floating gate, and a control gate is arranged in the first through hole. The control gate is arranged in the first through hole, so that a special photoetching procedure is not needed for manufacturing the control gate, the process flow is simplified, the production cost is saved, and the Nor flash memory structure can still realize better performance. The flash memory structure can be obtained by the manufacturing method.
Description
Technical Field
The invention relates to the technical field of flash memories, in particular to a Nor flash memory structure and a manufacturing method thereof.
Background
The Nor flash memory has high transmission efficiency, high reading speed and high cost efficiency under the condition of small capacity of 1 MB-4 MB, so that the Nor flash memory is widely applied to the technical field of semiconductors.
Fig. 1 is a schematic plan view of a Nor flash memory structure. Fig. 2 is a schematic sectional view taken along the direction AB in fig. 1. As shown in fig. 1 and fig. 2, in a conventional Nor flash memory structure, a semiconductor substrate 100 includes a plurality of isolation structures 101 arranged in parallel and an Active Area (AA) defined by the isolation structures 101, a plurality of floating gates 103 are arranged in rows and columns in the active area, each floating gate connects two adjacent isolation structures 101, and each memory cell includes a floating gate 102, an inter-electrode dielectric layer 103 disposed on a surface of the floating gate 102, a control gate 104 disposed on a surface of the inter-electrode dielectric layer 103, and a source region and a drain region respectively disposed in the active area at two sides of the floating gate. Along the row direction of the floating gates 102, the control gates 104 of a plurality of memory cells are connected so as to be shared by the plurality of memory cells.
In the Nor flash memory, the floating gate and the control gate are both formed by conductive polysilicon. In the manufacturing process of the Nor flash memory, an active region, a first polycrystalline silicon material layer (used for forming a floating gate) and an inter-electrode dielectric layer are firstly formed on a semiconductor substrate, then a second polycrystalline silicon material layer used for manufacturing a control gate is formed on the upper surface of the inter-electrode dielectric layer 103 in a deposition mode, the control gate 104 is obtained through photoetching and etching processes, then the polycrystalline silicon control gate 104 is used as a reference, a floating gate 102 is formed through a Self-Aligned-Source (Self-Aligned-Source) etching process for a plurality of times, and finally Source-drain injection, metal silicide manufacturing and Source-drain Contact hole (Contact, CT) manufacturing are carried out.
The Nor flash memory needs to be manufactured by depositing polycrystalline silicon and a dielectric layer for multiple times and inserting multiple photoetching and etching procedures, so that the technological process is complex and the production cost is high.
Disclosure of Invention
In order to simplify the manufacturing process flow of the flash memory, save the production cost and not influence the performance of the Nor flash memory obviously, the invention provides a Nor flash memory structure and a manufacturing method thereof.
In one aspect, the present invention provides a Nor flash memory structure, including:
the semiconductor substrate is internally provided with isolation regions which are respectively arranged in rows and columns along a first direction and a second direction and an active region positioned between the isolation regions, the active region comprises a floating gate region, a source region and a drain region, two floating gate regions are arranged between two adjacent isolation regions in the first direction in parallel, the source region extends along the first direction and separates two ringing rows of the isolation regions, the drain region is positioned between the two floating gate regions arranged in parallel, and the surface of the semiconductor substrate of the floating gate region is provided with a gate oxide layer and a floating gate positioned on the surface of the gate oxide layer;
the interelectrode dielectric layer continuously covers the upper surface and the side surfaces of the floating gate and the surface of the semiconductor substrate between the floating gates arranged along the first direction;
the first spacing layer is positioned on the interelectrode dielectric layer and is provided with a first through hole which is formed along the thickness direction, the first through hole is positioned between the floating gates which are arranged along the first direction, and the interelectrode dielectric layer covering the surface of the semiconductor substrate and the side surface of the floating gate is exposed;
and the control gate is arranged in the first through hole.
Optionally, the Nor flash memory structure further includes:
word lines disposed on the first spacers and extending in the first direction, the word lines being in electrical contact with the plurality of control gates arranged in the first direction.
Optionally, the first spacer layer further has second through holes opened along a thickness direction, and each of the second through holes exposes one of the drain regions.
Optionally, the Nor flash memory structure further includes:
the drain electrode plug is arranged in the second through hole;
the second spacer layer is arranged on the first spacer layer, and conducting plugs which are connected with the drain plugs in a one-to-one corresponding mode are formed in the second spacer layer;
and bit lines arranged on the second spacers and extending along the second direction, wherein the bit lines are electrically contacted with the plurality of conductive plugs arranged in the second direction.
Optionally, the Nor flash memory structure further includes:
and the etching barrier layer is positioned between the first spacing layer and the interelectrode dielectric layer, and the first through hole penetrates through the etching barrier layer.
Optionally, the material of the control gate is selected from at least one of metal, metal oxide, metal nitride and doped polysilicon.
Optionally, the control gate is made of tungsten, copper, ruthenium, cobalt, chromium, iron, palladium, molybdenum, tantalum, manganese, vanadium, gold, silver, or niobium.
Optionally, the inter-electrode dielectric layer is an ONO structure.
In another aspect, the present invention provides a method for fabricating a Nor flash memory structure, including:
obtaining a semiconductor substrate, wherein isolation regions which are respectively arranged in rows and columns along a first direction and a second direction and an active region positioned between the isolation regions are formed in the semiconductor substrate, the active region comprises a floating gate region, a source region and a drain region, two floating gate regions are arranged in parallel between two adjacent isolation regions in the first direction, the source region extends along the first direction and separates two adjacent rows of the isolation regions, the drain region is positioned between the two floating gate regions which are arranged in parallel, and a gate oxide layer and a floating gate positioned on the surface of the gate oxide layer are sequentially formed on the surface of the semiconductor substrate of the floating gate region;
forming an interelectrode dielectric layer on the semiconductor substrate, wherein the interelectrode dielectric layer continuously covers the upper surface and the side surfaces of the floating gates and the surface of the semiconductor substrate between the floating gates arranged along a first direction;
forming a first spacing layer on the interelectrode dielectric layer, and forming a first through hole in the first spacing layer along the thickness direction, wherein the first through hole is positioned between the floating gates arranged along the first direction and exposes the interelectrode dielectric layer covering the surface of the semiconductor substrate and the side surface of the floating gate;
and filling a conductive material in the first through hole to form a control gate.
Optionally, before forming the first spacer layer, the method further includes:
and forming an etching barrier layer on the semiconductor substrate, wherein the etching barrier layer covers the surface of the interelectrode dielectric layer.
Optionally, the step of forming a first spacer layer on the inter-electrode dielectric layer and forming a first through hole in the first spacer layer along the thickness direction includes:
forming a first spacing layer on the etching barrier layer;
etching the first spacing layer to form an opening penetrating through the first spacing layer between the floating gates arranged along the first direction, wherein the etching blocking layer is used for protecting the interelectrode dielectric layer from being etched;
and removing the etching barrier layer exposed from the opening, and forming the first through hole corresponding to the opening.
Optionally, the step of filling a conductive material in the first through hole to form a control gate includes:
depositing a conductive material on the semiconductor substrate, wherein the conductive material fills the first through hole;
and removing the conductive material covered on the first spacing layer, and taking the conductive material in the first through hole as the control gate.
Optionally, after forming the control gate, the manufacturing method further includes:
depositing a layer of word line material on the first spacer layer, the layer of word line material covering an upper surface of each of the control gates;
and etching the word line material layer to form a plurality of word lines extending along the first direction, wherein each word line is electrically contacted with the control gates arranged along the first direction.
Optionally, in the step of forming the first through hole by etching, a second through hole is further formed in the first spacer layer, and each second through hole exposes one drain region; in the step of forming the control gate by filling the first through hole with a conductive material, the second through hole is also filled with the conductive material, and the conductive material in the second through hole is used as a drain plug.
Optionally, after the word line is formed, the manufacturing method further includes:
forming a second spacer layer on the first spacer layer, and forming conducting plugs in the second spacer layer, wherein the conducting plugs are connected with the drain plugs in a one-to-one correspondence manner;
depositing a bit line material layer on the second spacer layer, wherein the bit line material layer covers the upper surface of each through plug;
and etching the bit line material layer to form a plurality of bit lines extending along the second direction, wherein each bit line is electrically connected with the drain plugs arranged along the second direction through the conducting plugs.
In the Nor flash memory structure, the first through hole is formed in the first spacing layer, the control grid is arranged in the first through hole, namely the control grid adopts a plug design, the interpolar dielectric layer passing through the inner wall of the hole can be coupled with the floating grid, the influence on the performance of the flash memory is small, in addition, the interpolar dielectric layer and the control grid in the Nor flash memory structure can be patterned without a special photoetching procedure, and the control grid can be manufactured in the process of forming the plug for connecting the drain region and the source region.
Compared with the conventional manufacturing method of the Nor flash memory structure, the manufacturing method of the Nor flash memory structure provided by the invention can reduce the execution times of material deposition, photoetching and etching processes, simplify the manufacturing process flow of the flash memory, and contribute to saving the production cost, and the performance of the formed Nor flash memory is not obviously reduced compared with the conventional structure.
Furthermore, in the manufacturing method of the Nor flash memory structure provided by the invention, before the first spacer layer is formed, an etching barrier layer can be formed on the inter-electrode dielectric layer, so that the influence of the process for etching the first spacer layer on the inter-electrode dielectric layer is avoided, and the performance of the formed Nor flash memory structure is improved.
Drawings
Fig. 1 is a schematic plan view of a Nor flash memory structure.
Fig. 2 is a schematic sectional view taken along the direction AB in fig. 1.
Fig. 3 is a schematic diagram illustrating locations of an isolation region, an active region and a floating gate in a Nor flash memory structure according to an embodiment of the invention.
Fig. 4 is a schematic plan view of a Nor flash memory structure according to an embodiment of the invention.
Fig. 5 to 8 are schematic cross-sectional views illustrating a Nor flash memory structure manufactured by a method for manufacturing a Nor flash memory structure according to an embodiment of the invention.
The reference numerals in fig. 1 and 2 illustrate:
100-a semiconductor substrate; 101-an isolation structure; 102-a floating gate; 103-an inter-electrode dielectric layer; 104-control gate.
The reference numerals in fig. 3 to 8 illustrate:
200-a semiconductor substrate; 200 a-source region; 200 b-drain region; 201-an isolation region; 202-a gate oxide layer; 203-floating gate; 204-an inter-electrode dielectric layer; 205-etching the barrier layer; 206-a first spacer layer; 206 a-a first through hole; 207-control gate; 208-source plug; 209-drain plug; 210-word line; 211-bit line.
Detailed Description
The Nor flash memory structure and the fabrication method thereof according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In particular embodiments, some features that are known in the art have not been described in order to avoid obscuring the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The embodiment of the invention provides a manufacturing method of a Nor flash memory, which comprises the following steps:
obtaining a semiconductor substrate, wherein isolation regions which are respectively arranged in rows and columns along a first direction and a second direction and an active region positioned between the isolation regions are formed in the semiconductor substrate, the active region comprises a floating gate region, a source region and a drain region, two floating gate regions are arranged in parallel between two adjacent isolation regions in the first direction, the source region extends along the first direction and separates two adjacent rows of the isolation regions, the drain region is positioned between the two floating gate regions which are arranged in parallel, and a gate oxide layer and a floating gate positioned on the surface of the gate oxide layer are sequentially formed on the surface of the semiconductor substrate of the floating gate region;
forming an interelectrode dielectric layer on the semiconductor substrate, wherein the interelectrode dielectric layer continuously covers the upper surface and the side surfaces of the floating gates and the surface of the semiconductor substrate between the floating gates arranged along a first direction;
forming a first spacing layer on the interelectrode dielectric layer, and forming a first through hole in the first spacing layer along the thickness direction, wherein the first through hole is positioned between the floating gates arranged along the first direction and exposes the interelectrode dielectric layer covering the surface of the semiconductor substrate and the side surface of the floating gate;
and filling a conductive material in the first through hole to form a control gate.
Fig. 3 is a schematic plan view illustrating locations of an isolation region, an active region and a floating gate in a Nor flash memory structure according to an embodiment of the invention. Fig. 4 is a schematic plan view of a Nor flash memory structure according to an embodiment of the invention. Fig. 5 to 8 are schematic cross-sectional views illustrating a Nor flash memory structure manufactured by a method for manufacturing a Nor flash memory structure according to an embodiment of the invention. Fig. 5 to 8 are schematic cross-sectional views along the CD direction in fig. 4. The following describes a method for fabricating the Nor flash memory structure according to this embodiment with reference to the accompanying drawings.
As shown in fig. 3 and 5, isolation regions 201 arranged in rows and columns along a first direction (x) and a second direction (y) and an active region (AA) located between the isolation regions 201 are formed in the semiconductor substrate, the active region includes a floating gate region, a source region 200a and a drain region 200b, two floating gate regions are arranged in parallel between two adjacent isolation regions 201 in the first direction, the source region 200a extends along the first direction and separates two adjacent rows of the isolation regions 201, the drain region 200b is located between two parallel floating gate regions, and a gate oxide layer 202 and a floating gate 203 located on the surface of the gate oxide layer 202 are sequentially formed on the surface of the semiconductor substrate in the floating gate region.
It is to be understood that the source region 200a and the drain region 200b may be located at both sides of the floating gate 203, respectively, in the first direction, as shown in fig. 3 and 4. The memory cells corresponding to the floating gates arranged along the first direction (row direction) may share the same source region 200a, i.e., the source regions corresponding to the floating gates of the same row may be connected. Memory cells corresponding to two floating gates juxtaposed between two of the isolation regions 201 adjacent in the first direction may share the drain region 200b between the two floating gates.
As shown in fig. 3 and 5, after the floating gate 203 is formed, the manufacturing method includes forming an inter-electrode dielectric layer 204 on the semiconductor substrate 200. The inter-electrode dielectric layer 204 continuously covers the upper surface and the side surfaces of the floating gates 203 and the surface of the semiconductor substrate 200 between the floating gates 203 arranged in the first direction. It should be understood that the inter-electrode dielectric layer 204 covers the gate oxide layer 202 on the surface of the semiconductor substrate 200. The inter-electrode dielectric layer 204 may separate the floating gate 203 from a control gate 207 to be formed later, and the control gate 207 may be coupled to the floating gate 203 through the inter-electrode dielectric layer 204.
Next, as shown in fig. 6 and 7, a first spacer 206 is formed on the inter-electrode dielectric layer 204, and a first through hole 206a is formed in the first spacer 206 along the thickness direction, where the first through hole 206a is located between the floating gates 203 arranged along the first direction, and exposes the inter-electrode dielectric layer 204 covering the surface of the semiconductor substrate 200 and the side surface of the floating gate 203.
The first through hole 206a may also expose a portion of the upper surface of the inter-electrode dielectric layer 204 adjacent to the upper surface of the floating gate 203. That is to say, in the first direction, the sidewall of the control gate 207 may extend above the floating gate 203, that is, the width of the control gate 207 in the first direction may be greater than the width of the isolation region 201, so that the manufacturing space of the control gate is relatively large, which is beneficial to reducing the manufacturing difficulty of the control gate, and at the same time, the coupling area between the control gate and the floating gate may also be increased; in the second direction, the width of the control gate 207 may be equal to or greater than the width of the floating gate 203.
In this embodiment, before forming the first spacer layer 206, the manufacturing method may further include: and forming an etching barrier layer 205 on the semiconductor substrate, wherein the etching barrier layer 205 covers the surface of the inter-electrode dielectric layer 204. The process of etching the first spacer layer 206 may be stopped on the surface of the etch stop layer 205, so as to avoid the influence of etching the first spacer layer 206 on the inter-electrode dielectric layer 204, which is beneficial to improving the performance of the Nor flash memory.
Specifically, as shown in fig. 6 and 7, the step of forming a first spacer layer 206 on the inter-electrode dielectric layer 204 and opening a first through hole 206a in the first spacer layer 206 along the thickness direction may include: first, a first spacer layer 206 is formed on the etch stop layer 205; then, etching the first spacer layer 206 to form an opening penetrating through the first spacer layer 206 between the floating gates 203 arranged along the first direction, wherein the inter-electrode dielectric layer 204 is protected from being etched by the etch stop layer 205; and removing the etching barrier layer 205 exposed by the opening, forming the first through hole 206a corresponding to the opening, wherein the first through hole 206a exposes the surface of the inter-electrode dielectric layer 204.
When the etching barrier layer 205 exposed by the opening is removed by etching, fluorocarbon with a low fluorine-carbon ratio may be used as an etching gas. The fluorocarbon may be, for example, C2H2F4、C4F8、C4F6、C5F8And the like. The fluorocarbon with low fluorine-carbon ratio is used as the etching gas, so that the etching selectivity is improved, the interpolar dielectric layer 204 on the shoulder part of the side wall of the floating gate can be effectively protected, the electric leakage and the short circuit caused by the damage of the interpolar dielectric layer 204 are avoided, and the bottom of the opening with the high aspect ratio can be well etched.
As shown in fig. 8, the step of filling the first via hole 206a with a conductive material to form the control gate 207 may include: depositing a conductive material on the semiconductor substrate (i.e., depositing a conductive material on the first spacer layer 206), the conductive material filling the first through hole 206 a; the conductive material overlying the first spacer 206 is removed, and the conductive material in the first via 206a is used as the control gate 207.
Wherein a Chemical Mechanical Polishing (CMP) process may be used to remove the conductive material overlying the first spacer layer 206. After the chemical mechanical polishing process, the upper surface of the conductive material may be flush with the first spacer, that is, the upper surface of the control gate 207 may be flush with the upper surface of the first spacer 206.
The conductive material may be deposited on the first spacer layer 206 by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. The chemical vapor deposition process may be Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).
As shown in fig. 4 and 8, in the step of forming the first through hole 206a by etching, second through holes may be further formed in the first spacer layer 206, each of the second through holes exposing one of the drain regions 200 b; in the step of filling the first via hole 206a with a conductive material to form the control gate 207, the conductive material may fill the second via hole, the conductive material in the second via hole may be used as a drain plug 209, and the drain plug 209 may be in electrical contact with the drain region 200 b.
Simultaneously with the formation of the first and second through holes, a third through hole may be formed in the first spacer layer 206, the third through hole exposing one of the source regions 200 a. The conductive material may also fill the third through hole, and the conductive material in the third through hole may be used as a source plug 208, where the source plug 208 is electrically contacted with the source region 200 a.
A plurality of floating gates 203 arranged along the first direction may share one source region 200a, and thus only one source plug 208 may be formed on the source region 200a, or a plurality of source plugs 208 may be formed for control; in the first direction, the drain region 200b is located between two floating gate regions arranged in parallel (i.e. between two floating gates 203 arranged in parallel), and since the drain region 200b is blocked by the isolation region 201, a drain plug 209 is formed on each drain region 200 b.
The first through hole, the second through hole, and the third through hole may also be formed by a Self-Aligned Contact (SAC) process as disclosed.
In this embodiment, referring to fig. 4, after forming the control gate 207, the manufacturing method may further include forming a plurality of word lines 210. The specific steps may include: depositing a layer of word line material over the first spacer layer 206, the layer of word line material covering the upper surface of each of the control gates 207; then, the word line material layer is etched to form a plurality of word lines 210 extending along the first direction, each of the word lines 210 being in electrical contact with a plurality of the control gates 207 arranged along the first direction.
After forming the word lines 210, the fabrication method may further include forming a plurality of bit lines 211. The specific steps may include: forming a second spacer on the first spacer 206 and forming a via plug in the second spacer, which is connected to the drain plug 209 in a one-to-one correspondence; then, depositing a bit line material layer on the second spacer layer, wherein the bit line material layer covers the upper surface of each through plug; and etching the bit line material layer to form a plurality of bit lines 211 extending along the second direction, wherein each bit line 211 is electrically connected to the plurality of drain plugs 209 arranged along the second direction through the via plugs. The second spacer layer may be the same material as the first spacer layer 206, for example, a silicon oxide layer, and may be formed by a Chemical Vapor Deposition (CVD) process.
In the method for manufacturing the Nor flash memory structure of this embodiment, the first through hole 206a is formed in the first spacer 206, and the control gate 207 is formed by filling the first through hole 206a with a conductive material, compared with a conventional Nor flash memory structure, a special photolithography process is not required for patterning in order to manufacture the control gate 207, and the control gate 207 may be manufactured in a process of forming a plug for connecting a source region and a drain region, so that the number of times of performing material deposition, photolithography, and etching processes may be reduced, a process flow is simplified, requirements on process conditions and man-hours are reduced, and production cost is saved.
Further, before forming the first spacer layer 206, an etching stop layer 205 may be formed on the inter-electrode dielectric layer 204, so as to avoid an influence of a process for etching the first spacer layer 206 on the inter-electrode dielectric layer 204, which is beneficial to improving the performance of the formed Nor flash memory structure.
The embodiment also provides a Nor flash memory structure, which can be manufactured by the manufacturing method of the Nor flash memory structure.
As shown in fig. 4 and 8, the Nor flash memory structure includes a semiconductor substrate 200, an inter-electrode dielectric layer 204, a first spacer 206, and a control gate 207. The semiconductor substrate 200 is formed with isolation regions 201 which are respectively arranged in rows and columns along a first direction (x) and a second direction (y) and an active region (AA) which is positioned between the isolation regions 201, the active region comprises floating gate regions, source regions 200a and drain regions 200b, two adjacent isolation regions 201 are arranged in parallel in the first direction, the source regions 200a extend along the first direction and separate two adjacent rows of the isolation regions 201, the drain regions 200b are positioned between two floating gate regions which are arranged in parallel, and the surface of the semiconductor substrate of each floating gate region is provided with a gate oxide layer 202 and a floating gate 203 positioned on the surface of the gate oxide layer 202. The inter-electrode dielectric layer 204 continuously covers the upper surface and the side surfaces of the floating gates 203 and the surface of the semiconductor substrate 200 between the floating gates 203 arranged in the first direction. The first spacer layer 206 is located on the inter-electrode dielectric layer 204 and has a first through hole 206a formed along the thickness direction, and the first through hole 206a is located between the floating gates 203 arranged along the first direction and exposes the inter-electrode dielectric layer 204 covering the surface of the semiconductor substrate 200 and the side surface of the floating gate 203. The control gate 207 is disposed in the first through hole 206 a.
Specifically, the first through hole 206a is located on the isolation region 201, and in the first direction, the first through hole 206a may further expose a portion of the upper surface of the inter-electrode dielectric layer 204 on the surface of the floating gate 203. That is, as shown in fig. 4 and fig. 8, in the first direction, the sidewall of the control gate 207 may extend above the floating gate 203, that is, the width of the control gate 207 in the first direction may be greater than the width of the isolation region 201, so that the manufacturing space of the control gate is relatively large, which is beneficial to reducing the manufacturing difficulty of the control gate, and at the same time, the coupling area between the control gate and the floating gate may also be increased; in the second direction, the width of the control gate 207 may be equal to or greater than the width of the floating gate 203.
As shown in fig. 8, the Nor flash memory structure may further include an etching stop layer 205, the etching stop layer 205 is located between the first spacer layer 206 and the inter-electrode dielectric layer 204, and the first through hole 206a penetrates through the etching stop layer 205. The etch stop layer 205 may protect the inter-electrode dielectric layer 204 when the first spacer layer 206 is etched. The thickness of the etching barrier layer can be 340-420 angstroms, for example 380 angstroms. The material of the etching barrier layer can be silicon nitride or silicon oxynitride.
In this embodiment, the gate oxide layer 202 may be a silicon oxide layer, and the material of the floating gate 203 may be polysilicon or metal. The inter-electrode dielectric layer 204 may be an Oxide-Nitride-Oxide (ONO) structure. In another embodiment, the inter-electrode dielectric layer may also be a silicon oxide layer.
The first spacer layer 206 may be a silicon oxide layer. The first spacer layer 206 may further have second through holes opened in a thickness direction, each of the second through holes exposing one of the drain regions 200 b. Furthermore, the first spacer layer 206 may further include a third through hole opened in the thickness direction, and the third through hole exposes one of the source regions 200 a.
The Nor flash memory structure may further include a source plug 208 and a drain plug 209, the source plug 208 being disposed in the third through hole, and the drain plug 209 being disposed in the second through hole. As shown in fig. 4, a source region 200a can be shared by a plurality of floating gates 203 arranged along the first direction, so that only one source plug 208 can be disposed on the source region 200a, or a plurality of source plugs 208 can be disposed for convenience of control; the drain regions 200b are separated by the isolation region 201, and thus a drain plug 209 is disposed on each drain region 200 b.
In this embodiment, the upper surface of the control gate 207 and the upper surface of the first spacer 206 may be flush. The material of the control gate 207 may be at least one selected from a metal, a metal oxide, a metal nitride, and a doped polysilicon. For example, the material of the control gate 207 may include tungsten, copper, ruthenium, cobalt, chromium, iron, palladium, molybdenum, tantalum, manganese, vanadium, gold, silver, niobium, or the like. The material of the source plug 208 and the drain plug 209 may be the same as the material of the control gate 207, so that the control gate 207, the source plug 208 and the drain plug 209 may be fabricated simultaneously in the same process, which facilitates the simplification of the flash memory fabrication process and the saving of the production cost.
As shown in fig. 4, a memory cell of the Nor flash memory includes a floating gate 203, a control gate 207, and Source (S, S) and Drain (Drain, D) regions located at two sides of the floating gate 203, and the Source region 200a and the Drain region 200b can be formed by ion implantation on the semiconductor substrate. A plurality of memory cells arranged in the first direction may share a same source region, a source plug 208 is formed on the source region, a drain plug 209 is formed on a drain region of each memory cell, and the source region and the drain region may be controlled by the source plug 208 and the drain plug 209, respectively.
To control the Nor flash memory, the Nor flash memory structure may further include a plurality of Word lines (Word lines) 210. Specifically, as shown in fig. 4, the word line 210 may be disposed on the first spacer 206 and extend along the first direction, and the word line 210 is in electrical contact with the plurality of control gates 207 arranged along the first direction.
The Nor flash memory structure may further include a second spacer layer disposed on the first spacer layer 206, and Bit lines (Bit lines) 211, in which via plugs connected to the drain plugs 209 in a one-to-one correspondence are formed; the bit line 211 may be disposed on the second spacer and extend along the second direction, and the bit line 211 may be in electrical contact with a plurality of the via plugs arranged along the second direction. The source plug 208 may be electrically connected to other conductive lines so that the source region 200a may be operated through the conductive lines and the source plug 208.
When writing the memory cell, applying a positive voltage to the control gate 207 through the word line 210, and applying appropriate voltages to the source region (source terminal) and the drain region (drain terminal) through the source plug 208 and the drain plug 209, electrons can be injected into the floating gate 203 by Hot electron injection (Hot electron injection), and charges can be accumulated in the floating gate 203, i.e. programming of the memory cell is realized; when the memory cell is subjected to an Erase operation (Erase), negative voltage is applied to the control gate 207 through the word line 210, and appropriate voltages are applied to the source region and the drain region through the source plug 208 and the drain plug 209, electrons in the floating gate 203 can be pulled into the semiconductor substrate 200 through the F-N tunneling effect, that is, the electron erasing of the floating gate 203 (i.e., the erasing of the memory cell) is realized; when the memory cell is Read, a small voltage is applied to the control gate 207 through the word line 210, and appropriate voltages are applied to the source region and the drain region through the source plug 208 and the drain plug 209, so that a conductive channel exists between the source region and the drain region without changing the number of electrons stored in the floating gate 203, if electrons exist in the floating gate 203, a "0" can be Read from the drain terminal through the drain plug 209, and if no electrons exist in the floating gate, a "1" can be Read from the drain terminal, so that the memory cell can be Read.
The inventor has calculated a coupling ratio (coupling ratio) between the conventional Nor flash memory structure and the Nor flash memory structure of this embodiment, where the coupling ratio of the conventional Nor flash memory structure is about 73%, and the coupling ratio of the Nor flash memory structure of this embodiment is 66.7%, which are not very different. That is, the Nor flash memory structure of the present embodiment has a function that is not much different from that of the conventional Nor flash memory structure.
In the Nor flash memory structure of the present embodiment, a first via hole 206a is formed in the first spacer 206, and the control gate 207 is disposed in the first via hole 206a, i.e., the control gate 207, is designed as a plug, the inter-electrode dielectric layer 204 passing through the inner wall of the first via hole can be coupled to the floating gate 203, the performance of the flash memory is little affected, and in the Nor flash memory structure, the control gate 207 does not need a special photolithography process for patterning, the control gate 207 may also be fabricated during the process of forming plugs for source and drain regions, compared with the conventional Nor flash memory structure, the Nor flash memory structure of the embodiment can not affect the performance of the flash memory basically, the required photoetching and etching procedures are reduced, the manufacturing process flow of the flash memory is simplified, the requirements on process conditions and working hours are reduced, and the production cost is saved.
It should be noted that the terms "first", "second", "third", and the like in the description are used for distinguishing various components, elements, steps, and the like in the description, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any variations and modifications of the present invention may be made by those skilled in the art without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above, and therefore, any modifications, equivalent variations and modifications made to the above embodiments according to the technical essence of the present invention are within the protection scope of the present invention.
Claims (15)
1. A Nor flash memory structure, comprising:
the semiconductor substrate is internally provided with isolation regions which are respectively arranged in rows and columns along a first direction and a second direction and an active region positioned between the isolation regions, the active region comprises a floating gate region, a source region and a drain region, two floating gate regions are arranged between two adjacent isolation regions in the first direction in parallel, the source region extends along the first direction and separates two adjacent rows of the isolation regions, the drain region is positioned between the two floating gate regions arranged in parallel, and the surface of the semiconductor substrate of the floating gate region is provided with a gate oxide layer and a floating gate positioned on the surface of the gate oxide layer;
the interelectrode dielectric layer continuously covers the upper surface and the side surfaces of the floating gate and the surface of the semiconductor substrate between the floating gates arranged along the first direction;
the first spacing layer is positioned on the interelectrode dielectric layer and is provided with a first through hole which is formed along the thickness direction, the first through hole is positioned between the floating gates which are arranged along the first direction, and the interelectrode dielectric layer covering the surface of the semiconductor substrate and the side surface of the floating gate is exposed;
and the control gate is arranged in the first through hole.
2. The Nor flash memory structure of claim 1, further comprising:
word lines disposed on the first spacers and extending in the first direction, the word lines being in electrical contact with the plurality of control gates arranged in the first direction.
3. The Nor flash memory structure of claim 1 wherein said first spacer layer further has second through holes opened in a thickness direction, each of said second through holes exposing one of said drain regions.
4. The Nor flash memory structure of claim 3, further comprising:
the drain electrode plug is arranged in the second through hole;
the second spacer layer is arranged on the first spacer layer, and conducting plugs which are connected with the drain plugs in a one-to-one corresponding mode are formed in the second spacer layer;
and bit lines disposed on the second spacers and extending in the second direction, the bit lines being in electrical contact with the plurality of via plugs arranged in the second direction.
5. The Nor flash memory structure of any of claims 1-4, further comprising:
and the etching barrier layer is positioned between the first spacing layer and the interelectrode dielectric layer, and the first through hole penetrates through the etching barrier layer.
6. The Nor flash memory structure of claim 1 wherein the control gate is of a material selected from at least one of a metal, a metal oxide, a metal nitride, and doped polysilicon.
7. The Nor flash memory structure of claim 6, wherein the material of the control gate comprises tungsten, copper, ruthenium, cobalt, chromium, iron, palladium, molybdenum, tantalum, manganese, vanadium, gold, silver, or niobium.
8. The Nor flash memory structure of claim 1 wherein said inter-electrode dielectric layer is an ONO structure.
9. A manufacturing method of a Nor flash memory structure is characterized by comprising the following steps:
obtaining a semiconductor substrate, wherein isolation regions which are respectively arranged in rows and columns along a first direction and a second direction and an active region positioned between the isolation regions are formed in the semiconductor substrate, the active region comprises a floating gate region, a source region and a drain region, two floating gate regions are arranged in parallel between two adjacent isolation regions in the first direction, the source region extends along the first direction and separates two adjacent rows of the isolation regions, the drain region is positioned between the two floating gate regions which are arranged in parallel, and a gate oxide layer and a floating gate positioned on the surface of the gate oxide layer are sequentially formed on the surface of the semiconductor substrate of the floating gate region;
forming an interelectrode dielectric layer on the semiconductor substrate, wherein the interelectrode dielectric layer continuously covers the upper surface and the side surfaces of the floating gates and the surface of the semiconductor substrate between the floating gates arranged along a first direction;
forming a first spacing layer on the interelectrode dielectric layer, and forming a first through hole in the first spacing layer along the thickness direction, wherein the first through hole is positioned between the floating gates arranged along the first direction and exposes the interelectrode dielectric layer covering the surface of the semiconductor substrate and the side surface of the floating gate;
and filling a conductive material in the first through hole to form a control gate.
10. The method of fabricating a Nor flash memory structure of claim 9, further comprising, prior to forming the first spacer layer:
and forming an etching barrier layer on the semiconductor substrate, wherein the etching barrier layer covers the surface of the interelectrode dielectric layer.
11. The method of claim 10, wherein the step of forming a first spacer layer on the inter-electrode dielectric layer and forming a first through hole in the first spacer layer along a thickness direction comprises:
forming a first spacing layer on the etching barrier layer;
etching the first spacing layer to form an opening penetrating through the first spacing layer between the floating gates arranged along the first direction, wherein the etching blocking layer is used for protecting the interelectrode dielectric layer from being etched;
and removing the etching barrier layer exposed from the opening, and forming the first through hole corresponding to the opening.
12. The method of claim 9, wherein the step of filling the first via with a conductive material to form a control gate comprises:
depositing a conductive material on the semiconductor substrate, wherein the conductive material fills the first through hole;
and removing the conductive material covered on the first spacing layer, and taking the conductive material in the first through hole as the control gate.
13. The method of fabricating a Nor flash memory structure of claim 12, wherein after forming the control gate, the method of fabricating further comprises:
depositing a layer of word line material on the first spacer layer, the layer of word line material covering an upper surface of each of the control gates;
and etching the word line material layer to form a plurality of word lines extending along the first direction, wherein each word line is electrically contacted with the control gates arranged along the first direction.
14. The method of claim 13, wherein in the step of forming the first via hole by etching, second via holes are further formed in the first spacer layer, each of the second via holes exposing one of the drain regions; in the step of forming the control gate by filling the first through hole with a conductive material, the second through hole is also filled with the conductive material, and the conductive material in the second through hole is used as a drain plug.
15. The method of fabricating a Nor flash memory structure of claim 14, wherein after forming the word line, the method further comprises:
forming a second spacer layer on the first spacer layer, and forming conducting plugs in the second spacer layer, wherein the conducting plugs are connected with the drain plugs in a one-to-one correspondence manner;
depositing a bit line material layer on the second spacer layer, wherein the bit line material layer covers the upper surface of each through plug;
and etching the bit line material layer to form a plurality of bit lines extending along the second direction, wherein each bit line is electrically connected with the drain plugs arranged along the second direction through the conducting plugs.
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