CN113611745B - Method for manufacturing semiconductor device - Google Patents
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- CN113611745B CN113611745B CN202110877890.4A CN202110877890A CN113611745B CN 113611745 B CN113611745 B CN 113611745B CN 202110877890 A CN202110877890 A CN 202110877890A CN 113611745 B CN113611745 B CN 113611745B
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 258
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000004061 bleaching Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate; forming a first opening exposing the substrate on the floating gate layer and the control gate layer; forming a first word line structure and a second word line structure on two sides of the first opening respectively; forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer; and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask, so that the first word line structure and the second word line structure respectively form a first gate structure and a second gate structure. According to the invention, the first opening is formed to enable the first photoresist layer to cover the first word line structure, the second word line structure and the first opening, so that the pattern area of the first photoresist layer is increased, the process window of the first photoresist layer is increased, the photoresist drifting is reduced or avoided, and the product yield is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technology, and in particular, to a method for manufacturing a semiconductor device.
Background
The Nor Flash memory (Nor Flash) is used as a nonvolatile Flash memory device, can directly run application programs in the device, and has the characteristic of high transmission efficiency. Fig. 1 is a layout diagram of a Nor flash memory, and fig. 2 is a schematic cross-sectional view of the Nor flash memory shown in fig. 1 along the AA' direction. Referring to fig. 2, one control gate (the control gate is formed by etching the control gate material layer 120 later) is disposed on both sides of each word line (i.e., the first word line 131 and the second word line 132) of the Nor flash memory, and both ends of the control gate need to have a certain area to connect the contact hole, and meanwhile, the two control gates need to be isolated, so that the photoresist layer 140 as shown in fig. 1 needs to be formed. Referring to fig. 1, the control gate material layer 120 covered by the photoresist layer 140 is left in a subsequent etching process to connect the contact holes, and the control gate material layer 120 exposed by the photoresist layer 140 is removed in the subsequent etching process to separate two control gates (not shown).
However, as the level of integrated circuit fabrication technology continues to advance, the size of the Nor flash memory continues to shrink, and the area of the individual features in the photoresist layer 140 also correspondingly shrinks, such that the process window of the Nor flash memory continues to shrink. When the area of the single pattern in the photoresist layer 140 is too small, a photoresist drift may occur, and may adversely affect the subsequent process, and affect the morphology and performance of the Nor device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which increases the pattern area of a first photoresist layer, thereby increasing a process window of the first photoresist layer.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
Providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate;
forming a first opening exposing the substrate on the floating gate layer and the control gate layer;
forming a first word line structure and a second word line structure on two sides of the first opening respectively;
Forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer;
And etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask, so that the first word line structure and the second word line structure form a first gate structure and a second gate structure respectively.
Optionally, the forming the first opening includes:
Forming a patterned second photoresist layer on the control gate layer;
And etching the floating gate layer and the control gate layer by taking the patterned second photoresist layer as a mask layer to form the first opening.
Optionally, the forming the first word line structure and the second word line structure includes:
Forming a hard mask layer on the control gate layer to fill the first opening;
Forming a second opening and a third opening exposing part of the control gate layer on the hard mask layer, and forming a first side wall on the side walls of the second opening and the third opening;
Etching the control gate layer by taking the hard mask layer and the first side wall as masks, exposing part of the floating gate layer by the second opening and the third opening, and forming a second side wall covering the control gate layer on the side walls of the second opening and the third opening;
Etching the floating gate layer by taking the hard mask layer, the first side wall and the second side wall as masks, so that part of the substrate is exposed by the second opening and the third opening, and a third side wall is formed on the side walls and the bottoms of the second opening and the third opening;
and forming word lines in the second opening and the third opening to form a first word line structure and a second word line structure, wherein the first word line structure comprises a first side wall, a second side wall, a third side wall and word lines in the second opening, and the second word line structure comprises a first side wall, a second side wall, a third side wall and word lines in the third opening.
Optionally, after forming the first word line structure and the second word line structure, before forming the first photoresist layer, the method further includes:
and removing the hard mask layer to expose the first opening and part of the control gate layer.
Optionally, a set width exists between a sidewall of the first word line structure adjacent to the first opening and a sidewall of the first opening adjacent to the second opening, and a sidewall of the second word line structure adjacent to the first opening is flush with a sidewall of the first opening adjacent to the third opening.
Optionally, the first photoresist layer covers the first word line structure, the second word line structure, the first opening, and a control gate layer between the first word line structure and the first opening.
Optionally, after forming the first gate structure and the second gate structure, the method further includes:
removing the first photoresist layer;
forming an interlayer dielectric layer on the surfaces of the substrate, the control gate layer, the first word line structure and the second word line structure, and forming a contact hole exposing the control gate layer in the interlayer dielectric layer;
forming an electrical connection in the contact hole;
and forming a metal layer on the interlayer dielectric layer, wherein the electric connecting piece is connected with the metal layer and the control gate layer.
Optionally, a first dielectric layer is further formed between the substrate and the floating gate layer, and a second dielectric layer is further formed between the floating gate layer and the control gate layer.
Optionally, the first dielectric layer is a silicon oxide layer, and the second oxide layer is an ONO laminated structure formed by stacking a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
Optionally, the method for manufacturing a semiconductor device is used for manufacturing the Nor flash memory.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate; forming a first opening exposing the substrate on the floating gate layer and the control gate layer; forming a first word line structure and a second word line structure on two sides of the first opening respectively; forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer; and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask, so that the first word line structure and the second word line structure form a first gate structure and a second gate structure respectively. According to the invention, the first openings are formed on the control gate layer and the floating gate layer, so that the first photoresist layer covers the first word line structure, the second word line structure and the first openings, and the pattern area of the first photoresist layer is increased, so that the process window of the first photoresist layer is increased, the occurrence of photoresist bleaching of the first photoresist layer is reduced or avoided, and the product yield is improved.
Drawings
FIG. 1 is a design layout of a Nor flash memory;
FIG. 2 is a schematic cross-sectional view of the Nor flash memory shown in FIG. 1 along the AA' direction;
FIGS. 3-6 are schematic diagrams illustrating partial steps in a method for fabricating a Nor flash memory;
fig. 7 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 8-16 are schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Wherein, the reference numerals are as follows:
100-a substrate; 110-a layer of floating gate material; 120-a control gate material layer; 131-a first word line; 132-a second word line; 140 photoresist layer;
200-substrate; 210-a layer of floating gate material; 211-a floating gate layer; 220-a control gate material layer; 221-a control gate layer; 231-a first word line; 232-a second word line; 240-photoresist layer; 250-interlayer dielectric layer; 251-electrical connector; 260-a metal layer;
300-substrate; 301 a first opening; 302-a second opening; 303-a third opening; 310-a first dielectric layer; 320-a floating gate layer; 321-floating gate; 330-a second dielectric layer; 340-a control gate layer; 341-a control gate; 350-a hard mask layer; 351-a first side wall; 352-second side wall; 353-third side wall; 360-word line; 370-a first photoresist layer; 380-an interlayer dielectric layer; 381-electrical connectors; 390-metal layer.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 3-6 are schematic structural diagrams corresponding to partial steps in a method for manufacturing a Nor flash memory.
First, referring to fig. 3, the Nor flash memory includes a substrate 200, a floating gate material layer 210 and a control gate material layer 220 are sequentially formed on the substrate 200, grooves (not shown) exposing a portion of the substrate 200 are formed on the floating gate material layer 210 and the control gate material layer 220, and a first word line 231 and a second word line 232 are formed in the grooves. Optionally, a first dielectric layer is further formed between the substrate 200 and the floating gate material layer 210, and a second dielectric layer is further formed between the floating gate material layer 210 and the control gate material layer 220. Optionally, the first dielectric layer is a silicon oxide layer, and the second dielectric layer is an ONO laminated structure formed by stacking a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
Referring to fig. 4 and 5, a patterned photoresist layer 240 is formed on the first word line 231 and the second word line 232, and a portion of the control gate material layer 220 covering a side of the first word line 231 near the second word line 232 is extended; the control gate material layer 220 and the floating gate material layer 210 are etched using the patterned photoresist layer 240 as a mask to form a control gate layer 221 and a floating gate layer 211. At this time, a portion of the control gate layer 221 of the first word line 231 near the side of the second word line 232 is protected by the photoresist layer 240 and is exposed to air after the photoresist layer 240 is removed. Note that fig. 4 and 5 are only one cross section of the semiconductor device (similar to the cross section along the AA' direction in fig. 1), and therefore, the photoresist layer 240 formed on the surface of the second word line 232 is not shown in fig. 4 and 5. In addition, before the patterned photoresist layer 240 is formed, the surfaces of the first and second word lines 231 and 232 are formed with a silicon oxide layer (not shown) through a thermal oxidation growth process, and thus, the silicon oxide layer may serve as a barrier layer to protect portions of the first and second word lines 231 and 232 that are not covered by the patterned photoresist layer 240 during the formation of the control gate layer 221 and the floating gate layer 211.
Referring to fig. 6, an interlayer dielectric layer 250 and a metal layer 260 are sequentially formed on the substrate 200, the first word line 231, the second word line 232, and the exposed control gate layer 221, a contact hole (not shown) is formed in the interlayer dielectric layer 250 above the exposed control gate layer 221, and an electrical connector 251 is formed in the contact hole to connect the control gate layer 221 and the metal layer 260.
However, as the level of integrated circuit fabrication technology continues to advance, the size of the Nor flash memory continues to shrink, as does the pattern area of the photoresist layer 240. When the pattern area of the photoresist layer 240 is too small, the process window of the photoresist layer 240 is too small, which may cause a drift and adversely affect the subsequent process, affecting the morphology and performance of the Nor device.
In order to solve the problem of process window shrinkage caused by too small photoresist layer pattern area, the invention provides a manufacturing method of a semiconductor device. Fig. 7 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 7, the method for manufacturing a semiconductor device according to the present embodiment includes:
Step S01: providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate;
step S02: forming a first opening exposing the substrate on the floating gate layer and the control gate layer;
step S03: forming a first word line structure and a second word line structure on two sides of the first opening respectively;
Step S04: forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer;
step S05: and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask, so that the first word line structure and the second word line structure form a first gate structure and a second gate structure respectively.
Fig. 8 to 16 are schematic structural views corresponding to each step in the method for manufacturing a semiconductor device according to an embodiment of the present invention, and the method for manufacturing a semiconductor device according to the embodiment is described in detail below with reference to fig. 8 to 16.
First, referring to fig. 8, step S01 is performed to provide a substrate 300, on which a floating gate layer 320 and a control gate layer 340 are sequentially formed on the substrate 300. In this embodiment, a first dielectric layer 310 is further formed between the substrate 300 and the floating gate layer 320, and a second dielectric layer 330 is further formed between the floating gate layer 320 and the control gate layer 340. Optionally, the first dielectric layer 310 is a silicon oxide layer, and the second dielectric layer 330 is an ONO stack structure formed by stacking a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
Next, referring to fig. 9, step S02 is performed to form a first opening 301 exposing the substrate 300 on the floating gate layer 320 and the control gate layer 340. In this embodiment, the process of forming the first opening 301 includes: forming a patterned second photoresist layer (not shown) on the control gate layer 340; the floating gate layer 320 and the control gate layer 340 are etched with the patterned second photoresist layer as a mask layer to form the first opening 301.
Subsequently, referring to fig. 10-13, step S03 is performed to form a first word line structure and a second word line structure on both sides of the first opening 301, respectively. Specifically, the process of forming the first word line structure and the second word line structure includes: referring to fig. 10, a hard mask layer 350 is formed on the control gate layer 340 to fill the first opening 301; referring to fig. 11, a second opening 302 and a third opening 303 exposing a portion of the control gate layer 340 are formed on the hard mask layer 350, and a first sidewall 351 is formed on sidewalls of the second opening 302 and the third opening 303; referring to fig. 12, the hard mask layer 350 and the first sidewall 351 are used as masks to etch the control gate layer 340, so that the second opening 302 and the third opening 303 expose part of the floating gate layer 320, and a second sidewall 352 covering the control gate layer 340 is formed on the sidewalls of the second opening 302 and the third opening 303; etching the floating gate layer 320 by taking the hard mask layer 350, the first side wall 351 and the second side wall 352 as masks, so that the second opening 302 and the third opening 303 expose part of the substrate 300, and forming a third side wall 353 on the side walls and the bottom of the second opening 302 and the third opening 303; next, referring to fig. 13, a word line 360 is formed in the second opening 302 and the third opening 303 to form the first word line structure and the second word line structure, wherein the first word line structure includes a first sidewall 351, a second sidewall 352, a third sidewall 353 and a word line 360 in the second opening 302, and the second word line structure includes a first sidewall 351, a second sidewall 352, a third sidewall 353 and a word line 360 in the third opening 303.
It should be noted that, a set width exists between the sidewall of the first word line structure near the first opening 301 and the sidewall of the first opening 301 near the second opening 302, and the sidewall of the second word line structure near the first opening 301 is flush with the sidewall of the first opening 301 near the third opening 303. Optionally, after performing step S03, before performing step S04, the method further includes: the hard mask layer 350 is removed to expose the first opening 301 and a portion of the control gate layer 340.
Next, referring to fig. 14, step S04 is performed to form a first photoresist layer 370 in the first opening 301 and extend to cover the first word line structure and the second word line structure, so as to enlarge a process window of the first photoresist layer 370. Since the control gate layer 340 having a predetermined width is exposed between the first word line structure and the first opening 301 formed in step S03, the first photoresist layer 370 covers the first word line structure, the second word line structure and the first opening 301, and also covers the control gate layer 340 exposed between the first word line structure and the first opening 301.
Subsequently, referring to fig. 15, step S05 is performed to etch the floating gate layer 320 and the control gate layer 340 using the first photoresist layer 370 as a mask, so that the first and second word line structures form a first and second gate structure, respectively. The first gate structure comprises the first word line structure, a control gate 341 and a floating gate 321 under the first word line structure, and a part of the surface of the control gate 341 of the first gate structure, which is close to one side of the first opening 301, is exposed; the second gate structure includes the second word line structure and the control gate 341 and floating gate 321 under the second word line structure.
Further, referring to fig. 16, after forming the first gate structure and the second gate structure, further comprising: removing the first photoresist layer 370; forming an interlayer dielectric layer 380 on the surfaces of the substrate 300, the first word line structure and the second word line structure, and forming a contact hole (not shown) exposing the control gate 341 in the interlayer dielectric layer 380; forming an electrical connector 381 within the contact hole; a metal layer 390 is formed on the interlayer dielectric layer 380, and the electrical connector 381 connects the metal layer 390 and the control gate 341. Note that, the contact hole is formed on a surface of the portion of the control gate 341 that is not covered by the first sidewall 351 in the first gate structure (i.e., a surface of the portion of the control gate 341 that is exposed in step S05).
In this embodiment, the method for manufacturing a semiconductor device is used to manufacture a Nor flash memory device, and in other embodiments of the present invention, the method for manufacturing a semiconductor device may be used to manufacture other semiconductor devices with the same or similar structures, which is not limited in the present invention.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate; forming a first opening exposing the substrate on the floating gate layer and the control gate layer; forming a first word line structure and a second word line structure on two sides of the first opening respectively; forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer; and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask, so that the first word line structure and the second word line structure form a first gate structure and a second gate structure respectively. According to the invention, the first openings are formed on the control gate layer and the floating gate layer, so that the first photoresist layer covers the first word line structure, the second word line structure and the first openings, and the pattern area of the first photoresist layer is increased, so that the process window of the first photoresist layer is increased, the occurrence of photoresist bleaching of the first photoresist layer is reduced or avoided, and the product yield is improved.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
Providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate;
forming a first opening exposing the substrate on the floating gate layer and the control gate layer;
forming a first word line structure and a second word line structure on two sides of the first opening respectively;
Forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer;
And etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask, so that the first word line structure and the second word line structure form a first gate structure and a second gate structure respectively.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the process of forming the first opening includes:
Forming a patterned second photoresist layer on the control gate layer;
And etching the floating gate layer and the control gate layer by taking the patterned second photoresist layer as a mask layer to form the first opening.
3. The method of manufacturing a semiconductor device according to claim 1, wherein forming the first word line structure and the second word line structure comprises:
Forming a hard mask layer on the control gate layer to fill the first opening;
Forming a second opening and a third opening exposing part of the control gate layer on the hard mask layer, and forming a first side wall on the side walls of the second opening and the third opening;
Etching the control gate layer by taking the hard mask layer and the first side wall as masks, exposing part of the floating gate layer by the second opening and the third opening, and forming a second side wall covering the control gate layer on the side walls of the second opening and the third opening;
Etching the floating gate layer by taking the hard mask layer, the first side wall and the second side wall as masks, so that part of the substrate is exposed by the second opening and the third opening, and a third side wall is formed on the side walls and the bottoms of the second opening and the third opening;
and forming word lines in the second opening and the third opening to form a first word line structure and a second word line structure, wherein the first word line structure comprises a first side wall, a second side wall, a third side wall and word lines in the second opening, and the second word line structure comprises a first side wall, a second side wall, a third side wall and word lines in the third opening.
4. The method for manufacturing a semiconductor device according to claim 3, wherein after forming the first word line structure and the second word line structure, before forming the first photoresist layer, further comprising:
and removing the hard mask layer to expose the first opening and part of the control gate layer.
5. The method of manufacturing a semiconductor device according to claim 3, wherein a set width exists between a sidewall of the first word line structure adjacent to the first opening and a sidewall of the first opening adjacent to the second opening, and the sidewall of the second word line structure adjacent to the first opening is flush with the sidewall of the first opening adjacent to the third opening.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the first photoresist layer covers the first word line structure, the second word line structure, the first opening, and a control gate layer between the first word line structure and the first opening.
7. The method for manufacturing a semiconductor device according to claim 6, further comprising, after forming the first gate structure and the second gate structure:
removing the first photoresist layer;
forming an interlayer dielectric layer on the surfaces of the substrate, the control gate layer, the first word line structure and the second word line structure, and forming a contact hole exposing the control gate layer in the interlayer dielectric layer;
forming an electrical connection in the contact hole;
and forming a metal layer on the interlayer dielectric layer, wherein the electric connecting piece is connected with the metal layer and the control gate layer.
8. The method for manufacturing a semiconductor device according to claim 1, wherein a first dielectric layer is further formed between the substrate and the floating gate layer, and a second dielectric layer is further formed between the floating gate layer and the control gate layer.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the first dielectric layer is a silicon oxide layer, and the second dielectric layer is an ONO stack structure in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are stacked.
10. The method of manufacturing a semiconductor device according to claim 1, wherein the method of manufacturing a semiconductor device is used for manufacturing a Nor flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110877890.4A CN113611745B (en) | 2021-07-30 | 2021-07-30 | Method for manufacturing semiconductor device |
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