CN103021955A - Polycrystalline silicon resistance structure and method for manufacturing corresponding semiconductor integrated device - Google Patents
Polycrystalline silicon resistance structure and method for manufacturing corresponding semiconductor integrated device Download PDFInfo
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- CN103021955A CN103021955A CN2012105644453A CN201210564445A CN103021955A CN 103021955 A CN103021955 A CN 103021955A CN 2012105644453 A CN2012105644453 A CN 2012105644453A CN 201210564445 A CN201210564445 A CN 201210564445A CN 103021955 A CN103021955 A CN 103021955A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 346
- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 165
- 230000015654 memory Effects 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims description 341
- 229910052751 metal Inorganic materials 0.000 claims description 113
- 239000002184 metal Substances 0.000 claims description 113
- 229910021332 silicide Inorganic materials 0.000 claims description 105
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 105
- 239000012774 insulation material Substances 0.000 claims description 66
- 239000000758 substrate Substances 0.000 claims description 60
- 230000015572 biosynthetic process Effects 0.000 claims description 55
- 230000004888 barrier function Effects 0.000 claims description 51
- 238000007667 floating Methods 0.000 claims description 45
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- -1 conductive plunger Inorganic materials 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 6
- 229910052914 metal silicate Inorganic materials 0.000 claims description 5
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical group [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 2
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- 238000005516 engineering process Methods 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
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- 238000002513 implantation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
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Abstract
Disclosed are a polycrystalline silicon resistance structure and a method for manufacturing a corresponding semiconductor integrated device. The method for manufacturing the semiconductor integrated device includes forming control gate material layers on a first region and a second region; synchronously etching the control gate material layers of the first region and the second region; forming a control gate of a split gate type flash memory in the first region; forming second polycrystalline silicon resistors in the second region; and forming first polycrystalline silicon resistors in the second region while forming a word line of the split gate type flash memory. The polycrystalline silicon resistance structure and the method have the advantages that extra processes are omitted, a process period is shortened, and consumed raw materials for depositing polycrystalline silicon and production and process costs are saved.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of polysilicon resistance structure and corresponding formation method for integrated semiconductor device.
Background technology
Characteristic size (CD along with semiconductor device, Critical Dimension) becomes more and more less, the integrated level of semiconductor chip is more and more higher, and the number of devices and the type that need to form in unit are also get more and more, thereby also more and more higher to the requirement of semiconductor technology.The position of the various different components of reasonable arrangement and utilize the common ground of each device manufacturing to save the focus that semiconductor technology step and material become present research how.
In semiconductor device was made, polysilicon was a kind of electric conducting material that is in daily use, and usually can be used for making the floating boom, control gate of gate electrode, high value polysilicon resistance, the flash memory of MOS transistor etc.
Publication number is that the Chinese patent literature of CN101465161A discloses a kind of gate-division type flash memory, specifically please refer to Fig. 1, comprise: Semiconductor substrate 10, be positioned at two storage bit unit 50 that described Semiconductor substrate 10 spaced surfaces are arranged, groove between described two storage bit unit 50, be positioned at the sidewall of described groove and the tunnel oxide 70 of lower surface, be positioned at tunnel oxide 70 surfaces and fill the polysilicon word line 40 of expiring described groove, be positioned at the conductive plunger 20 on described Semiconductor substrate 10 surfaces, described conductive plunger 20 is positioned at the both sides of described storage bit unit 50.Wherein, described storage bit unit 50 comprises the ground floor silicon oxide layer 51 that is positioned at described Semiconductor substrate 10 surfaces, be positioned at first multi-crystal silicon floating bar 52 on described ground floor silicon oxide layer 51 surfaces, be positioned at the second layer silicon oxide layer 53 on described the first multi-crystal silicon floating bar 52 surfaces, be positioned at first polysilicon control grid 54 on described second layer silicon oxide layer 53 surfaces, cover the monox lateral wall 55 of described ground floor silicon oxide layer 51, the first multi-crystal silicon floating bar 52, second layer silicon oxide layer 53, the first polysilicon control grid 54.
At present, described gate-division type flash memory is to separate to make with polysilicon resistance, namely behind the formation gate-division type flash memory, forms mask layer on described gate-division type flash memory surface more first in the appointed area, then forms polysilicon resistance in other zones.But the integrated level of described formation technique is lower, and processing step is more.
Summary of the invention
The problem that the present invention solves provides a kind of polysilicon resistance structure and corresponding formation method for integrated semiconductor device, utilizes to form the polysilicon resistance structure when forming gate-division type flash memory, has greatly saved process costs, has shortened process cycle.
For addressing the above problem, technical solution of the present invention provides a kind of formation method for integrated semiconductor device, comprise: Semiconductor substrate is provided, described Semiconductor substrate has first area and the second area relative with the first area, the semiconductor substrate surface of described first area is formed with the first insulation material layer, described the first insulation material layer surface is formed with the floating boom material layer, described floating boom material surface is formed with the second insulation material layer, the semiconductor substrate surface of described second area is formed with separator, and the second insulation material layer surface of described first area and the insulation surface of second area are formed with the control gate material layer; Form the mask layer with opening in described control gate material surface, wherein, the opening that is positioned at the first area is the first opening, and the opening that is positioned at second area is the second opening; Sidewall at described the first opening forms the first side wall, forms the second side wall at the sidewall of described the second opening; The control gate material layer that control gate material layer, the second insulation material layer, floating boom material layer, the first insulation material layer and the second opening that described the first opening is come out comes out carries out etching, until expose the Semiconductor substrate of first area and the separator of second area; Form the first oxide layer in described the first opening, the second open bottom and sidewall surfaces, and in described the first opening, the second opening, fill full polysilicon, wherein the polysilicon in the first opening forms the word line, and the polysilicon in the second opening forms the first polysilicon resistance; The part control gate material layer of removing described mask layer and being covered by mask layer, be positioned at the control gate material layer formation control grid of the first side wall below, the control gate material layer that is positioned at the second side wall below forms the second polysilicon resistance, and exposes two end surfaces of described control gate, polysilicon resistance; Described the second insulation material layer, floating boom material layer, the first insulation material layer that is covered by mask layer of etching until expose the Semiconductor substrate of first area, forms gate-division type flash memory in the first area; Two end surfaces that expose at described the first polysilicon resistance and the second polysilicon resistance form metal silicide and conductive plunger, form metal interconnecting layer on described conductive plunger surface, and by metal silicide, conductive plunger and metal interconnecting layer the first polysilicon resistance is connected with the second polysilicon resistance and forms the polysilicon resistance structure.
Optionally, also comprise: after forming gate-division type flash memory, form the 3rd insulating barrier on described the first polysilicon resistance surface, described the 3rd insulating layer exposing goes out two end surfaces of the first polysilicon resistance, form metal silicide at described the first polysilicon resistance two end surfaces that expose and word line surface, form conductive plunger on described metal silicide surface.
Optionally, also comprise: after forming gate-division type flash memory, form the 4th insulating barrier in described Semiconductor substrate, form the second polysilicon material layer at described the 4th surface of insulating layer, the second polysilicon material layer, the 4th insulating barrier to described first area and part second area carry out etching, expose the two ends of described the first polysilicon resistance and the two ends of the second polysilicon resistance, form metal silicide at described the first polysilicon resistance two end surfaces that expose and the second polysilicon resistance two end surfaces, form conductive plunger on described metal silicide surface.
Optionally, described Semiconductor substrate also comprises the 3rd zone, described the 3rd zone is used to form MOS transistor, and gate dielectric layer, polygate electrodes in the grid structure of described the 4th insulating barrier, the second polysilicon material layer and the 3rd regional MOS transistor form simultaneously.
Optionally, when described the first polysilicon resistance surface that exposes forms metal silicide and conductive plunger, form metal silicide and conductive plunger on the word line surface of described gate-division type flash memory.
Optionally, the length of described the second polysilicon resistance is greater than the length of the second side wall, described the second side wall only covers the surface, centre position of the second polysilicon resistance, the length of described control gate is greater than the length of the first side wall, the surface, centre position of described the first side wall Coverage Control grid, form metal silicide at two end surfaces of described control gate and two end surfaces of described the second polysilicon resistance, form conductive plunger on described metal silicide surface.
Optionally, when the surface at described the second polysilicon resistance two ends that expose forms metal silicide and conductive plunger, form metal silicide and conductive plunger on the control gate surface of the described gate-division type flash memory that exposes.
Optionally, the formation technique of described metal silicide is that self-aligned metal silicate forms technique.
Optionally, the material of described control gate material layer is polysilicon, and is doped with N-type foreign ion or p type impurity ion in the described control gate material layer.
Optionally, be doped with N-type foreign ion or p type impurity ion in described the first polysilicon resistance.
Optionally, by controlling the width of the second opening and the second side wall, control the resistance of the first polysilicon resistance and the second polysilicon resistance.、
The embodiment of the invention also provides a kind of polysilicon resistance structure, comprise: Semiconductor substrate, be positioned at the separator of described semiconductor substrate surface, be positioned at even number second polysilicon resistance of described insulation surface, be positioned at the side wall on surface, described the second polysilicon resistance centre position, the first polysilicon resistance in the opening between per two adjacent side walls, be positioned at not the second polysilicon resistance two end surfaces of being covered by side wall and the metal silicide of the first polysilicon resistance two end surfaces, be positioned at the conductive plunger on described metal silicide surface, described the first polysilicon resistance is connected by the metal interconnecting layer that is connected with described conductive plunger with the second polysilicon resistance.
Optionally, the first adjacent polysilicon resistance is connected by conductive plunger, metal interconnecting layer series connection, the second adjacent polysilicon resistance is connected by conductive plunger, metal interconnecting layer series connection, and described one of them first polysilicon resistance is connected by metal silicide, conductive plunger, metal interconnecting layer series connection with one of them second polysilicon resistance.
Optionally, the first adjacent polysilicon resistance, the second polysilicon resistance are connected by metal silicide, conductive plunger, metal interconnecting layer series connection.
Optionally, be connected by metal silicide, conductive plunger, metal interconnecting layer series connection with other first polysilicon resistances, the second polysilicon resistance or both Parallel connection structures after the first adjacent polysilicon resistance, the second polysilicon resistance parallel connection.
Compared with prior art, the present invention has the following advantages:
The embodiment of the invention is the formation control gate material layer on first area and second area, and the control gate material layer to described first area and second area carries out etching synchronously, form the control gate of gate-division type flash memory in the first area, form the second polysilicon resistance at second area, and in the word line that forms gate-division type flash memory, form the first polysilicon resistance at second area, do not need to increase any extra technique, shortened process cycle, and the consumption of raw materials of having saved deposit spathic silicon, saved the production technology cost.
Further, the length of the second polysilicon resistance of the embodiment of the invention is greater than the length of the second side wall, described the second side wall only covers the surface, centre position of the second polysilicon resistance, utilization is formed on second side wall on the second polysilicon resistance surface as silicide barrier layer, and described the second side wall forms simultaneously with the first side wall that forms gate-division type flash memory, do not need additionally to form again the self-aligned silicide barrier layer, saved the production technology cost, shortened process cycle.
Further, the embodiment of the invention forms the 4th insulating barrier on described the first polysilicon resistance surface, form the second polysilicon material layer at described the 4th surface of insulating layer, described the second polysilicon material layer and the 4th insulating barrier are as self aligned silicide barrier layer, and gate dielectric layer, polygate electrodes in the grid structure of described the 4th insulating barrier, the second polysilicon material layer and formation MOS transistor form simultaneously, do not need additionally to form again silicide barrier layer, save the production technology cost, shortened process cycle.
Description of drawings
Fig. 1 is the structural representation of the gate-division type flash memory of prior art;
Fig. 2 is the schematic flow sheet of the formation method for integrated semiconductor device of the embodiment of the invention;
The structural representation of the semiconductor integrated device forming process of Fig. 3 to Figure 19 embodiment of the invention.
Embodiment
When utilizing existing technique to form gate-division type flash memory and polysilicon resistance, described gate-division type flash memory is to separate to make with polysilicon resistance, after namely in the appointed area, forming gate-division type flash memory first, form mask layer on described gate-division type flash memory surface again, then form polysilicon resistance in other zones.But need the deposit multilayer polysilicon layer to be used for formation control grid, floating boom or word line owing to make described gate-division type flash memory, after forming behind the gate-division type flash memory described multilayer polysilicon layer with other zones and etching away, form again another layer polysilicon layer to make polysilicon resistance, caused the waste of material and the increase of processing step.
Therefore, the formation method for integrated semiconductor device that the embodiment of the invention provides a kind of polysilicon resistance structure and polysilicon resistance structure and gate-division type flash memory are formed simultaneously, form the polysilicon resistance structure in the control gate in forming gate-division type flash memory, need not increase extra technique, etching, deposition step have been saved, and the consumption of raw materials of having saved deposit spathic silicon, reduced process costs.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization in the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public implementation.
The embodiment of the invention at first provides a kind of formation method for integrated semiconductor device, and concrete schematic flow sheet please refer to Fig. 2, comprising:
Step S101, Semiconductor substrate is provided, described Semiconductor substrate has first area and the second area relative with the first area, the semiconductor substrate surface of described first area is formed with the first insulation material layer, described the first insulation material layer surface is formed with the floating boom material layer, described floating boom material surface is formed with the second insulation material layer, the semiconductor substrate surface of described second area is formed with separator, and the second insulation material layer surface of described first area and the insulation surface of second area are formed with the control gate material layer;
Step S102 forms the mask layer with opening in described control gate material surface, and wherein, the opening that is positioned at the first area is the first opening, and the opening that is positioned at second area is the second opening;
Step S103 forms the first side wall at the sidewall of described the first opening, forms the second side wall at the sidewall of described the second opening;
Step S104, the control gate material layer that control gate material layer, the second insulation material layer, floating boom material layer, the first insulation material layer and the second opening that described the first opening is come out comes out carries out etching, until expose the Semiconductor substrate of first area and the separator of second area;
Step S105, form the first oxide layer in described the first opening, the second open bottom and sidewall surfaces, and fill full polysilicon in described the first opening, the second opening, wherein the polysilicon in the first opening forms the word line, and the polysilicon in the second opening forms the first polysilicon resistance;
Step S106, the part control gate material layer of removing described mask layer and being covered by mask layer, be positioned at the control gate material layer formation control grid of the first side wall below, the control gate material layer that is positioned at the second side wall below forms the second polysilicon resistance, and exposes two end surfaces of described control gate, polysilicon resistance;
Step S107, described the second insulation material layer, floating boom material layer, the first insulation material layer that is covered by mask layer of etching until expose the Semiconductor substrate of first area, forms gate-division type flash memory in the first area;
Step S108, two end surfaces that expose at described the first polysilicon resistance and the second polysilicon resistance form metal silicide and conductive plunger, form metal interconnecting layer on described conductive plunger surface, and by metal silicide, conductive plunger and metal interconnecting layer the first polysilicon resistance is connected with the second polysilicon resistance and forms the polysilicon resistance structure.
Concrete, please refer to Fig. 3 to Figure 19, the structural representation of the semiconductor integrated device forming process of the embodiment of the invention.
Please refer to Fig. 3, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 has first area I and the second area II relative with first area I.
Described Semiconductor substrate 100 can be wherein a kind of of silicon substrate, germanium substrate, germanium silicon substrate, gallium arsenide substrate, gallium nitride substrate or silicon-on-insulator substrate.Those skilled in the art can select according to semiconductor integrated device to be formed the type of described Semiconductor substrate 100, and therefore the type of described Semiconductor substrate should not limit protection scope of the present invention.
Described Semiconductor substrate 100 has first area I and the second area II relative with first area I.Described first area I is adjacent with second area II or be separated by.Form gate-division type flash memory at described first area I in the subsequent technique, form the polysilicon resistance structure at second area II.In the fabrication of semiconductor device of reality, described Semiconductor substrate 100 has one or more first area I and second area II, in the present embodiment, do exemplary illustrated with a first area I and a second area II adjacent with described first area I, the quantity of described first area and second area and position should too not limit the scope of the invention.
In the present embodiment, owing to often have some MOS transistor in the memory circuitry as the control transistor, described Semiconductor substrate 100 also comprises the 3rd zone (not shown), and described the 3rd zone is used to form MOS transistor.
Please refer to Fig. 4, Semiconductor substrate 100 surfaces at described first area I form the first insulation material layer 111, form floating boom material layer 112 on described the first insulation material layer 111 surfaces, form the second insulation material layer 113 on described floating boom material layer 112 surfaces, Semiconductor substrate 100 surfaces at described second area II form separator 200, in the second insulation material layer 113 surfaces of described first area I and the separator 200 surperficial formation control gate material layer 114 of second area II.
In the present embodiment, described separator 200 be shallow trench isolation from (STI) structure, in other embodiments, the silicon oxide layer that described separator can also form for selective oxidation (LOCOS) technique of utilizing silicon.The polysilicon resistance structure is follow-up to be formed at described separator 200 surfaces, so that other device electric isolation such as described polysilicon resistance structure and gate-division type flash memory, MOS transistor.
In the present embodiment, the material of described the first insulation material layer 111 and the second insulation material layer 113 is silica, and the technique that forms described the first insulation material layer 111 and the second insulation material layer 113 is thermal oxidation technology or chemical vapor deposition method.The material of described floating boom material layer 112 is polysilicon, silicon nitride or metal, and described floating boom material layer 112 is used to form floating boom in subsequent technique.The material of described control gate material layer 114 is polysilicon, the control gate material layer 114 of first area I is used to form control gate in subsequent technique, the control gate material layer 114 of second area II is used to form the second polysilicon resistance in subsequent technique, the resistance that the thickness by controlling described control gate material layer 114 and doping content can be controlled the polysilicon resistance of final formation.In the present embodiment, the material of described floating boom material layer 112 and control gate material layer 114 is polysilicon, form described floating boom material layer 112 and control gate material layer 114 and be chemical vapor deposition method, and the process situ of formation control gate material layer 114 is doped with the foreign ion of N-type or P type.In other embodiments, also can after forming described control gate material layer, utilize ion implantation technology in the control gate material layer, to be doped with the foreign ion of N-type or P type.
In the present embodiment, form the first insulation material layer 111 at the first area of described Semiconductor substrate 100 I and second area II surface first, form floating boom material layer 112 on described the first insulation material layer 111 surfaces, form the second insulation material layer 113 on described floating boom material layer 112 surfaces, form grinding barrier layer (not shown) on described the second insulation material layer 113 surfaces, grinding barrier layer to described second area, the second insulation material layer, the floating boom material layer, the Semiconductor substrate of the first insulation material layer and partial depth is carried out etching and is formed groove, and in described groove, be full of insulating material, silica for example, remove unnecessary insulating material by chemical mechanical milling tech, until stop at the grinding barrier layer surface, insulating material in the described groove forms fleet plough groove isolation structure, then removes described grinding barrier layer.Follow the surface of shallow trench isolation structure formation control gate material layer 114 at the second insulation material layer 113 and the second area II of described first area I.Owing to utilize the apparent height of the fleet plough groove isolation structure of cmp formation usually can be lower than the apparent height that grinds the barrier layer; so that utilize the apparent height of the apparent height of the fleet plough groove isolation structure that described technique forms and the second mask material layer similar; can be so that the height of the control gate material layer of the control gate material layer of first area and second area be similar; so that the height of the mask layer of the mask layer of the first area of follow-up formation and second area is similar; be conducive to follow-up to polysilicon carry out cmp when forming the word line to grinding the control that stops, avoid occuring grinding or on the mask layer surface in addition polysilicon remain.
In other embodiments, also can form first separator, form the first insulation material layer in described Semiconductor substrate first area and insulation surface again, form the floating boom material layer on described the first insulation material layer surface, form the second insulation material layer in described floating boom material surface, and remove the first insulation material layer of described insulation surface by etching technics, the floating boom material layer, the second insulation material layer, only the semiconductor substrate surface in described first area forms the first insulation material layer, the floating boom material layer, the second insulation material layer, and in the second insulation material layer surface of described first area and the insulation surface formation control gate material layer of second area.
In other embodiments, also only the semiconductor substrate surface in described first area forms the first insulation material layer, floating boom material layer, form the second insulation material layer and the control gate material layer that is positioned at the second insulation material layer surface in the floating boom material surface of described first area and the insulation surface of second area, because the material of the second insulation material layer and separator all is insulating material, both effects are identical, and multiform becomes one deck the second insulation material layer can the second polysilicon resistance of final formation not to be impacted between described separator and the control gate material layer.
After forming described control gate material layer 114, described control gate material layer 114 is carried out etching, form the control gate material layer 114 of block rectangle, the control gate material layer 114 of each rectangle is corresponding to one gate-division type flash memory unit or polysilicon resistance construction unit, and the width of wherein said rectangle has defined the length of follow-up formation the second polysilicon resistance and the length of control gate.In the present embodiment, the equal in length of the length of described the second polysilicon resistance and control gate.In other embodiments, the size of the control gate material layer of the control gate material layer of the rectangle of described first area and the rectangle of second area is not identical, so that the length of the length of final the second polysilicon resistance that forms and control gate is unequal.
In other embodiments, can the control gate material layer not carried out etching first yet, behind the follow-up removal mask layer, utilize patterned photoresist layer for mask control gate material layer, the second insulation material layer, floating boom material layer, the first insulation material layer to be carried out etching, define the length of control gate, the second polysilicon resistance and the graphics shape that comes out in control gate, the second polysilicon resistance two ends, so that finally two control gates can be formed in described word line both sides, form two the second polysilicon resistances in described dummy word line both sides.
In other embodiments, also can form first the control gate material layer figure of the class rectangle with fracture, described fracture is corresponding to the first opening of follow-up formation and the position at the second opening two ends, so that after take described the first opening and the second opening as mask control gate material layer figure being carried out etching, the control gate material layer that is positioned at the first opening and the second opening both sides is separated, and the control gate material layer that does not need to utilize photoetching process will be positioned at the first opening and the second opening both sides separates, finally can form two control gates in described word line both sides, form two the second polysilicon resistances in described the first polysilicon resistance both sides.
Please refer to Fig. 5, form the mask layer 120 with opening on described control gate material layer 114 surfaces, wherein, the opening that is positioned at first area I is the first opening 121, and the opening that is positioned at second area II is the second opening 122.
The material of described mask layer 120 is silica, silicon nitride or both laminated construction.In the present embodiment, the material of described mask layer 120 is silicon nitride.The technique that forms described the first opening 121 and the second opening 122 is dry etch process or wet-etching technology.In the present embodiment, the technique that forms described the first opening 121 and the second opening 122 is dry etch process, and described the first opening 121 exposes control gate material layer 114 surfaces of first area I, and described the second opening 122 exposes control gate material layer 114 surfaces of second area II.Described the first opening is used to form gate-division type flash memory in subsequent technique, described the second opening is used to form the first polysilicon resistance and the second polysilicon resistance in subsequent technique.The size of described the first opening and the second opening can equate, also can be unequal.Because the width of the first polysilicon resistance of follow-up formation depends on the width of the second opening and the width of follow-up formation the second side wall, the width of the second polysilicon resistance of follow-up formation depends on the width of the second side wall, the length of the first polysilicon resistance depends on the length of the second opening, the height of the first polysilicon resistance and the height of gate-division type flash memory depend on the thickness of described mask layer, and because the resistance of polysilicon resistance and the length positive correlation of polysilicon resistance, be inversely proportional to the area of section of polysilicon resistance, namely with the high negative correlation of the first polysilicon resistance, with the first polysilicon resistance, the width negative correlation of the second polysilicon resistance, by controlling the thickness of described mask layer, the width of the second opening, the width of length and follow-up formation the second side wall can be controlled the first polysilicon resistance of final formation, the size of the second polysilicon resistance.
Please refer to Fig. 6, be the vertical view of second area II among Fig. 5, and the structure of second area is that Fig. 6 is along the cross-sectional view of AA ' direction among Fig. 5.In the present embodiment, the length S2 of described the second opening 122 is less than the width S 1 of the rectangle control gate material layer 114 of second area, the length of described the first opening is less than the width of the rectangle control gate material layer of first area, so that the length of final the first side wall that forms is less than the length of control gate, the length of final the second side wall that forms is less than the length of the second polysilicon resistance, and described the first opening 121, the position of the second opening 122 is positioned at the centre position of rectangle control gate material layer, the final control gate that forms, the two ends of the second polysilicon resistance are not by the first side wall, the second side wall covers, the control gate that exposes, two end surfaces of the second polysilicon resistance are used to form metal silicide and conductive plunger, so that control gate, the second polysilicon resistance is connected with metal interconnecting layer respectively.
Please in the lump with reference to figure 7 and Fig. 8, Fig. 8 is the plan structure schematic diagram of the second area of Fig. 7, forms the first side wall 131 at the sidewall of described the first opening 121, forms the second side wall 132 at the sidewall of described the second opening 122.
Described the first side wall 131, the second side wall 132 are silicon oxide layer, silicon nitride layer or both laminated construction, and the technique that forms side wall is those skilled in the art's known technology, and therefore not to repeat here.In the present embodiment, described the first side wall 131 and the second side wall 132 adopt same formation technique to form.In other embodiments, described the first side wall and the second side wall also can separately form.The thickness of the thickness of described the first side wall and the second side wall can be not identical yet.Because the thickness of the second side wall corresponding to the width of the first polysilicon resistance, the second polysilicon resistance, therefore namely can be controlled the width of the first polysilicon resistance, the second polysilicon resistance by the thickness of controlling described the second side wall.
Please refer to Fig. 9, the control gate material layer 114 that control gate material layer 114, the second insulation material layer 113, floating boom material layer 112, the first insulation material layer 111 and the second opening 122 that described the first opening 121 is come out comes out carries out etching, until expose the Semiconductor substrate 100 of first area I and the separator 200 of second area II.
In the present embodiment, described etching technics specifically comprises: take described the first side wall 131, the second side wall 132 and mask layer 120 as mask, described control gate material layer 114 is carried out etching, until expose the second insulation material layer 113 of first area and the separator 200 of second area, the first opening 121 after described etching and the sidewall of the second opening 122 form the 3rd side wall 133; Take described the 3rd side wall 133 as mask, to the second insulation material layer 113, floating boom material layer 112, the first insulation material layer 111 continuation etchings of described first area, until expose Semiconductor substrate 100 surfaces of described first area.
In other embodiments, since different gate-division type flash memories corresponding to different floating gate structure, control gate structure, namely corresponding to different etching technics.Therefore described lithographic method to floating boom material layer, control gate material layer can be implemented with the multiple alternate manner that is different from this description, and those skilled in the art can do similar popularization in the situation of intension of the present invention.
In the present embodiment, when the second insulation material layer 113 that comes out at etching the first opening 121, floating boom material layer 112, the first insulation material layer 111, the separator 200 that comes out of etching the second opening 122 simultaneously also is so that the separator 200 of segment thickness is etched.But because the second insulation material layer 113, the first insulation material layer 111 are often very thin, and the etching gas of etching floating boom material layer 112 often has higher etching selection ratio to silica, be not easy to etch away separator 200, so that the thickness of the separator that etches away is very little.
Please refer to Figure 10, please refer to Fig. 9 at described the first opening 121(), the second opening 122(please refer to Fig. 9) bottom and sidewall surfaces form the first oxide layer 140, and at described the first opening 121, the full polysilicon of the second opening 121 interior fillings, wherein the polysilicon in the first opening 121 forms word line 141, the second openings 121 interior polysilicons and forms the first polysilicon resistance 142.
The technique that forms described the first oxide layer 140, word line 141 and the first polysilicon resistance 142 specifically comprises: in described the first opening 121, the second opening 122 sidewalls and lower surface, described mask layer 120 surfaces form the first silica material layer (not shown), form the first polysilicon material layer (not shown) on described the first silica material layer surface, and described the first polysilicon material layer is filled completely described the first opening 121, the second opening 122 fully; The first polysilicon material layer to described mask layer 120 surfaces, the first silica material layer carries out cmp, until first polysilicon material layer on mask layer 120 surfaces of mask layer 120 surfaces of described first area and second area, the first silica material layer is completely removed, expose described mask layer 120, so that described the first opening, fill full polysilicon in the second opening, wherein, the first polysilicon material layer 140 in the first opening 121 forms tunnel oxide, the polysilicon that polysilicon in the first opening 121 forms in word line 141, the second openings 122 forms the first polysilicon resistance 142.
In the present embodiment, described the first polysilicon material layer situ is doped with N-type foreign ion or p type impurity ion, in other embodiments, after forming described word line and the first polysilicon resistance, described word line and the first polysilicon resistance are carried out Implantation, so that be doped with N-type foreign ion or p type impurity ion in the word line of described formation and the first polysilicon resistance.By controlling the concentration of described doping ion, can control the resistance of the first polysilicon resistance.
In the present embodiment, when forming the word line, formed the first polysilicon resistance, do not need additionally to form again another layer polysilicon layer and be used to form the first polysilicon resistance, saved the consumption of raw materials of deposit spathic silicon, and described the first polysilicon resistance is formed self-aligned in described the second opening, follow-up the needs carried out chemical wet etching formation polysilicon resistance to polysilicon layer, saved processing step, improved the technique integrated level.
Please refer to Figure 11, remove described mask layer 120(and please refer to Figure 10) and be please refer to Figure 10 by the control gate material layer 114(that mask layer 120 covers), be positioned at the control gate material layer formation control grid 115 of the first side wall 131 belows, the control gate material layer that is positioned at the second side wall 132 belows forms the second polysilicon resistance 116.
The technique of removing described mask layer 120 is dry etch process or wet-etching technology.In the present embodiment, utilize hot phosphoric acid that described mask layer 120 is carried out wet etching.
After removing described mask layer 120, form patterned photoresist layer in described Semiconductor substrate, described patterned photoresist layer covers the control gate material layer of word line, the first polysilicon resistance, the first side wall and the second side wall and subregion.Take described patterned photoresist layer as mask, originally the control gate material layer that was positioned at mask layer 120 belows is carried out etching, until expose the second insulation material layer 113 of first area and the separator 200 of second area, separated so that be positioned at the control gate material layer of word line 141 both sides, form two control gates 115, separated so that be positioned at the control gate material layer of the first polysilicon resistance 142 both sides, formed two the second polysilicon resistances 116.
In the present embodiment, in the formation control grid, formed the second polysilicon resistance, do not need additionally to form again another layer polysilicon layer and be used to form the second polysilicon resistance, saved the consumption of raw materials of deposit spathic silicon, and described the second polysilicon resistance utilizes the self aligned etching of carrying out of the second side wall, follow-uply do not need that polysilicon layer is carried out chemical wet etching and form the second polysilicon resistance, saved processing step, improved the technique integrated level.
Please refer to Figure 12, be the vertical view of second area among Figure 11, and the structure of second area is that Figure 12 is along the cross-sectional view of AA ' direction, wherein among Figure 11, succinct for accompanying drawing, the first oxide layer 140 among described Figure 12 among not shown Figure 11 and the 3rd side wall 133.The length of the second polysilicon resistance 116 that described etching forms is greater than the length of the second side wall 132, and 132 centre positions that cover the second polysilicon resistance 116 of the second side wall, the two ends of described the second polysilicon resistance 116 are not covered by the second side wall 132, so that follow-up two end surfaces at described the second polysilicon resistance 116 can form metal silicide and conductive plunger.
Please refer to Figure 13, after etching is removed described control gate material layer (please refer to Figure 10), continue etching and originally be please refer to Figure 10 by mask layer 120() the second insulation material layer 113, floating boom material layer 112, the first insulation material layer 111 that cover, until expose the Semiconductor substrate 100 of first area, form gate-division type flash memory 150 in the first area.Described floating boom material layer forms the floating boom of gate-division type flash memory 150.
After forming described gate-division type flash memory 150, also the sidewall surfaces at described gate-division type flash memory 150 sidewalls and polysilicon resistance forms the 4th side wall (not indicating), so that the second polysilicon resistance 116 under the floating boom in the gate-division type flash memory 150, control gate, the second side wall and extraneous electricity isolation, and prevent from follow-up ion doping technique Implantation in floating boom, control gate, the second polysilicon resistance, affecting the electric property of device.
Please refer to Figure 14, form the 4th insulating barrier 151 on described word line 141, the first polysilicon resistance 142 and Semiconductor substrate 100 surfaces, form the second polysilicon material layer 152 on described the 4th insulating barrier 151 surfaces and the 4th side wall surface.
In the present embodiment, gate dielectric layer, the polygate electrodes in the grid structure of the MOS transistor in described the 4th insulating barrier 151, the second polysilicon material layer 152 and the 3rd zone forms simultaneously.Owing to usually have MOS transistor in the described memory circuitry, therefore utilize the gate dielectric layer, the polygate electrodes that form described grid structure to form the 4th insulating barrier 151, the second polysilicon material layer 152, improved the integrated level of technique.In the present embodiment, the silicon oxide layer of described the 4th insulating barrier 151 for utilizing thermal oxidation technology to form, the polysilicon layer of described the second polysilicon material layer 152 for utilizing chemical vapor deposition method to form.
Please in the lump with reference to Figure 15 and Figure 16, Figure 15 is the cross-sectional view of the semiconductor integrated device forming process of the embodiment of the invention, Figure 16 is the vertical view of the polysilicon resistance structure of the second area among Figure 15, and the polysilicon resistance structure among Figure 15 is that Figure 12 is along the cross-sectional view of AA ' direction.The second polysilicon material layer 152 and the 4th insulating barrier 151 to first area I and part second area II carry out etching, form the 3rd opening 153, described the 3rd opening 153 exposes the part surface at the first polysilicon resistance 142 two ends, and described the second polysilicon material layer 152 exposes the part surface at the second polysilicon resistance 116 two ends.Form the 5th side wall 135 at described the 3rd opening 153 sidewalls.Semiconductor substrate 100 surfaces, the first polysilicon resistance 142 surfaces, the second polysilicon resistance 116 surfaces and the second polysilicon material layer 152 surfaces in described word line 141 surfaces that expose, control gate 115 surfaces, source region to be formed form metal silicide 160.
In the present embodiment, described metal silicide 160 is nickle silicide, titanium silicide, tantalum silicide, tungsten silicide, cobalt silicide etc., and the technique that forms described metal silicide 160 is self-aligning metal silicide technology.Because self-aligning metal silicide technology is those skilled in the art's known technology, is not described further at this.
Because the manufacture process that existing technique forms polysilicon resistance is to form first one deck polysilicon material layer; polysilicon material layer is carried out after etching forms polysilicon resistance; form silicide trapping layer (salicide block layer at described polysilicon resistance part surface; SAB); capped polysilicon resistance surface utilize described silicide trapping layer to protect the polysilicon resistance surface, so that can not form the silicide of not expecting.Yet the introducing of silicide trapping layer has increased the complexity of technique, and has increased manufacturing cost.
In the present embodiment, described the 4th insulating barrier 151, the second polysilicon material layer 152 is formed on described the first polysilicon resistance surface as the silicide barrier layer of the first polysilicon resistance, second side wall 132 on the described surface that is formed on described the second polysilicon resistance centre position is as the second polysilicon resistance silicide barrier layer, do not need additionally to form silicide barrier layer (SAB), so that only be formed on described the first polysilicon resistance that exposes during follow-up formation self-aligned metal silicate, the surface at the second polysilicon resistance two ends, thus can be on the metal silicide surface by forming conductive plunger with described the first polysilicon resistance, the second polysilicon resistance is connected to each other.
Because the technique of described formation metal silicide is self-aligning metal silicide technology, all can form metal silicide at the described silicon face that exposes, therefore in the present embodiment, sidewall at described the 3rd opening 153 forms the 5th side wall 135, because the material of described the 5th side wall 135 is silica or silicon nitride, described the 5th side wall 135 surfaces can not form metal silicide, so that the metal silicide electric isolation on the metal silicide on the first polysilicon resistance 142 surfaces that expose and the second polysilicon material layer 152 surfaces.
Because existing gate oxide is very thin, if only utilize described gate oxide as silicide barrier layer, in the process that forms metal silicide, be easy to destroyed, can not effectively play the effect of silicide barrier layer, therefore in the present embodiment, the gate dielectric layer of utilization formation grid structure and polygate electrodes are as silicide barrier layer, thus the smooth formation of assurance self-aligned metal silicate.And because described the first polysilicon resistance 142, the metal silicide on the second polysilicon resistance 116 surfaces and the metal silicide electric isolation on the second polysilicon material layer 152 surfaces, follow-up the needs carried out the etching removal to described remaining the second polysilicon material layer 152, saved etching technics.
In other embodiments, the second polysilicon material layer and the 4th insulating barrier to first area and part second area carry out etching, only keep the second polysilicon material layer near polysilicon resistance structure near zone, and the part surface at described the first polysilicon resistance two ends is formed with the 3rd opening, and the part surface at described the second polysilicon resistance two ends is formed with the 4th opening.
In other embodiments, after described the second polysilicon material layer and the 4th insulating barrier carried out etching, the second polysilicon material layer and the 4th insulating barrier that only keep the surface, centre position of the first polysilicon resistance, second polysilicon material layer on the described surface, centre position that is positioned at the first polysilicon resistance and the 4th insulating barrier are as the silicide barrier layer of the first polysilicon resistance, the second side wall is as the silicide barrier layer of the second polysilicon resistance, thereby the surface that exposes at described the first polysilicon resistance, the second polysilicon resistance two ends is formed self-aligned metal silicide.
In other embodiments, can also form the 3rd insulating barrier on described the first polysilicon resistance surface, the two ends of described the 3rd insulating barrier expose the first polysilicon resistance surface, described the 3rd insulating barrier is as silicide barrier layer, so that follow-up the first polysilicon resistance surface that exposes at the two ends of described the 3rd insulating barrier forms self-aligned metal silicate and conductive plunger.
After forming described metal silicide, the follow-up interlayer dielectric layer (not shown) that covers gate-division type flash memory and polysilicon resistance structure that forms at described semiconductor substrate surface, and surperficial at the metal silicide of described control gate 115, the metal silicide of word line 141, the metal silicide surface of the first polysilicon resistance 142, form conductive plunger in the interlayer dielectric layer on the metal silicide surface of the second polysilicon resistance 116, and the metal interconnecting layer that utilizes the interlayer dielectric layer surface is by the conductive plunger formation polysilicon resistance structure that will described the first polysilicon resistance 142 be connected with the second polysilicon resistance 116.
In the present embodiment, metal silicide, the conductive plunger on the metal silicide on the control gate surface of described gate-division type flash memory, conductive plunger and the second polysilicon resistance surface form simultaneously, and metal silicide, the conductive plunger on metal silicide, conductive plunger and the first polysilicon resistance surface on the word line surface of described gate-division type flash memory form simultaneously.In other embodiments, metal silicide, the conductive plunger on the metal silicide on the control gate of described gate-division type flash memory, word line surface, conductive plunger and the first polysilicon resistance, the second polysilicon resistance surface also can separate and form.
In the present embodiment, please refer to Figure 17, the first adjacent polysilicon resistance 116 is by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection are connected, the second adjacent polysilicon resistance 142 is by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection are connected, and described one of them first polysilicon resistance 142 and one of them the second polysilicon resistance 116 are by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection are connected, be connected so that all interior first polysilicon resistances 142 of polysilicon resistance structure are connected with the second polysilicon resistance 116, thereby form a polysilicon resistance structure that resistance is larger.And by the first polysilicon resistance of control series connection and the number of the second polysilicon resistance, can control very easily the resistance of the polysilicon resistance structure of final generation.
In other embodiments, please refer to Figure 18, the first adjacent polysilicon resistance 142, the second polysilicon resistance 116 can also be connected, thereby form a polysilicon resistance structure that resistance is larger by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection.
In other embodiments, please refer to Figure 19, can also will be connected, thereby form a polysilicon resistance structure that resistance is larger by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection with other first polysilicon resistances 142, the second polysilicon resistance 116 or both Parallel connection structures after the first adjacent polysilicon resistance 142,116 parallel connections of the second polysilicon resistance.
The embodiment of the invention also provides a kind of polysilicon resistance structure, please in the lump with reference to Figure 15 and Figure 17, comprise: Semiconductor substrate 100, be positioned at the separator 200 on described Semiconductor substrate 100 surfaces, be positioned at even number second polysilicon resistance 116 on described separator 200 surfaces, be positioned at second side wall 132 on surface, described the second polysilicon resistance 116 centre position, the first polysilicon resistance 142 in the opening between per two adjacent the second side walls 132, be positioned at not by 116 liang of end surfaces of the second polysilicon resistance of the second side wall 132 coverings and the metal silicide 160 of 116 liang of end surfaces of the first polysilicon resistance, be positioned at the conductive plunger 161 on described metal silicide 160 surfaces, described the first polysilicon resistance 142 is connected by the metal interconnecting layer 162 that is connected with described conductive plunger 161 with the second polysilicon resistance 116 and forms the polysilicon resistance structure.
In the present embodiment, the first adjacent polysilicon resistance 116 is by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection are connected, the second adjacent polysilicon resistance 142 is by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection are connected, and described one of them first polysilicon resistance 142 and one of them the second polysilicon resistance 116 are by metal silicide 160, conductive plunger 161, metal interconnecting layer 162 series connection are connected, be connected so that all interior first polysilicon resistances 142 of polysilicon resistance structure are connected with the second polysilicon resistance 116, thereby form a polysilicon resistance structure that resistance is larger.
In other embodiments, the first adjacent polysilicon resistance, the second polysilicon resistance can also be connected, thereby form a polysilicon resistance structure that resistance is larger by metal silicide, conductive plunger, metal interconnecting layer series connection.
In other embodiments, can also will be connected, thereby form a polysilicon resistance structure that resistance is larger by metal silicide, conductive plunger, metal interconnecting layer series connection with other first polysilicon resistances, the second polysilicon resistance or both Parallel connection structures after the first adjacent polysilicon resistance, the second polysilicon resistance parallel connection.
To sum up, the embodiment of the invention is the formation control gate material layer on first area and second area, and the control gate material layer to described first area and second area carries out etching synchronously, form the control gate of gate-division type flash memory in the first area, form the second polysilicon resistance at second area, and in the word line that forms gate-division type flash memory, form the first polysilicon resistance at second area, do not need to increase any extra technique, shortened process cycle, and the consumption of raw materials of having saved deposit spathic silicon, saved the production technology cost.
Further, the length of the second polysilicon resistance of the embodiment of the invention is greater than the length of the second side wall, described the second side wall only covers the surface, centre position of the second polysilicon resistance, utilization is formed on second side wall on the second polysilicon resistance surface as silicide barrier layer, and described the second side wall forms simultaneously with the first side wall that forms gate-division type flash memory, do not need additionally to form again the self-aligned silicide barrier layer, saved the production technology cost.
Further, the embodiment of the invention forms the 4th insulating barrier on described the first polysilicon resistance surface, form the second polysilicon material layer at described the 4th surface of insulating layer, described the second polysilicon material layer and the 4th insulating barrier are as self aligned silicide barrier layer, and gate dielectric layer, polygate electrodes in the grid structure of described the 4th insulating barrier, the second polysilicon material layer and formation MOS transistor form simultaneously, do not need additionally to form again silicide barrier layer, saved the production technology cost.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (15)
1. a formation method for integrated semiconductor device is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate has first area and the second area relative with the first area, the semiconductor substrate surface of described first area is formed with the first insulation material layer, described the first insulation material layer surface is formed with the floating boom material layer, described floating boom material surface is formed with the second insulation material layer, the semiconductor substrate surface of described second area is formed with separator, and the second insulation material layer surface of described first area and the insulation surface of second area are formed with the control gate material layer;
Form the mask layer with opening in described control gate material surface, wherein, the opening that is positioned at the first area is the first opening, and the opening that is positioned at second area is the second opening;
Sidewall at described the first opening forms the first side wall, forms the second side wall at the sidewall of described the second opening;
The control gate material layer that control gate material layer, the second insulation material layer, floating boom material layer, the first insulation material layer and the second opening that described the first opening is come out comes out carries out etching, until expose the Semiconductor substrate of first area and the separator of second area;
Form the first oxide layer in described the first opening, the second open bottom and sidewall surfaces, and in described the first opening, the second opening, fill full polysilicon, wherein the polysilicon in the first opening forms the word line, and the polysilicon in the second opening forms the first polysilicon resistance;
The part control gate material layer of removing described mask layer and being covered by mask layer, be positioned at the control gate material layer formation control grid of the first side wall below, the control gate material layer that is positioned at the second side wall below forms the second polysilicon resistance, and exposes two end surfaces of described control gate, polysilicon resistance;
Described the second insulation material layer, floating boom material layer, the first insulation material layer that is covered by mask layer of etching until expose the Semiconductor substrate of first area, forms gate-division type flash memory in the first area;
Two end surfaces that expose at described the first polysilicon resistance and the second polysilicon resistance form metal silicide and conductive plunger, form metal interconnecting layer on described conductive plunger surface, and by metal silicide, conductive plunger and metal interconnecting layer the first polysilicon resistance is connected with the second polysilicon resistance and forms the polysilicon resistance structure.
2. formation method for integrated semiconductor device as claimed in claim 1, it is characterized in that, also comprise: after forming gate-division type flash memory, form the 3rd insulating barrier on described the first polysilicon resistance surface, described the 3rd insulating layer exposing goes out two end surfaces of the first polysilicon resistance, form metal silicide at described the first polysilicon resistance two end surfaces that expose and word line surface, form conductive plunger on described metal silicide surface.
3. formation method for integrated semiconductor device as claimed in claim 1, it is characterized in that, also comprise: after forming gate-division type flash memory, form the 4th insulating barrier in described Semiconductor substrate, form the second polysilicon material layer at described the 4th surface of insulating layer, the second polysilicon material layer to described first area and part second area, the 4th insulating barrier carries out etching, expose the two ends of described the first polysilicon resistance and the two ends of the second polysilicon resistance, form metal silicide at described the first polysilicon resistance two end surfaces that expose and the second polysilicon resistance two end surfaces, form conductive plunger on described metal silicide surface.
4. formation method for integrated semiconductor device as claimed in claim 3, it is characterized in that, described Semiconductor substrate also comprises the 3rd zone, described the 3rd zone is used to form MOS transistor, and gate dielectric layer, polygate electrodes in the grid structure of described the 4th insulating barrier, the second polysilicon material layer and the 3rd regional MOS transistor form simultaneously.
5. formation method for integrated semiconductor device as claimed in claim 2 or claim 3, it is characterized in that, when described the first polysilicon resistance surface that exposes forms metal silicide and conductive plunger, form metal silicide and conductive plunger on the word line surface of described gate-division type flash memory.
6. formation method for integrated semiconductor device as claimed in claim 1, it is characterized in that, the length of described the second polysilicon resistance is greater than the length of the second side wall, described the second side wall only covers the surface, centre position of the second polysilicon resistance, the length of described control gate is greater than the length of the first side wall, the surface, centre position of described the first side wall Coverage Control grid, form metal silicide at two end surfaces of described control gate and two end surfaces of described the second polysilicon resistance, form conductive plunger on described metal silicide surface.
7. formation method for integrated semiconductor device as claimed in claim 6, it is characterized in that, when the surface at described the second polysilicon resistance two ends that expose forms metal silicide and conductive plunger, form metal silicide and conductive plunger on the control gate surface of the described gate-division type flash memory that exposes.
8. such as claim 2,3 or 6 described formation method for integrated semiconductor devices, it is characterized in that the formation technique of described metal silicide is that self-aligned metal silicate forms technique.
9. formation method for integrated semiconductor device as claimed in claim 1 is characterized in that, the material of described control gate material layer is polysilicon, and is doped with N-type foreign ion or p type impurity ion in the described control gate material layer.
10. formation method for integrated semiconductor device as claimed in claim 1 is characterized in that, is doped with N-type foreign ion or p type impurity ion in described the first polysilicon resistance.
11. formation method for integrated semiconductor device as claimed in claim 1 is characterized in that, by controlling the width of the second opening and the second side wall, controls the resistance of the first polysilicon resistance and the second polysilicon resistance.
12. polysilicon resistance structure, it is characterized in that, comprise: Semiconductor substrate, be positioned at the separator of described semiconductor substrate surface, be positioned at even number second polysilicon resistance of described insulation surface, be positioned at the side wall on surface, described the second polysilicon resistance centre position, the first polysilicon resistance in the opening between per two adjacent side walls, be positioned at not the second polysilicon resistance two end surfaces of being covered by side wall and the metal silicide of the first polysilicon resistance two end surfaces, be positioned at the conductive plunger on described metal silicide surface, described the first polysilicon resistance is connected by the metal interconnecting layer that is connected with described conductive plunger with the second polysilicon resistance.
13. polysilicon resistance structure as claimed in claim 12, it is characterized in that, the first adjacent polysilicon resistance is connected by metal silicide, conductive plunger, metal interconnecting layer series connection, the second adjacent polysilicon resistance is connected by metal silicide, conductive plunger, metal interconnecting layer series connection, and described one of them first polysilicon resistance is connected by metal silicide, conductive plunger, metal interconnecting layer series connection with one of them second polysilicon resistance.
14. polysilicon resistance structure as claimed in claim 12 is characterized in that, the first adjacent polysilicon resistance, the second polysilicon resistance are connected by metal silicide, conductive plunger, metal interconnecting layer series connection.
15. polysilicon resistance structure as claimed in claim 12, it is characterized in that, be connected by metal silicide, conductive plunger, metal interconnecting layer series connection with other first polysilicon resistances, the second polysilicon resistance or both Parallel connection structures after the first adjacent polysilicon resistance, the second polysilicon resistance parallel connection.
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| CN103426727A (en) * | 2013-08-29 | 2013-12-04 | 上海宏力半导体制造有限公司 | Split-grid resistor structure and manufacturing method thereof |
| CN103839778A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing polyresistor structure and polyresistor structure |
| CN107919346A (en) * | 2016-10-10 | 2018-04-17 | 北大方正集团有限公司 | The production method of polysilicon resistance |
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| CN112820649A (en) * | 2021-02-05 | 2021-05-18 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and preparation method thereof |
| CN112820649B (en) * | 2021-02-05 | 2024-04-09 | 上海华虹宏力半导体制造有限公司 | Split gate flash memory and preparation method thereof |
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