CN113611745A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN113611745A CN113611745A CN202110877890.4A CN202110877890A CN113611745A CN 113611745 A CN113611745 A CN 113611745A CN 202110877890 A CN202110877890 A CN 202110877890A CN 113611745 A CN113611745 A CN 113611745A
- Authority
- CN
- China
- Prior art keywords
- layer
- opening
- word line
- line structure
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 259
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000004061 bleaching Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate; forming a first opening exposing the substrate on the floating gate layer and the control gate layer; forming a first word line structure and a second word line structure on two sides of the first opening respectively; forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer; and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask, so that the first word line structure and the second word line structure respectively form a first gate structure and a second gate structure. According to the invention, the first photoresist layer covers the first word line structure, the second word line structure and the first opening by forming the first opening, so that the pattern area of the first photoresist layer is increased, the process window of the first photoresist layer is enlarged, the photoresist bleaching is reduced or avoided, and the product yield is improved.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device.
Background
The Nor Flash memory (Nor Flash) is used as a nonvolatile Flash memory device, can directly run an application program in the device, and has the characteristic of high transmission efficiency. Fig. 1 is a design layout of a Nor flash memory, and fig. 2 is a schematic cross-sectional structure of the Nor flash memory shown in fig. 1 along an AA' direction. Referring to fig. 2, two sides of each word line (i.e., the first word line 131 and the second word line 132) of the Nor flash memory have a control gate (the control gate needs to be formed by subsequent etching of the control gate material layer 120), two ends of the control gate need to be kept a certain area to connect the contact holes, and the two control gates need to be separated, so that the photoresist layer 140 shown in fig. 1 needs to be formed. Referring to fig. 1, the control gate material layer 120 covered by the photoresist layer 140 is remained in a subsequent etching process to connect the contact holes, and the control gate material layer 120 exposed by the photoresist layer 140 is removed in a subsequent etching process to separate two control gates (not shown).
However, as the state of the art of integrated circuit fabrication continues to advance, the size of the Nor flash memory is reduced, and the area of the single pattern in the photoresist layer 140 is also reduced accordingly, so that the process window of the Nor flash memory is reduced. When the area of a single pattern in the photoresist layer 140 is too small, photoresist bleaching may occur, and adverse effects may be generated on subsequent processes, which affect the morphology and performance of the Nor device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which increases the pattern area of a first photoresist layer, thereby increasing the process window of the first photoresist layer.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate;
forming a first opening exposing the substrate on the floating gate layer and the control gate layer;
forming a first word line structure and a second word line structure on two sides of the first opening respectively;
forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer;
and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask so as to enable the first word line structure and the second word line structure to respectively form a first gate structure and a second gate structure.
Optionally, the process of forming the first opening includes:
forming a patterned second photoresist layer on the control gate layer;
and etching the floating gate layer and the control gate layer by taking the patterned second photoresist layer as a mask layer to form the first opening.
Optionally, the process of forming the first word line structure and the second word line structure includes:
forming a hard mask layer filling the first opening on the control gate layer;
forming a second opening and a third opening which expose part of the control gate layer on the hard mask layer, and forming a first side wall on the side wall of the second opening and the third opening;
etching the control gate layer by using the hard mask layer and the first side wall as masks to enable the second opening and the third opening to expose part of the floating gate layer, and forming a second side wall covering the control gate layer on the side walls of the second opening and the third opening;
etching the floating gate layer by using the hard mask layer, the first side wall and the second side wall as masks to enable the second opening and the third opening to expose part of the substrate, and forming third side walls on the side walls and the bottoms of the second opening and the third opening;
word lines are formed in the second opening and the third opening to form the first word line structure and the second word line structure, the first word line structure comprises a first side wall, a second side wall, a third side wall and word lines in the second opening, and the second word line structure comprises the first side wall, the second side wall, the third side wall and word lines in the third opening.
Optionally, after forming the first word line structure and the second word line structure, before forming the first photoresist layer, the method further includes:
and removing the hard mask layer to expose the first opening and part of the control gate layer.
Optionally, a set width exists between a sidewall of the first word line structure close to the first opening and a sidewall of the first opening close to the second opening, and a sidewall of the second word line structure close to the first opening is flush with a sidewall of the first opening close to the third opening.
Optionally, the first photoresist layer covers the first word line structure, the second word line structure, the first opening, and the control gate layer between the first word line structure and the first opening.
Optionally, after forming the first gate structure and the second gate structure, the method further includes:
removing the first photoresist layer;
forming an interlayer dielectric layer on the surfaces of the substrate, the control gate layer, the first word line structure and the second word line structure, and forming a contact hole exposing the control gate layer in the interlayer dielectric layer;
forming an electrical connection member in the contact hole;
and forming a metal layer on the interlayer dielectric layer, wherein the electric connecting piece is connected with the metal layer and the control gate layer.
Optionally, a first dielectric layer is further formed between the substrate and the floating gate layer, and a second dielectric layer is further formed between the floating gate layer and the control gate layer.
Optionally, the first dielectric layer is a silicon oxide layer, and the second oxide layer is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.
Optionally, the manufacturing method of the semiconductor device is used for manufacturing a Nor flash memory.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate; forming a first opening exposing the substrate on the floating gate layer and the control gate layer; forming a first word line structure and a second word line structure on two sides of the first opening respectively; forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer; and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask so as to enable the first word line structure and the second word line structure to respectively form a first gate structure and a second gate structure. According to the invention, the first openings are formed on the control gate layer and the floating gate layer, so that the first photoresist layer covers the first word line structure, the second word line structure and the first openings, and the pattern area of the first photoresist layer is increased, thereby increasing the process window of the first photoresist layer, reducing or avoiding the first photoresist layer from being subjected to photoresist floating, and improving the product yield.
Drawings
FIG. 1 is a design layout of a Nor flash memory;
FIG. 2 is a cross-sectional view along AA' of the Nor flash memory of FIG. 1;
FIGS. 3-6 are schematic structural diagrams corresponding to partial steps in a method for manufacturing a Nor flash memory;
fig. 7 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 8-16 are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor device according to an embodiment of the invention;
wherein the reference numbers are as follows:
100-a substrate; 110-a layer of floating gate material; 120-a control gate material layer; 131-a first word line; 132-a second word line; 140-a photoresist layer;
200-a substrate; 210-a layer of floating gate material; 211-a floating gate layer; 220-a control gate material layer; 221-a control gate layer; 231 — first word line; 232-second word line; 240-photoresist layer; 250-an interlayer dielectric layer; 251-an electrical connection; 260-a metal layer;
300-a substrate; 301 a first opening; 302-a second opening; 303-a third opening; 310-a first dielectric layer; 320-a floating gate layer; 321-a floating gate; 330-second dielectric layer; 340-control gate layer; 341-control gate; 350-a hard mask layer; 351-a first side wall; 352-second side wall; 353-a third side wall; 360-word line; 370-a first photoresist layer; 380-interlayer dielectric layer; 381-electrical connection; 390-metal layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 3-6 are schematic structural diagrams corresponding to partial steps in a manufacturing method of a Nor flash memory.
Referring to fig. 3, the Nor flash memory includes a substrate 200, a floating gate material layer 210 and a control gate material layer 220 are sequentially formed on the substrate 200, a trench (not shown) exposing a portion of the substrate 200 is formed on the floating gate material layer 210 and the control gate material layer 220, and a first word line 231 and a second word line 232 are formed in the trench. Optionally, a first dielectric layer 210 is further formed between the substrate 200 and the floating gate layer 220, and a second dielectric layer 230 is further formed between the floating gate layer 220 and the control gate layer 240. Optionally, the first dielectric layer 210 is a silicon oxide layer, and the second oxide layer 230 is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.
Referring to fig. 4 and 5, a patterned photoresist layer 240 is formed on the first word line 231 and the second word line 232 and extends to cover a portion of the control gate material layer 220 of the first word line 231 on a side close to the second word line 232; and etching the control gate material layer 220 and the floating gate material layer 210 by using the patterned photoresist layer 240 as a mask to form a control gate layer 221 and a floating gate layer 211. At this time, a portion of the control gate layer 221 of the first word line 231 on a side close to the second word line 232 is protected by the photoresist layer 240 and is exposed to the air after the photoresist layer 240 is removed. It should be noted that fig. 4 and 5 are only a cross section of the semiconductor device (similar to the cross section along the AA' direction in fig. 1), and therefore, the photoresist layer 240 formed on the surface of the second word line 232 is not shown in fig. 4 and 5. In addition, before the patterned photoresist layer 240 is formed, a silicon oxide layer (not shown) is formed on the surfaces of the first word line 231 and the second word line 232 through a thermal oxidation growth process, and thus, the silicon oxide layer may serve as a barrier layer to protect portions of the first word line 231 and the second word line 232 that are not covered by the patterned photoresist layer 240 during the formation of the control gate layer 221 and the floating gate layer 211.
Referring to fig. 6, an interlayer dielectric layer 250 and a metal layer 260 are sequentially formed on the substrate 200, the first word line 231, the second word line 232 and the exposed control gate layer 221, a contact hole (not shown) is formed in the interlayer dielectric layer 250 above the exposed control gate layer 221, and an electrical connection member 251 is formed in the contact hole to connect the control gate layer 221 and the metal layer 260.
However, as the state of the art of integrated circuit fabrication continues to advance, the size of Nor flash memory continues to shrink, and the pattern area of the photoresist layer 240 also continues to shrink. When the pattern area of the photoresist layer 240 is too small, the process window of the photoresist layer 240 is too small, and photoresist bleaching may occur and may have adverse effects on subsequent processes, thereby affecting the morphology and performance of the Nor device.
The invention provides a manufacturing method of a semiconductor device, aiming at solving the problem of process window shrinkage caused by the over-small area of a photoresist layer pattern. Fig. 7 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention. Referring to fig. 7, the method for manufacturing a semiconductor device according to the present embodiment includes:
step S01: providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate;
step S02: forming a first opening exposing the substrate on the floating gate layer and the control gate layer;
step S03: forming a first word line structure and a second word line structure on two sides of the first opening respectively;
step S04: forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer;
step S05: and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask so as to enable the first word line structure and the second word line structure to respectively form a first gate structure and a second gate structure.
Fig. 8 to 16 are schematic structural diagrams corresponding to respective steps in a manufacturing method of a semiconductor device according to an embodiment of the present invention, and the manufacturing method of the semiconductor device according to the embodiment is described in detail below with reference to fig. 8 to 16.
First, referring to fig. 8, step S01 is performed to provide a substrate 300, and a floating gate layer 320 and a control gate layer 340 are sequentially formed on the substrate 300. In this embodiment, a first dielectric layer 310 is further formed between the substrate 300 and the floating gate layer 320, and a second dielectric layer 330 is further formed between the floating gate layer 320 and the control gate layer 340. Optionally, the first dielectric layer 310 is a silicon oxide layer, and the second oxide layer 330 is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.
Next, referring to fig. 9, step S02 is performed to form a first opening 301 exposing the substrate 320 on the floating gate layer 320 and the control gate layer 340. In this embodiment, the process of forming the first opening 301 includes: forming a patterned second photoresist layer (not shown) on the control gate layer 340; and etching the floating gate layer 320 and the control gate layer 340 by using the patterned second photoresist layer as a mask layer to form the first opening 301.
Subsequently, referring to fig. 10 to fig. 13, step S03 is performed to form a first word line structure and a second word line structure on two sides of the first opening 301, respectively. Specifically, the process of forming the first word line structure and the second word line structure includes: referring to fig. 10, a hard mask layer 350 is formed on the control gate layer 340 to fill the first opening 301; referring to fig. 11, a second opening 302 and a third opening 303 exposing a portion of the control gate layer 340 are formed on the hard mask layer 350, and a first sidewall 351 is formed on sidewalls of the second opening 302 and the third opening 303; referring to fig. 12, the control gate layer 340 is etched using the hard mask layer 350 and the first sidewalls 351 as masks, so that the second opening 302 and the third opening 303 expose a portion of the floating gate layer 320, and second sidewalls 352 covering the control gate layer 340 are formed on the sidewalls of the second opening 302 and the third opening 303; etching the floating gate layer 320 by using the hard mask layer 350, the first sidewall 351 and the second sidewall 352 as masks, so that the second opening 302 and the third opening 303 expose part of the substrate 300, and forming a third sidewall 353 on the sidewalls and the bottom of the second opening 302 and the third opening 303; next, referring to fig. 13, word lines 360 are formed in the second opening 302 and the third opening 303 to form the first word line structure and the second word line structure, the first word line structure includes the first sidewall 351, the second sidewall 352, the third sidewall 353 and the word lines 360 in the second opening 302, and the second word line structure includes the first sidewall 351, the second sidewall 352, the third sidewall 353 and the word lines 360 in the third opening 303.
It should be noted that a set width exists between the sidewall of the first wordline structure near the first opening 301 and the sidewall of the first opening 301 near the second opening 302, and the sidewall of the second wordline structure near the first opening 301 is flush with the sidewall of the first opening 301 near the third opening 303. Optionally, after the step S03 is executed and before the step S04 is executed, the method further includes: the hard mask layer 350 is removed to expose the first opening 301 and a portion of the control gate layer 340.
Next, referring to fig. 14, step S04 is performed to form a first photoresist layer 370 in the first opening 301 and extend to cover the first word line structure and the second word line structure, so as to enlarge a process window of the first photoresist layer 370. Since the control gate layer 340 with a predetermined width is exposed between the first word line structure and the first opening 301 formed in step S03, the first photoresist layer 370 covers the control gate layer 340 exposed between the first word line structure and the first opening 301 while covering the first word line structure, the second word line structure and the first opening 301.
Subsequently, referring to fig. 15, step S05 is performed to etch the floating gate layer 320 and the control gate layer 340 using the first photoresist layer 370 as a mask, so that the first word line structure and the second word line structure form a first gate structure and a second gate structure, respectively. The first gate structure comprises the first word line structure and a control gate 341 and a floating gate 321 below the first word line structure, and a part of the surface of the control gate 341 on one side of the first gate structure close to the first opening 301 is exposed; the second gate structure includes the second word line structure and a control gate 341 and a floating gate 321 under the second word line structure.
In addition, referring to fig. 16, after the first gate structure and the second gate structure are formed, the method further includes: removing the first photoresist layer 370; forming an interlayer dielectric layer 380 on the surfaces of the substrate 300, the first word line structure and the second word line structure, and forming a contact hole (not shown) in the interlayer dielectric layer 380 to expose the control gate 341; forming electrical connection member 381 within the contact hole; a metal layer 390 is formed on the interlayer dielectric layer 380, and the electrical connector 381 connects the metal layer 390 and the control gate layer 341. Note that the contact hole is formed on the surface of the portion of the control gate 341 in the first gate structure that is not covered by the first sidewall 351 (i.e., the surface of the portion of the control gate 341 exposed in step S05).
In this embodiment, the manufacturing method of the semiconductor device is used for manufacturing a Nor flash memory device, and in other embodiments of the present invention, the manufacturing method of the semiconductor device may be used for manufacturing other semiconductor devices having the same or similar structures, which is not limited by the present invention.
In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate; forming a first opening exposing the substrate on the floating gate layer and the control gate layer; forming a first word line structure and a second word line structure on two sides of the first opening respectively; forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer; and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask so as to enable the first word line structure and the second word line structure to respectively form a first gate structure and a second gate structure. According to the invention, the first openings are formed on the control gate layer and the floating gate layer, so that the first photoresist layer covers the first word line structure, the second word line structure and the first openings, and the pattern area of the first photoresist layer is increased, thereby increasing the process window of the first photoresist layer, reducing or avoiding the first photoresist layer from being subjected to photoresist floating, and improving the product yield.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein a floating gate layer and a control gate layer are sequentially formed on the substrate;
forming a first opening exposing the substrate on the floating gate layer and the control gate layer;
forming a first word line structure and a second word line structure on two sides of the first opening respectively;
forming a first photoresist layer in the first opening, and extending to cover the first word line structure and the second word line structure so as to enlarge a process window of the first photoresist layer;
and etching the control gate layer and the floating gate layer by taking the first photoresist layer as a mask so as to enable the first word line structure and the second word line structure to respectively form a first gate structure and a second gate structure.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the process of forming the first opening includes:
forming a patterned second photoresist layer on the control gate layer;
and etching the floating gate layer and the control gate layer by taking the patterned second photoresist layer as a mask layer to form the first opening.
3. The method of manufacturing the semiconductor device according to claim 1, wherein the process of forming the first word line structure and the second word line structure includes:
forming a hard mask layer filling the first opening on the control gate layer;
forming a second opening and a third opening which expose part of the control gate layer on the hard mask layer, and forming a first side wall on the side wall of the second opening and the third opening;
etching the control gate layer by using the hard mask layer and the first side wall as masks to enable the second opening and the third opening to expose part of the floating gate layer, and forming a second side wall covering the control gate layer on the side walls of the second opening and the third opening;
etching the floating gate layer by using the hard mask layer, the first side wall and the second side wall as masks to enable the second opening and the third opening to expose part of the substrate, and forming third side walls on the side walls and the bottoms of the second opening and the third opening;
word lines are formed in the second opening and the third opening to form the first word line structure and the second word line structure, the first word line structure comprises a first side wall, a second side wall, a third side wall and word lines in the second opening, and the second word line structure comprises the first side wall, the second side wall, the third side wall and word lines in the third opening.
4. The method of manufacturing a semiconductor device according to claim 3, wherein after forming the first word line structure and the second word line structure, and before forming the first photoresist layer, further comprising:
and removing the hard mask layer to expose the first opening and part of the control gate layer.
5. The method for manufacturing a semiconductor device according to claim 3, wherein a set width exists between a sidewall of the first word line structure adjacent to the first opening and a sidewall of the first opening adjacent to the second opening, and a sidewall of the second word line structure adjacent to the first opening is flush with a sidewall of the first opening adjacent to the third opening.
6. The method for manufacturing the semiconductor device according to claim 5, wherein the first photoresist layer covers the first word line structure, the second word line structure, the first opening, and a control gate layer between the first word line structure and the first opening.
7. The method of manufacturing a semiconductor device according to claim 6, further comprising, after forming the first gate structure and the second gate structure:
removing the first photoresist layer;
forming an interlayer dielectric layer on the surfaces of the substrate, the control gate layer, the first word line structure and the second word line structure, and forming a contact hole exposing the control gate layer in the interlayer dielectric layer;
forming an electrical connection member in the contact hole;
and forming a metal layer on the interlayer dielectric layer, wherein the electric connecting piece is connected with the metal layer and the control gate layer.
8. The method for manufacturing a semiconductor device according to claim 1, wherein a first dielectric layer is further formed between the substrate and the floating gate layer, and a second dielectric layer is further formed between the floating gate layer and the control gate layer.
9. The method according to claim 8, wherein the first dielectric layer is a silicon oxide layer, and the second oxide layer is an ONO stack structure in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are stacked.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the method for manufacturing a Nor flash memory is used for manufacturing a Nor flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110877890.4A CN113611745B (en) | 2021-07-30 | 2021-07-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110877890.4A CN113611745B (en) | 2021-07-30 | 2021-07-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113611745A true CN113611745A (en) | 2021-11-05 |
| CN113611745B CN113611745B (en) | 2024-05-14 |
Family
ID=78338960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110877890.4A Active CN113611745B (en) | 2021-07-30 | 2021-07-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113611745B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020034849A1 (en) * | 2000-09-20 | 2002-03-21 | Wang Chih Hsin | Self aligned method of forming a semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling, and a memory array made thereby |
| CN103021955A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Polycrystalline silicon resistance structure and method for manufacturing corresponding semiconductor integrated device |
| CN104465524A (en) * | 2014-12-30 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Mirroring split gate flash memory and formation method thereof |
| CN108538843A (en) * | 2018-04-09 | 2018-09-14 | 上海华虹宏力半导体制造有限公司 | The preparation method of flash cell and semiconductor structure |
| CN109712981A (en) * | 2019-01-02 | 2019-05-03 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| US20200098877A1 (en) * | 2018-09-26 | 2020-03-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Control gate strap layout to improve a word line etch process window |
| CN111785724A (en) * | 2020-08-28 | 2020-10-16 | 上海华力微电子有限公司 | Forming method of flash memory device |
| CN111968982A (en) * | 2020-10-20 | 2020-11-20 | 晶芯成(北京)科技有限公司 | Nor flash memory structure and manufacturing method thereof |
| CN112670290A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | Method for forming memory device |
| CN112750785A (en) * | 2021-01-22 | 2021-05-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split-gate flash memory device |
-
2021
- 2021-07-30 CN CN202110877890.4A patent/CN113611745B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020034849A1 (en) * | 2000-09-20 | 2002-03-21 | Wang Chih Hsin | Self aligned method of forming a semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling, and a memory array made thereby |
| CN103021955A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Polycrystalline silicon resistance structure and method for manufacturing corresponding semiconductor integrated device |
| CN104465524A (en) * | 2014-12-30 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Mirroring split gate flash memory and formation method thereof |
| US20160190335A1 (en) * | 2014-12-30 | 2016-06-30 | Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Split-Gate Flash Memory Having Mirror Structure and Method for Forming the Same |
| CN108538843A (en) * | 2018-04-09 | 2018-09-14 | 上海华虹宏力半导体制造有限公司 | The preparation method of flash cell and semiconductor structure |
| US20200098877A1 (en) * | 2018-09-26 | 2020-03-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Control gate strap layout to improve a word line etch process window |
| CN109712981A (en) * | 2019-01-02 | 2019-05-03 | 上海华虹宏力半导体制造有限公司 | Memory and forming method thereof |
| CN111785724A (en) * | 2020-08-28 | 2020-10-16 | 上海华力微电子有限公司 | Forming method of flash memory device |
| CN111968982A (en) * | 2020-10-20 | 2020-11-20 | 晶芯成(北京)科技有限公司 | Nor flash memory structure and manufacturing method thereof |
| CN112670290A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | Method for forming memory device |
| CN112750785A (en) * | 2021-01-22 | 2021-05-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split-gate flash memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113611745B (en) | 2024-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8110340B2 (en) | Method of forming a pattern of a semiconductor device | |
| JP2008078298A (en) | Semiconductor device and manufacturing method thereof | |
| US8741754B2 (en) | Fabricating method of non-volatile memory | |
| US7579265B2 (en) | Method for manufacturing recess gate in a semiconductor device | |
| US20070010053A1 (en) | Method for fabricating conductive line | |
| KR100318569B1 (en) | Semiconductor device and method for manufacturing the same | |
| CN112071844B (en) | Mask plate of flash memory device and manufacturing method | |
| KR100827509B1 (en) | Method for forming semiconductor device | |
| US7595252B2 (en) | Method of manufacturing a semiconductor memory device | |
| CN113611745B (en) | Method for manufacturing semiconductor device | |
| US7429527B2 (en) | Method of manufacturing self-aligned contact openings | |
| US8304910B2 (en) | Semiconductor device and method of producing the same | |
| US20070072370A1 (en) | Non-volatile memory and fabricating method thereof | |
| KR100529391B1 (en) | Semiconductor memory device and method for fabrication thereof | |
| KR100811257B1 (en) | Method of fabricating the semiconductor device having recessed channel | |
| CN113363142A (en) | Method for forming semiconductor device | |
| KR100228773B1 (en) | Semiconductor device and process for fabricating the same | |
| CN112242398B (en) | Method for manufacturing memory | |
| CN115411044A (en) | Flash memory device and method of manufacturing the same | |
| KR100825814B1 (en) | Semiconductor device having contact barrier and method of manufacturing the same | |
| CN109994382B (en) | Repaired mask structure and resulting underlying patterned structure | |
| US7498221B2 (en) | Method of forming gate of semiconductor device | |
| KR100590378B1 (en) | Method of manufactoring a flash memory device | |
| JPH08130195A (en) | Semiconductor device and manufacture thereof | |
| KR100866964B1 (en) | Method of forming interconnected fine hard-mask pattern for fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |