CN112750785A - Manufacturing method of split-gate flash memory device - Google Patents
Manufacturing method of split-gate flash memory device Download PDFInfo
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- CN112750785A CN112750785A CN202110088507.7A CN202110088507A CN112750785A CN 112750785 A CN112750785 A CN 112750785A CN 202110088507 A CN202110088507 A CN 202110088507A CN 112750785 A CN112750785 A CN 112750785A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
The invention provides a manufacturing method of a split-gate flash memory device, which is characterized in that the top surface of a control gate material layer is flush with the top surface of a word line, then a photoresist layer is formed on the control gate material layer and the word line, and the photoresist layer is subjected to exposure and development processes to form a graphical photoresist layer; sequentially etching the exposed control gate material layer and the exposed floating gate material layer by taking the patterned photoresist layer as a mask so as to form a control gate layer and a floating gate layer; and removing the patterned photoresist layer to expose the top surface of the control gate material layer and the top surface of the word line and form metal silicide, wherein the metal silicide covers the top surfaces of the control gate material layer and the word line, so that the contact resistance of the control gate layer can be reduced due to the existence of the metal silicide.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a split-gate flash memory device.
Background
A Flash memory (Flash) device is a type of nonvolatile semiconductor memory including a stacked gate Flash memory and a split gate Flash memory. Compared with a stacked gate flash memory, the word line in the split gate flash memory avoids the over-erase effect and has higher programming efficiency. Please refer to fig. 1 to 5, which are schematic structural diagrams of a split-gate flash memory device in the prior art; the conventional manufacturing method of the split-gate flash memory device generally includes: firstly, as shown in fig. 1, providing a semiconductor substrate 1, wherein a floating gate material layer 2, an isolation layer 3, a control gate material layer 4 and a mask layer 5 are sequentially formed on the semiconductor substrate 1; an opening 6 is formed in the mask layer 5, a part of the control gate material layer 4 is exposed from the opening 6, then, as shown in fig. 2, a sidewall 7 is formed on a sidewall of the opening 6, and the control gate material layer 4, the isolation layer 3 and the floating gate material layer 2 are sequentially etched by using the sidewall 7 as a mask, so that the opening 6 extends through the control gate material layer 4, the isolation layer 3 and the floating gate material layer 2; next, as shown in fig. 3, the openings 6 are filled with word lines 8; next, as shown in fig. 4, the mask layer 5 is removed to expose a portion of the control gate material layer 4, and, as shown in fig. 5, a patterned photoresist layer is formed to cover the exposed control gate material layer 4, and the exposed control gate material layer 4, the isolation layer 3, and the floating gate material layer 2 are sequentially etched to form a first control gate 4a, a second control gate 4b, a first floating gate 2a, and a second floating gate 2 b.
However, in the above steps, after the mask layer 5 is removed, a height difference is formed between the word line 8 and the control gate material layer 4, and in the subsequent step of forming a patterned photoresist layer, after exposure and development of the photoresist, the photoresist is likely to remain between the word line 8 and the control gate material layer 4 (for example, the photoresist remains on the sidewall of the word line), thereby affecting the subsequent etching of the control gate material layer 4. Moreover, because the surface of the first control gate and the surface of the second control gate are covered by the sidewall, metal silicide cannot be formed on the surfaces of the first control gate and the second control gate, which may result in higher contact resistance of the first control gate 4a and the second control gate 4 b.
Disclosure of Invention
The invention aims to provide a manufacturing method of a split-gate flash memory device, which aims to solve the problems that photoresist residue exists between a control gate material layer and a word line material layer and the contact resistance of a control gate is large in the prior art.
In order to solve the above technical problem, the present invention provides a method for manufacturing a split-gate flash memory device, wherein the method for manufacturing the split-gate flash memory device includes:
providing a semiconductor substrate, wherein a floating gate material layer, a mask layer, a side wall and a word line are sequentially formed on the semiconductor substrate, the word line penetrates through the floating gate material layer, and the side wall is positioned on the word line;
removing the mask layer to expose the floating gate material layer and the side wall of the side wall far away from the word line;
forming a control gate material layer on the floating gate material layer, wherein the top surface of the control gate material layer is flush with the top surface of the word line;
forming a photoresist layer on the control gate material layer and the word lines, and performing exposure and development processes on the photoresist layer to form a patterned photoresist layer, wherein part of the control gate material layer is exposed out of the patterned photoresist layer;
sequentially etching the exposed control gate material layer and the exposed floating gate material layer by taking the patterned photoresist layer as a mask so as to form a control gate layer and a floating gate layer;
removing the patterned photoresist layer to expose the top surface of the control gate layer and the top surfaces of the word lines; and
and forming a metal silicide, wherein the metal silicide covers the top surface of the control gate layer and the top surface of the word line.
Optionally, in the manufacturing method of the split-gate flash memory device, the method for sequentially forming the floating gate material layer, the mask layer, the sidewall spacer and the word line on the semiconductor substrate includes:
forming a floating gate material layer and a mask layer on the semiconductor substrate in sequence, wherein the floating gate material layer covers the semiconductor substrate;
forming a first opening in the mask layer, wherein part of the floating gate material layer is exposed out of the first opening;
forming a side wall material layer by a chemical vapor deposition process, wherein the side wall material layer covers the side wall and the bottom wall of the first opening and extends to cover the top surface of the mask layer;
removing the side wall material layer on the top surface of the mask layer and the bottom wall of the first opening to form the side wall, and defining a second opening by covering the side wall of the opposite side wall of the first opening;
etching the exposed floating gate material layer by taking the side wall as a mask so as to enable the second opening to extend through the floating gate material layer;
forming a word line material layer, wherein the word line material layer fills the second opening and extends to cover the top surface of the mask layer;
and removing the word line material layer on the top surface of the mask layer to form a word line.
Optionally, in the manufacturing method of the split-gate flash memory device, after the exposed floating gate material layer is etched by using the sidewall as a mask and before the word line is formed, the manufacturing method of the split-gate flash memory device further includes: and forming a tunneling oxide layer, wherein the tunneling oxide layer covers the side wall and the bottom wall of the second opening, and the word line is positioned on the tunneling oxide layer.
Optionally, in the manufacturing method of the split-gate flash memory device, a gate oxide layer is further formed between the floating gate material layer and the semiconductor substrate, and the second opening further extends through the gate oxide layer.
Optionally, in the method for manufacturing a split-gate flash memory device, when the patterned photoresist layer is used as a mask and the exposed control gate material layer and floating gate material layer are sequentially etched, the method further includes: and etching the gate oxide layer to expose part of the semiconductor substrate.
Optionally, in the manufacturing method of the split-gate flash memory device, after removing the mask layer, before forming the control gate material layer on the floating gate material layer, the manufacturing method of the flash memory device further includes:
forming an isolation material layer, wherein the isolation material layer covers the top surface of the floating gate material layer, the top surface of the word line and the exposed side wall of the side wall; the isolation material layer comprises a first oxide layer, a nitride layer covering the first oxide layer and a second oxide layer covering the nitride layer.
Optionally, in the manufacturing method of the split-gate flash memory device, a method of forming a control gate material layer on the floating gate material layer includes:
forming a control gate material layer overlying the isolation material layer;
and removing the isolation material layer and the control gate material layer on the top surface of the word line so that the top surface of the control gate material layer is flush with the top surface of the word line.
Optionally, in the method for manufacturing a split-gate flash memory device, when the patterned photoresist layer is used as a mask and the exposed control gate material layer and the exposed floating gate material layer are sequentially etched, the method further includes: and etching the isolation material layer to form an isolation layer, wherein the isolation layer comprises a first isolation layer and a second isolation layer which are respectively positioned at two sides of the word line.
Optionally, in the manufacturing method of the split-gate flash memory device, the control gate layer includes a first control gate and a second control gate respectively located at two sides of the word line, the floating gate layer includes a first floating gate and a second floating gate respectively located at two sides of the word line, and a portion of the semiconductor substrate is exposed by the first floating gate and the second floating gate.
Optionally, in the manufacturing method of the split-gate flash memory device, after the metal silicide is formed, the manufacturing method of the split-gate flash memory device further includes:
forming a dielectric layer, wherein the dielectric layer covers the metal silicide and the exposed semiconductor substrate; and the number of the first and second groups,
and forming a plurality of penetrating contact structures in the dielectric layer, wherein the contact structures are respectively aligned with the first control gate, the second control gate and the word line.
In the manufacturing method of the split-gate flash memory device provided by the invention, firstly, a semiconductor substrate is provided, a floating gate material layer, a mask layer, a side wall and a word line are sequentially formed on the semiconductor substrate, the word line penetrates through the mask layer and the floating gate material layer, and the side wall is positioned between the word line and the mask layer; then, removing the mask layer to expose the top surface of the floating gate material layer and the side wall of the side wall far away from the word line side; forming a control gate material layer on the floating gate material layer, wherein the top surface of the control gate material layer is flush with the top surface of the word line; because the top surface of the control gate material layer is flush with the top surface of the word line, no height difference exists between the top surface of the word line and the top surface of the control gate material layer, and a better process window can be improved for a subsequently formed patterned photoresist layer; then, forming a photoresist layer on the control gate material layer and the word line, and performing exposure and development processes on the photoresist layer to form a patterned photoresist layer, wherein a part of the control gate material layer is exposed out of the patterned photoresist layer; because the top surface of the word line is flush with the top surface of the control gate material layer, photoresist can be prevented from remaining between the word line and the control gate material layer after the photoresist layer is exposed and developed; and then, with the graphical photoresist layer as a mask, sequentially etching the exposed control gate material layer and the floating gate material layer to form a control gate layer and a floating gate layer, namely defining the parts to be removed in the control gate material layer and the floating gate material layer through the graphical photoresist layer. Then, removing the patterned photoresist layer to expose the top surface of the control gate layer and the top surface of the word line; and forming a metal silicide covering the top surface of the control gate layer and the top surface of the word line. The presence of the metal silicide may reduce the contact resistance of the control gate layer. Therefore, the problems that photoresist residues exist between the control gate material layer and the word line material layer and the control gate contact resistance is large in the prior art are solved.
Drawings
Fig. 1 to 5 are schematic structural diagrams of a method for manufacturing a split-gate flash memory device according to the prior art;
FIG. 6 is a flow chart illustrating a method for manufacturing a split-gate flash memory device according to the present invention;
fig. 7 to 20 are schematic structural diagrams formed in the method for manufacturing a split-gate flash memory device according to the present invention.
Wherein the reference numerals are as follows:
1-a semiconductor substrate; 2-a layer of floating gate material; 3-an isolating layer; 4-a control gate material layer; 5-mask layer; 6-opening; 7-side wall; 8-word line; 2 a-a first floating gate; 2 b-a second floating gate; 4 a-a first control gate; 4 b-a second control gate;
10-a semiconductor substrate; 11-a gate oxide layer; 12-a layer of floating gate material; 13-a mask layer; 14-a first opening; 15-side wall material layer; 16-side walls; 17-a second opening; 18-tunneling oxide layer; 19-word line; 20-a layer of isolating material; 21-a first oxide layer; 22-a nitride layer; 23-a second oxide layer; 30-a control gate material layer; 40-a patterned photoresist layer; 120-a first floating gate; 121-a second floating gate; 201-a first isolation layer; 202-a second isolation layer; 301-a first control gate; 302-a second control gate; 303-metal silicide; 304-a dielectric layer; 305-a contact structure; 305 a-a first contact structure; 305 b-a second contact structure; 305 c-third contact structure.
Detailed Description
The following describes the manufacturing method of the split-gate flash memory device in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Please refer to fig. 1, which is a flowchart illustrating a method for manufacturing a split-gate flash memory device according to an embodiment of the present invention. As shown in fig. 1, the present invention provides a method for manufacturing a split gate flash memory device, comprising:
step S1: providing a semiconductor substrate, wherein a floating gate material layer, a mask layer, a side wall and a word line are sequentially formed on the semiconductor substrate, the word line penetrates through the floating gate material layer, and the side wall is positioned on the word line;
step S2: removing the mask layer to expose the floating gate material layer and the side wall of the side wall far away from the word line;
step S3: forming a control gate material layer on the floating gate material layer, wherein the top surface of the control gate material layer is flush with the top surface of the word line;
step S4: forming a photoresist layer on the control gate material layer and the word lines, and performing exposure and development processes on the photoresist layer to form a patterned photoresist layer, wherein part of the control gate material layer is exposed out of the patterned photoresist layer;
step S5: sequentially etching the exposed control gate material layer and the exposed floating gate material layer by taking the patterned photoresist layer as a mask so as to form a control gate layer and a floating gate layer;
step S6: removing the patterned photoresist layer to expose the top surface of the control gate layer and the top surfaces of the word lines; and
step S7: and forming a metal silicide, wherein the metal silicide covers the top surface of the control gate layer and the top surface of the word line.
Next, the above steps will be described in more detail with reference to fig. 7 to 20. Fig. 7 to fig. 20 are schematic structural diagrams formed in the method for manufacturing a split-gate flash memory device according to an embodiment of the present invention.
Firstly, step S1 is executed, as shown in fig. 7, a semiconductor substrate 10 is provided, a floating gate material layer 12, a mask layer 13, a sidewall 16 and a word line 19 are sequentially formed on the semiconductor substrate 10, the word line 19 penetrates through the mask layer 13 and the floating gate material layer 12, and the sidewall 16 is located between the word line 19 and the mask layer 13; the semiconductor substrate 10 may be a silicon substrate.
In addition, a gate oxide layer 11 is further formed between the floating gate material layer 12 and the semiconductor substrate 10, and the gate oxide layer 11 is used for isolation between the semiconductor substrate 10 and the floating gate material layer 12. The floating gate material layer 12 is used to form a floating gate layer.
Specifically, the method for sequentially forming the gate oxide layer 11, the floating gate material layer 12, the mask layer 13, the sidewall spacer 16 and the word line 19 on the semiconductor substrate includes:
step S11, referring to fig. 7 in particular, a gate oxide layer 11, a floating gate material layer 12 and a mask layer 13 are sequentially formed on the semiconductor substrate 10, the gate oxide layer 11 covers the semiconductor substrate 10, and the gate oxide layer 11 may be formed by methods such as low pressure chemical vapor deposition, atomic layer deposition, thermal oxidation or molecular beam epitaxy. The gate oxide layer 11 is made of silicon oxide, such as silicon dioxide, preferably silicon dioxide, so as to enhance the interfacial adhesion between layers. The floating gate material layer 12 may be formed by a chemical vapor deposition method, and is used for forming a floating gate in a subsequent process, and the material thereof may be, for example, polysilicon. The mask layer 13 is made of at least one of silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide and silicon oxynitride.
Step S12: forming a first opening 14 in the mask layer 13, wherein a part of the floating gate material layer 12 is exposed by the first opening 14;
step S13: referring to fig. 9 to 10, a sidewall 16 is formed, and the sidewall 16 covers the sidewall of the first opening 14. Specifically, the method for forming the side wall 16 includes: as shown in fig. 9, a side wall material layer 15 is formed on the bottom wall and the side wall of the first opening 14 and the mask layer 13; then, removing a portion of the sidewall material layer 15 located at the mask layer 13 and the bottom wall of the first opening 14, that is, remaining a portion of the sidewall material layer 15 covering the sidewall of the first opening 17, so as to form the sidewall 16, and defining a second opening 17 by the sidewall 16 covering the opposite sidewall of the first opening 14.
Step S14: as shown in fig. 10, the exposed floating gate material layer 12 and the exposed gate oxide layer 11 are sequentially etched by using the sidewall spacers 16 as masks, so that the second opening 17 extends through the floating gate material layer 12 and the gate oxide layer 11, and the second opening 17 is used for defining the position of the word line 19.
Step S15: referring to fig. 11, a tunnel oxide layer 18 is formed, the tunnel oxide layer 18 covers the sidewall and the bottom wall of the second opening 17, and the tunnel oxide layer 18 is used to isolate a subsequently formed word line 19 from a floating gate layer and a control gate layer.
Step S16: forming a word line material layer which fills the second opening 17 and extends to cover the top surface of the mask layer 13; specifically, the word line material layer is formed by a chemical vapor deposition method.
Step S17: the layer of word line material on the top surface of the mask layer 13 is removed to form word lines 19. In other embodiments of the present invention, a method of etching back by using a dry etching process may also be used to remove the word line material layer on the top surface of the mask layer 13. The word line material layer is made of polycrystalline silicon.
Next, step S2 is executed, as shown in fig. 13, the mask layer 13 is removed, and the floating gate material layer 12 and the sidewalls of the sidewalls 16 far away from the word line 19 are exposed. When the mask layer 13 is removed, a wet etching process may be adopted, and an acidic etching solution, such as phosphoric acid, is preferably adopted in the wet etching process, so that a better etching selection ratio is provided between the etching solution and the mask layer 13, and the etching rate is increased.
Next, as shown in fig. 4, an isolation material layer 20 is formed, where the isolation material layer 20 covers the exposed sidewalls of the sidewall 16, the floating gate material layer 12, and the top surface of the word line 19, that is, the isolation material layer 20 covers the global surface of the semiconductor substrate 10, the isolation material layer 20 is used to form an isolation layer 201 in the subsequent process, and the isolation layer 201 is used to isolate a control gate layer and a floating gate layer which are formed in the subsequent process. The isolation material layer 20 includes a first oxide layer 21, a nitride layer 22 covering the first oxide layer 21, and a second oxide layer 23 covering the nitride layer 21.
More specifically, the isolation material layer 20 may be formed by one or more of a plasma chemical vapor deposition process, an atomic layer deposition process, a low pressure chemical vapor deposition process, or a sub-atmospheric pressure chemical vapor deposition process. In this embodiment, the isolation material layer 20 is preferably formed by a low pressure vapor deposition process and an atomic layer deposition process, so that the thickness uniformity of the isolation material layer 20 is better. For example, the first oxide layer 21 and the second oxide layer 23 may be formed using a Tetraethylorthosilicate (TEOS) low-pressure vapor deposition (LPCVD) process, and the nitride layer 22 may be formed using an atomic layer deposition process.
Next, step S3 is executed, and referring to fig. 15 to 16 in particular, a control gate material layer 30 is formed on the floating gate material layer 10, wherein a top surface of the control gate material layer 30 is flush with a top surface of the word line 19. Specifically, the method for forming the control gate material layer 30 includes:
step S31: as shown in fig. 15, forming a control gate material layer 30, wherein the control gate material layer 30 covers the isolation material layer 20; the control gate material layer 30 may be deposited by a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process, or a sub-atmospheric pressure chemical vapor deposition process.
Step S32, as shown in fig. 16, the isolation material layer 20 and the control gate material layer 30 on the top surface of the word line 19 are removed, so that the top surface of the control gate material layer 30 is flush with the top surface of the word line 19, i.e., the top surface of the word line 19 is exposed. When the control gate material layer 30 and the isolation material layer 20 on the top surface of the word line 19 are removed, a dry etching process can be adopted, preferably fluorine-containing etching gas is adopted, and the etching pressure is 5mT to 10 mT; the flow rate of the etching gas is 100sccm to 200sccm, and the etching time is 60s to 100s, so as to avoid the control gate material layer 30 and the isolation material layer 20 remaining on the top surface of the word line 19. In other embodiments of the present invention, a planarization process may also be used to remove the isolation material layer 20 and the control gate material layer 30 on the top surface of the word line 19.
Next, step S4 is executed: referring to fig. 17, a photoresist layer is formed on the control gate material layer 30 and the word line 19, and the photoresist layer is exposed and developed to form a patterned photoresist layer 40, where the patterned photoresist layer 40 exposes a portion of the control gate material layer 30, that is, a portion of the control gate material layer 30 to be remained is defined by the patterned photoresist layer 40.
Specifically, the method for forming the patterned photoresist layer 40 includes: a photoresist layer is spin-coated on the global surface of the semiconductor substrate 10, including the top surfaces of the word lines 19 and the control gate material layer 30, to form a photoresist layer, and an exposure and development process is performed on the photoresist layer, thereby forming a patterned photoresist layer 40. Compared with the prior art, when the photoresist layer 40 is formed, because the top surface of the word line 19 is flush with the top surface of the control gate material layer 30, namely, no height difference exists between the word line and the control gate material layer, a relatively flat photoresist layer can be formed on the top surfaces of the word line and the control gate material layer, and after the photoresist layer is subjected to exposure and development processes, the photoresist layer can be prevented from remaining between the control gate material layer 30 and the word line 19 after the development process, so that a relatively large process window can be provided for the subsequently formed patterned photoresist layer, and the process window of a contact structure (a subsequently formed contact structure on the control gate) can be increased, thereby improving the yield of products. Specifically, when the photoresist layer is exposed and developed, there is no height difference between the top surface of the word line 19 and the top surface of the control gate material layer 30.
Next, step S5 is executed: referring to fig. 18, the control gate material layer 30, the isolation material layer 20 and the floating gate material layer 10 exposed by etching are sequentially etched using the patterned photoresist layer 40 as a mask to form a control gate layer, an isolation layer and a floating gate layer; the control gate layer includes a first control gate 301 and a second control gate 302 respectively located at two sides of the word line 19, the isolation layer includes a first isolation layer 201 and a second isolation layer 202 respectively located at two sides of the word line, the floating gate layer includes a first floating gate 120 and a second floating gate 121 respectively located at two sides of the word line 19, and a portion of the semiconductor substrate 100 is exposed by the first floating gate 120 and the second floating gate 121. I.e. the portions of the control gate material layer 30 and the floating gate material layer 12 to be removed are defined by the patterned photoresist layer 40. In addition, when the control gate material layer 30, the isolation material layer 20, and the floating gate material layer 12 exposed by etching in sequence are etched using the patterned photoresist layer 140 as a mask, the method further includes: and etching the gate oxide layer 11, namely continuously etching the gate oxide layer 11 after etching the floating gate material layer 12 to expose part of the semiconductor substrate 100. And when the exposed control gate material layer 30, the isolation material layer 20, the floating gate material layer 10 and the gate oxide layer are etched in sequence, a dry etching process is adopted.
Then, step 6 is executed: removing the patterned photoresist layer 40 to expose the top surface of the first control gate 301, the top surface of the second control gate 302 and the top surface of the word line 19; the patterned photoresist layer 40 is preferably removed using an ashing process to avoid residue of the patterned photoresist layer 40.
Then, step S7 is performed, referring to fig. 19, a metal silicide 303 is formed, the metal silicide 303 covering the top surface of the control gate layer and the top surface of the word line 19. Specifically, the metal silicide 303 covers the top surface of the first control gate 301, the top surface of the second control gate 302, and the top surface of the word line 19, and since the top surfaces of the word line and the first control gate are flush with the top surface of the second control gate, compared with the prior art, when a contact structure aligned with the first control gate 301 and the second control gate 302 is formed subsequently, a process window for photolithography and etching of the contact structure can be increased. Further, since the top surfaces of the first control gate 301 and the second control gate 302 are exposed, a metal silicide 303 may be formed on the top surfaces of the first control gate and the second control gate, and compared with the prior art (the control gate in the prior art is usually covered with a process layer, and thus a metal silicide cannot be directly formed on the control gate), the metal silicide 303 may be connected to a contact structure 305 formed subsequently, and the contact resistance of the control gate may be reduced, that is, the contact resistance between the contact structure 305 and the first control gate 301 or the second control gate 302 is reduced, so as to solve the problem of the prior art that the contact resistance of the control gate is large.
Specifically, the method for forming the metal silicide 303 includes: and forming a metal layer which covers the top surface of the first control gate 301, the top surface of the second control gate 302 and the top surface of the word line 19, wherein the metal layer is made of at least one of titanium, zirconium, tantalum, tungsten, manganese, nickel and copper. Then, annealing the semiconductor substrate 10 to react the metal in the metal layer with silicon in the top surfaces of the first control gate 301, the second control gate 302 and the word line 19 to form the metal silicide 303, preferably using a gas containing hydrogen or nitrogen to eliminate a trace amount of oxygen in an annealing environment and prevent the metal in the metal layer from being oxidized; and, performing a cleaning process to remove the unreacted metal layer on the top surfaces of the first control gate 301, the second control gate 302 and the word line 19.
Next, referring to fig. 20, a dielectric layer 304 is formed, wherein the dielectric layer 304 covers the metal silicide 303 and the exposed semiconductor substrate 100; the dielectric layer 304 may be made of silicon oxide, which may isolate a plurality of contact structures 305 to be formed subsequently.
A plurality of contact structures 305 are formed through the dielectric layer 304, and the plurality of contact structures 305 are aligned with the first control gate 301, the second control gate 302 and the word line 19 respectively.
Here, at least three contact structures 305, such as a first contact structure 305a, a second contact structure 305b and a third contact structure 305c, are formed in the dielectric layer 304, the first contact structure 305a being aligned with the first control gate 301 for connection of the first control gate 301 to external circuitry. The second contact structure 305b is aligned to the word line 19 for connection of the word line 301 to external circuitry. The third contact structure 305c is aligned to the second control gate 302 for connection between the second control gate 302 and external circuitry.
Further, due to the presence of the metal silicide 303 on the top surfaces of the first control gate 301 and the second control gate 302, the first control gate 301 and the second control gate 302 can be easily connected out through the contact structure 305, and the metal silicide 303 can reduce the contact resistance between the first control gate 301, the first control gate 301 or the word line 19 and the contact structure 305, thereby increasing the contact voltage.
In summary, in the method for manufacturing the split-gate flash memory device according to the present invention, the top surface of the control gate material layer is flush with the top surface of the word line, and then a photoresist layer is formed on the control gate material layer and the word line, and the photoresist layer is exposed and developed to form a patterned photoresist layer, so that the photoresist layer is prevented from remaining between the word line and the control gate material layer; sequentially etching the exposed control gate material layer and the exposed floating gate material layer by taking the patterned photoresist layer as a mask so as to form a control gate layer and a floating gate layer; and removing the patterned photoresist layer to expose the top surface of the control gate material layer and the top surface of the word line and form metal silicide, wherein the metal silicide covers the top surfaces of the control gate material layer and the word line, so that the contact resistance of the control gate layer can be reduced due to the existence of the metal silicide.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of manufacturing a split gate flash memory device, comprising:
providing a semiconductor substrate, wherein a floating gate material layer, a mask layer, a side wall and a word line are sequentially formed on the semiconductor substrate, the word line penetrates through the floating gate material layer, and the side wall is positioned on the word line;
removing the mask layer to expose the floating gate material layer and the side wall of the side wall far away from the word line;
forming a control gate material layer on the floating gate material layer, wherein the top surface of the control gate material layer is flush with the top surface of the word line;
forming a photoresist layer on the control gate material layer and the word lines, and performing exposure and development processes on the photoresist layer to form a patterned photoresist layer, wherein part of the control gate material layer is exposed out of the patterned photoresist layer;
sequentially etching the exposed control gate material layer and the exposed floating gate material layer by taking the patterned photoresist layer as a mask so as to form a control gate layer and a floating gate layer;
removing the patterned photoresist layer to expose the top surface of the control gate layer and the top surfaces of the word lines; and
and forming a metal silicide, wherein the metal silicide covers the top surface of the control gate layer and the top surface of the word line.
2. The method of manufacturing a split-gate flash memory device according to claim 1, wherein the method of sequentially forming the floating gate material layer, the mask layer, the sidewall spacer, and the word line on the semiconductor substrate comprises:
forming a floating gate material layer and a mask layer on the semiconductor substrate in sequence, wherein the floating gate material layer covers the semiconductor substrate;
forming a first opening in the mask layer, wherein part of the floating gate material layer is exposed out of the first opening;
forming a side wall material layer by a chemical vapor deposition process, wherein the side wall material layer covers the side wall and the bottom wall of the first opening and extends to cover the top surface of the mask layer;
removing the side wall material layer on the top surface of the mask layer and the bottom wall of the first opening to form the side wall, and defining a second opening by covering the side wall of the opposite side wall of the first opening;
etching the exposed floating gate material layer by taking the side wall as a mask so as to enable the second opening to extend through the floating gate material layer;
forming a word line material layer, wherein the word line material layer fills the second opening and extends to cover the top surface of the mask layer;
and removing the word line material layer on the top surface of the mask layer to form a word line.
3. The method of manufacturing a split-gate flash memory device according to claim 2, wherein after etching the exposed floating gate material layer using the spacers as masks and before forming the word lines, the method further comprises: and forming a tunneling oxide layer, wherein the tunneling oxide layer covers the side wall and the bottom wall of the second opening, and the word line is positioned on the tunneling oxide layer.
4. The method of manufacturing a split-gate flash memory device according to claim 2, wherein a gate oxide layer is further formed between the floating gate material layer and the semiconductor substrate, and the second opening further extends through the gate oxide layer.
5. The method of claim 4, wherein when the patterned photoresist layer is used as a mask to sequentially etch the exposed control gate material layer and floating gate material layer, further comprising: and etching the gate oxide layer to expose part of the semiconductor substrate.
6. The method of manufacturing a split-gate flash memory device according to claim 1, wherein after removing the mask layer, before forming a control gate material layer on the floating gate material layer, the method further comprises:
forming an isolation material layer, wherein the isolation material layer covers the top surface of the floating gate material layer, the top surface of the word line and the exposed side wall of the side wall; the isolation material layer comprises a first oxide layer, a nitride layer covering the first oxide layer and a second oxide layer covering the nitride layer.
7. The method of manufacturing a split-gate flash memory device according to claim 6, wherein the method of forming the control gate material layer on the floating gate material layer comprises:
forming a control gate material layer overlying the isolation material layer;
and removing the isolation material layer and the control gate material layer on the top surface of the word line so that the top surface of the control gate material layer is flush with the top surface of the word line.
8. The method of claim 7, wherein when the exposed control gate material layer and the exposed floating gate material layer are sequentially etched using the patterned photoresist layer as a mask, further comprising: and etching the isolation material layer to form an isolation layer, wherein the isolation layer comprises a first isolation layer and a second isolation layer which are respectively positioned at two sides of the word line.
9. The method of manufacturing a split-gate flash memory device according to claim 1, wherein the control gate layer includes a first control gate and a second control gate respectively located at both sides of the word line, the floating gate layer includes a first floating gate and a second floating gate respectively located at both sides of the word line, and the first floating gate and the second floating gate expose a portion of the semiconductor substrate.
10. The method of manufacturing a split-gate flash memory device according to claim 1, wherein after forming the metal silicide, the method of manufacturing a split-gate flash memory device further comprises:
forming a dielectric layer, wherein the dielectric layer covers the metal silicide and the exposed semiconductor substrate; and the number of the first and second groups,
and forming a plurality of penetrating contact structures in the dielectric layer, wherein the contact structures are respectively aligned with the first control gate, the second control gate and the word line.
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