CN102543885A - Split-gate memory device and forming method thereof - Google Patents
Split-gate memory device and forming method thereof Download PDFInfo
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Abstract
The invention provides a forming method of a split-gate memory device. The forming method comprises the steps of: providing a substrate; forming two control gates on the substrate, wherein a region between the two control gates is an erasing gate region, and a region outside the two control gates is a word line region; forming a side wall and a sacrifice side wall which is arranged on the side surface of the side wall; using the sacrifice side wall as a mask to form a floating gate; removing the sacrifice side wall; and forming a tunneling oxide and an erasing gate, wherein the erasing gate and the floating gate have lateral overlapped parts. The invention additionally provides the split-gate memory device. By forming the lateral protruding part of the floating gate and enabling the erasing gate and the floating gate to have the lateral overlapped parts, the overlapped parts can effectively reduce the width of the potential barrier of the tunneling oxide and can improve information erasing speed. By etching a silicon oxide layer and a silicon nitride layer in one step to form a dual-layer side wall and using the dual-layer side wall as a gap layer between word lines and the floating gate, the process of the gap layer is simplified, the uniformity of the gap layer is improved and the writing uniformity is improved.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly a kind of discrete grid memory device and forming method thereof.
Background technology
In present semiconductor industry, IC products mainly can be divided into the three major types type: logic, memory and analog circuit, wherein memory device has accounted for sizable ratio in IC products.And in memory device, the development of flash memory (flash memory) is particularly rapid in recent years.Its main feature is under situation about not powering up, can keep canned data for a long time, have the integrated level height, faster access speed, be easy to wipe and multiple advantages such as rewriting, thereby obtained using widely in multinomial fields such as microcomputer, automation controls.
The standard physical structure of flash memory is called basic position (bit).Usually grid (gate) and the conducting channel interlayer of MOS are separated by gate insulator, are generally oxide layer (gate oxide); And flash memory more than between control gate (control gate) and conducting channel layer of substance, be referred to as floating boom (floating gate).Because the existence of floating boom makes flash memory can accomplish three kinds of basic manipulation modes: promptly to read, write, and wipe.Even if under the situation that does not have power supply to supply with, the existence of floating boom can keep storing the integrality of data.Fig. 1 has provided a memory device with discrete grid structure, has indicated shared erase gate (EG:erasing gate) 006 and two floating boom 002 (FG) in the drawings, in this device, can store two information simultaneously.Said structure comprises: substrate 001, comprise word line district 1 and be adjacent wipe grid region 2, said word line district 1 and wipe the control gate structure that 2 in grid region also is formed with FGS floating gate structure and is positioned at said FGS floating gate structure surface.Said FGS floating gate structure comprises floating gate oxide layers 0021 and is positioned at the floating boom 002 on the floating gate oxide layers 0021 that said control gate structure comprises dielectric layer 0031 and is positioned at the control gate 003 on the dielectric layer 0031.
Wherein, Said word line district 1 is formed with to draw together and is positioned at the word line oxide layer 0041 on the said substrate 001 and is positioned at the word line 004 on the said word line oxide layer 0041, and said FGS floating gate structure comprises the floating boom 002 that is positioned at the floating gate oxide layers on the said substrate and is positioned at said floating gate oxide layers surface;
The said grid region 2 of wiping is formed with tunnel oxide 006 and the erase gate 005 that is positioned on the said substrate 001, and said tunnel oxide 006 is between said erase gate structure and said FGS floating gate structure.
Said memory device also comprises side wall 007, and said side wall 007 is positioned at the both sides of FGS floating gate structure and control gate structure.
In conjunction with Fig. 1, said operation principle is described: because the physical characteristic and the structure of floating boom 002, when it was injected into negatron, " 0 " was just write as by numeral " 1 " in this position, and this process also can be described as programming mode for writing; Relative, after negatron was removed from floating boom 002, this position just became " 1 " by digital " 0 ", and this process is called wipes.Inject or the technology of wiping in the industry cycle has many discussions about electronics.Adopt tunnelling injection method (channel hot injection) mechanism when wherein programming.When source electrode (not shown) ground connection; The voltage of control gate 003 is greater than drain electrode during (not shown) voltage; Floating boom 002 and the potential barrier that is positioned at oxide layer between the conducting channel of substrate of said floating boom below can narrow down; Therefore the electronics in conducting channel can be accelerated from raceway groove and transit to the floating boom 002, and then accomplishes the action of programming (writing).When erasure information, used the Fowler-Nordheim tunneling effect, control gate 003 ground connection is wiped grid region 2 and is added positive voltage, and electronics to erase gate 005, is accomplished wiping electric charge in the floating boom 002 by floating boom 002 tunnelling.Because the Fowler-Nordheim effect is very responsive to the electric field in the tunnel oxide 006, electric field is big more, and tunnelling current is big more, and is fast more to the erasing speed of electric charge, therefore for improving the erasing speed of device, can reduce the potential barrier of passing through of said tunnel oxide.Application number is that 200610118219.7 Chinese patent discloses a kind of formation method of discrete grid memory device, but fails effectively to solve the problem of the potential barrier that reduces tunnel oxide.
Summary of the invention
The object of the present invention is to provide a kind of discrete grid memory device and forming method thereof, can effectively reduce the width of the potential barrier of tunnel oxide, improve information erasing speed.
For addressing the above problem, the present invention provides a kind of formation method of discrete grid memory device, comprising:
Substrate is provided, is formed with floating gate oxide layers, floating gate polysilicon layer, dielectric layer and control gate polysilicon layer on the said substrate successively;
With said floating gate polysilicon layer is etching stop layer, and etching control gate polysilicon layer forms two control gates, and the space of a side is for wiping the grid region in opposite directions for said two control gates, and the space of said two opposing sides of control gate is the word line district;
Formation is positioned at the side wall of each control gate both sides, and said side wall also is positioned at a side in the nearly word line of said floating gate polysilicon layer district;
Form the sacrifice side wall on the surface of said side wall;
With said sacrifice side wall is mask, and the said floating gate polysilicon layer of etching forms floating boom; One end in the nearly word line of said floating boom district flushes with control gate; The other end removes and to be positioned at the control gate below, also be positioned at double-deck side wall and sacrifice the side wall below, said two floating booms in opposite directions the space of a side for wiping the grid region;
Substrate between two floating booms closely wiping the grid region is carried out ion inject, form the source region;
Remove said sacrifice side wall, said floating boom side direction protrudes in said control gate structure, is formed with the side direction protuberance of floating boom;
Form tunnel oxide, said tunnel oxide Coverage Control grid are closely wiped the surface of grid region one side and the surface that floating boom is closely wiped grid region one side, and the thickness of said tunnel oxide is less than the thickness of sacrificing side wall;
Formation be positioned at the word line in word line district and be positioned at word line and substrate between the word line oxide layer, form and to be positioned at the erase gate of wiping the grid region, said erase gate and FGS floating gate structure have the lap of side direction, are formed with side wall between said word line and floating boom.
Optional, the thickness range of said sacrifice side wall is
Optional, the thickness of said tunnel oxide is
Optional, the width range of the lap of said erase gate and FGS floating gate structure side direction is
Optional, the material of said sacrifice side wall is silica or polymer.
Optional, said side wall is the double-deck side wall of silica, silicon nitride.
Optional; The formation method of said double-deck side wall comprises: at first form silicon oxide layer and silicon nitride layer at floating gate polysilicon layer and control gate surface; Then said silicon oxide layer of etching and silicon nitride layer; Form side wall in said control gate both sides, said side wall also is positioned at a side in the nearly word line of said floating gate polysilicon layer district.
Optional, comprise that also with said control gate be mask, inject carrying out ion in the substrate in said word line district, with the adjusting of the threshold voltage that carries out the word line district.
Optional, comprise that also with said control gate be mask, remove the floating gate polysilicon layer that is positioned at the word line district.
Optional, the method for said formation tunnel oxide is a low-pressure chemical vapor phase deposition technology.
Optional, form said tunnel oxide after, also comprise and remove the floating gate oxide layers that is positioned at said word line district.
Optional, remove be positioned at the floating gate oxide layers in said word line district after, also be included on the substrate in said word line district and form the word line oxide layer.
Optional, said word line thickness of oxide layer scope is
Optional, the thickness of said floating gate oxide layers is
Optional, the thickness of said floating gate polysilicon layer is
Optional, the thickness of said control gate polysilicon layer is
The present invention also provides a kind of discrete grid memory device, comprising:
Substrate, be positioned on the said substrate form the word line district and be adjacent wipe the grid region, said word line district and erase gate interval also are formed with FGS floating gate structure and are positioned at the surperficial control gate of said FGS floating gate structure;
Wherein, Said word line district comprises the word line oxide layer that is positioned on the said substrate and is positioned at the word line on the said word line oxide layer; Said FGS floating gate structure comprises the floating boom that is positioned at the floating gate oxide layers on the said substrate and is positioned at said floating gate oxide layers surface; Said floating boom protrudes in said control gate, is formed with floating boom side direction protuberance;
The said grid region of wiping comprises tunnel oxide and the erase gate that is positioned on the said substrate, and said tunnel oxide also is coated with said erase gate side and floating boom protuberance;
Also comprise side wall, said side wall is positioned between tunnel oxide and said control gate, between tunnel oxide and FGS floating gate structure, between word line and control gate and between word line and FGS floating gate structure.
Wherein, said erase gate and floating boom have the lap of side direction.
Optional, the width range of said floating boom side direction protuberance is
Optional, the thickness of said tunnel oxide is
Optional, the width range of the lap of said erase gate and FGS floating gate structure side direction is
Optional, said side wall is the double-deck side wall of silica, silicon nitride.
Optional, said word line thickness of oxide layer scope is
Optional, the thickness range of said floating gate oxide layers is
Optional, the thickness range of said floating boom is
Optional, the thickness range of said control gate is
Compared with prior art, such scheme has the following advantages:
Sacrifice side wall through at first on said side wall, forming; And through with said sacrifice side wall as mask, said floating gate polysilicon layer is carried out etching, form the floating boom of discrete grid memory device; Remove said sacrifice side wall; The floating boom surface that exposes said sacrifice side wall below forms tunnel oxide to form floating boom side direction protuberance at said side wall and floating boom side direction protuberance, and the erase gate that forms and the lap with side direction of floating boom; The lap of said side direction effectively reduces the width of the potential barrier of tunnel oxide, improves information erasing speed;
Further; Said side wall is the double-deck side wall of silica-silicon nitride, and its formation method is difference cvd silicon oxide and the two-layer material of silicon nitride, and only said silica and silicon nitride is carried out etching one time; Form said double-deck side wall; Avoided the dimensional discrepancy that causes in the side wall forming process, effectively improved the uniformity of side wall, thereby improved the uniformity that writes;
Further, the outermost layer of said side wall is a silicon nitride, in the technical process of follow-up removal silica material; Said side wall not be because the protection of silicon nitride can be removed, as remove floating gate oxide layers with the technology that forms the word line oxide layer in, can not be etched solution such as hydrofluoric acid of said side wall is got rid of; For another example when removing the sacrifice side wall; Can not be etched equally solution such as hydrofluoric acid of said side wall is removed, and when being positioned at the tunnel oxide in the word line district like removal, can not be etched equally solution such as hydrofluoric acid of said side wall is removed; Effectively improve the uniformity of side wall, thereby improved the uniformity that writes;
Simultaneously said double-deck side wall is between floating boom and word line, promptly as the clearance layer of floating boom and word line, and only needs etching oxidation silicon and the two-layer material of silicon nitride layer can form clearance layer, effectively improve the uniformity of clearance layer, thereby raising writes uniformity.
Description of drawings
Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purposes, characteristic and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.The drafting of accompanying drawing focuses on illustrating purport of the present invention not painstakingly according to actual ratio.In the accompanying drawings, for cheer and bright, part layer is amplified with the zone.
Fig. 1 is the structural representation of the discrete grid memory device of prior art;
Fig. 2 is the schematic flow sheet of the formation method of the discrete grid memory device of the present invention;
Fig. 3 to Figure 15 is the embodiment cross-sectional view of formation method of the discrete grid memory device of one embodiment of the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed practical implementation.
Method provided by the invention is not only applicable to discrete flash memory in grating device, is applicable to general logical device and memory device yet.Be specially adapted to characteristic size at 130nm and following mos transistor structure.Said MOS transistor can be PMOS transistor or the nmos pass transistor among the CMOS (complementary mos device).
In theory, utilize tunnel thermionic emission mechanism during discrete flash memory in grating device programming (writing), its speed is very fast, and the reaction time is generally in μ s magnitude, and when information erasing, utilizes the F-N tunneling effect, and reaction rate is slower, in the ms magnitude.According to F-N tunneling effect current formula, tunnelling current i
FNWith the field intensity E on the tunnel oxide
TunClosely related, for improving this electric field strength, can reduce the thickness of tunnel oxide, but cause the loss of electric charge on the floating boom easily, thereby cause losing of information; Erasing voltage also can't improve again and again in addition, otherwise can cause the increase of device stability problem and power consumption.
For improving the ability of wiping of discrete flash memory in grating device, reduce the width of the potential barrier of tunnel oxide, promptly reduce the width of the tunneling barrier between floating boom and the erase gate.The present invention provides a kind of formation method of discrete flash memory in grating device, comprising:
Substrate is provided, is formed with floating gate oxide layers, floating gate polysilicon layer, dielectric layer and control gate polysilicon layer on the said substrate successively;
With said floating gate polysilicon layer is etching stop layer, and etching control gate polysilicon layer forms two control gates, and the space of a side is for wiping the grid region in opposite directions for said two control gates, and the space of said two opposing sides of control gate is the word line district;
Formation is positioned at the side wall of each control gate both sides, and said side wall also is positioned at a side in the nearly word line of said floating gate polysilicon layer district;
Form the sacrifice side wall on the surface of said side wall;
With said sacrifice side wall is mask, and the said floating gate polysilicon layer of etching forms floating boom; One end in the nearly word line of said floating boom district flushes with control gate; The other end removes and to be positioned at the control gate below, also be positioned at double-deck side wall and sacrifice the side wall below, said two floating booms in opposite directions the space of a side for wiping the grid region;
Substrate between two floating booms closely wiping the grid region is carried out ion inject, form the source region;
Remove said sacrifice side wall, said floating boom side direction protrudes in said control gate structure, is formed with the side direction protuberance of floating boom;
Form tunnel oxide, said tunnel oxide Coverage Control grid are closely wiped the surface of grid region one side and the surface that floating boom is closely wiped grid region one side, and the thickness of said tunnel oxide is less than the thickness of sacrificing side wall;
Formation be positioned at the word line in word line district and be positioned at word line and substrate between the word line oxide layer, form and to be positioned at the erase gate of wiping the grid region, said erase gate and FGS floating gate structure have the lap of side direction, are formed with side wall between said word line and floating boom.
The present invention sacrifices side wall through at first on said side wall, forming; And through with said sacrifice side wall as mask, said floating gate polysilicon layer is carried out etching, form the floating boom of discrete grid memory device; Remove said sacrifice side wall; The floating boom surface that exposes said sacrifice side wall below forms tunnel oxide to form floating boom side direction protuberance at said side wall and floating boom side direction protuberance, and the erase gate that forms and the lap with side direction of floating boom; The lap of said side direction effectively reduces the width of the potential barrier of tunnel oxide, improves information erasing speed.
Fig. 2 is the formation method flow sketch map of the discrete grid memory device of one embodiment of the invention, comprising:
Execution in step S1 provides Semiconductor substrate, is formed with floating gate oxide layers, floating gate polysilicon layer, dielectric layer and control gate polysilicon layer on the said substrate successively;
Execution in step S2; With said floating gate polysilicon layer is etching stop layer etching control gate polysilicon layer; Form two control gates, said two control gates are wiped the grid region with formation in the space of a side in opposite directions, and the space of said two opposing sides of control gate will form the word line district;
Execution in step S3 carries out ion to the substrate in said word line district and injects, to carry out the threshold voltage adjustments in word line district;
Execution in step S4, for stopping layer, etching is positioned at the floating gate polysilicon layer in word line district with said floating gate oxide layers;
Execution in step S5 forms the double-deck side wall of oxide layer, silicon nitride that is positioned at each control gate both sides, and said oxide layer, the double-deck side wall of silicon nitride also are positioned at a side in the nearly word line of said floating gate polysilicon layer district;
Execution in step S6 forms the sacrifice side wall in the both sides of said double-deck side wall;
Execution in step S7, etching is wiped the floating gate polysilicon layer in grid region, forms floating boom, and an end in the nearly word line of said floating boom district flushes with control gate, and the other end removes and is positioned at the control gate below, also is positioned at double-deck side wall and sacrifices the side wall below;
Execution in step S8 carries out ion to the substrate between two floating booms closely wiping the grid region and injects, and forms the source region;
Execution in step S9 forms tunnel oxide, and said tunnel oxide is positioned at floating boom and closely wipes the surface of grid region one side and the surface that control gate is closely wiped grid region one side;
Execution in step S10, form be positioned at the word line in word line district and be positioned at word line and substrate between the word line oxide layer, form and be positioned at the erase gate of wiping the grid region.
Fig. 3 to Figure 15 is the formation method cross-sectional view of the discrete grid memory device of one embodiment of the invention, and said sketch map is an instance, should excessively not limit the scope of the present invention's protection at this.
As shown in Figure 3, Semiconductor substrate 110 is provided, silicon or SiGe that said Semiconductor substrate 110 can be monocrystalline, polycrystalline or non crystalline structure also can be silicon-on-insulators (SOI).The material that perhaps can also comprise other, for example three or five compounds of group such as GaAs.
Continuation forms floating gate oxide layers 120, floating gate polysilicon layer 130, dielectric layer 140, control gate polysilicon layer 150 and hard mask layer 160 successively with reference to figure 3 on the said substrate 110.Said floating gate oxide layers 120 is a silicon dioxide.The deposition process of said floating gate oxide layers can be conventional vacuum coating technology; For example boiler tube thermal oxidation; Ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, present embodiment adopts the boiler tube thermal oxidation technology.
Continuation is with reference to figure 3, and said floating gate polysilicon layer 130 is as floating boom (floating gate).The deposition process of said floating gate polysilicon layer 130 can be chemical vapor deposition (CVD), low-pressure chemical vapor phase deposition (LPCVD) technology, and present embodiment adopts low-pressure chemical vapor phase deposition technology.The floating gate polysilicon layer 130 has a thickness ranging
preferably
Be positioned at the dielectric layer 140 on the said floating gate polysilicon layer 130, be in particular the ONO three-decker, i.e. silica-silicon-nitride and silicon oxide.As insulating barrier, the advantage of little, the low defective of electric leakage is arranged with it.The deposition process such as the preamble of silica are said, and the deposition process of silicon nitride can be plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD) technology.Present embodiment adopts low-pressure chemical vapor phase deposition.
Continuation is positioned at the control gate polysilicon layer 150 on the said dielectric layer 140 with reference to figure 3, as control gate (control gate).The deposition process such as the preamble of polysilicon are said, and present embodiment adopts low-pressure chemical vapor phase deposition technology.Said control gate polysilicon layer 150 has a thickness ranging
preferably 600
The hard mask layer 160 that is positioned on the said control gate polysilicon layer 150 comprises oxide layer and is positioned at the silicon nitride layer on the said oxide layer that the thickness range of said silicon oxide layer is preferably
said silicon nitride for
thickness range is preferably
for
As shown in Figure 4, the photoresist layer of formation patterning on said hard mask layer 160.Said photoresist layer is corresponding with the control gate pattern of follow-up formation.Through an etching floating gate polysilicon layer each layer film more than 130 has been carved, formation is positioned at two control gates 151 on the said floating gate polysilicon layer 130.Said control gate 151 space of a side in opposite directions will be used to form and wipe the grid region, and said two control gates, 151 opposing sides will form the word line district.
Particularly, said etching adopts dry etching, and said dry etching adopts reactive ion etching, and used process gas is mainly fluoro-gas.
As shown in Figure 5; Form first photoresist layer 170, said photoresist layer 170 covers said dielectric layer 140, control gate 151 and hard mask layer 160 space in opposite directions, and covers the top of said hard mask layer 160; With said first photoresist layer 170 is mask; To being positioned at the substrate 110 of said two control gate 151 opposing sides, the substrate 110 that promptly is positioned at the word line district carries out ion and injects, to the word line district of follow-up formation carrying out threshold voltage adjustments.
As shown in Figure 5, preferably, for avoiding when ion injects, the photoresist layer 170 that is positioned at said hard mask layer 160 tops is stained with on the substrate 110 in word line district, and said photoresist layer 160 is not coated with the part of hard mask layer 160 near the word line district.
As shown in Figure 6, continuing with said photoresist layer 170 is mask, and said floating gate polysilicon layer 130 is carried out etching, removes to be positioned at the floating gate polysilicon layer 130 of word line on trivial.Expose said floating gate oxide layers 120.
The ion etching of above-mentioned word line threshold value adjustment and etching floating gate polysilicon layer 130 are mask with said photoresist layer 170 all, to simplify technology.
As shown in Figure 7; Remove said photoresist layer 170, form side wall 210, said side wall comprises side wall 210a and side wall 210b; Said side wall 210b is positioned at a side surface in opposite directions of dielectric layer 140, control gate 151 and hard mask layer 160; Said side wall 210a is positioned at an opposing side surface of said dielectric layer 140, control gate 151 and hard mask layer 160, and wherein, said side wall 210a also is formed on the surface of nearly word line district one side of said floating gate polysilicon layer 130.
Wherein, said side wall 210 is silica-silicon nitride structure, promptly is exposed to the outer silicon nitride layer that is.Its formation method is deposit one deck silicon oxide layer at first, and then deposit one deck silicon nitride layer at last through an etching, to said silicon oxide layer and silicon nitride layer while etching, forms said side wall 210a and side wall 210b simultaneously.The polycrystalline substance of the final side wall that forms 210 its contact floating gate polysilicon layers is silica, and is positioned at the silicon nitride on the silica.
The present invention only carries out etching one time to said silica and the two-layer material of silicon nitride; Promptly form said double-deck side wall 210; Avoided the dimensional discrepancy that causes in the side wall forming process, effectively improved the uniformity of side wall, to improve the uniformity that writes of said discrete grid memory device.
Wherein, The outermost layer of said side wall 210 is silicon nitrides, and in the technical process of follow-up removal silica material, said side wall 210 is not because the protection of silicon nitride can be removed; As in removing the technology of floating gate oxide layers with formation word line oxide layer; The said side wall 210 solution hf etching that can not be etched falls, and is removing when sacrificing side wall for another example, and the said side wall 210 solution hydrofluoric acid that can not be etched is equally removed; Effectively improve the uniformity of side wall, improved the uniformity that writes of said discrete grid memory device.
Said double-deck side wall 210 is also between floating boom and word line simultaneously; Promptly as the clearance layer between floating boom and the word line; Only etching oxidation silicon of needs and the two-layer material of silicon nitride layer can form clearance layer; Simplified the technical process of making clearance layer, effectively improved the uniformity of clearance layer, write uniformity thereby improve.
As shown in Figure 8, on said side wall 210a surface, form and sacrifice side wall 220a, on said side wall 210b surface, form and sacrifice side wall 220b, constitute and sacrifice side wall 220.The thickness range of said sacrifice side wall 220 is 200～400 dusts.In the present embodiment, said sacrifice side wall 220 is a silica.As other embodiment, said sacrifice side wall 220 all right polymer are like photoresistance.
Among the present invention, said sacrifice side wall 220b is used for the mask of the floating boom of follow-up formation, and after forming said floating boom, said sacrifice side wall 220a need be removed, to expose the floating boom surface that is positioned at said sacrifice side wall 220b below.
As shown in Figure 9, form second photoresist layer 230, said second photoresist layer 230 covers the surface of the floating gate oxide layers 120 of said sacrifice side wall 220a surface and nearly word line district one side, and said second photoresist layer 230 also is coated with hard mask layer 160.When avoiding ion to inject, second photoresist layer 230 that is positioned at said hard mask layer 160 tops is stained with on the said floating gate oxide layers 120, does not form second photoresist layer 230 near the part surface of the hard mask layer 160 of said sacrifice side wall 220b one side.
Continuation is mask with reference to figure 9 with said second photoresist layer 230, and said floating gate polysilicon layer 130 is carried out etching, forms floating boom 131, and said floating boom 131 is positioned at said control gate 151, side wall 210b and sacrifices side wall 220b below.An end that is said floating boom 131 flushes with control gate 151, and the other end not only is positioned at the below of said floating boom 131, also is positioned at said side wall 210b and sacrifices side wall 220b below.Wherein, In subsequent technique, said sacrifice side wall 220b need be removed, to expose the surface of the floating boom 131 that is positioned at said sacrifice side wall 220b below; Form the side direction protuberance of floating boom, and follow-uply will on floating boom side direction protuberance surface, form tunnel oxide.
Continuation is with reference to figure 9; So far, control gate 151, floating boom 131 all form, have good electrical conductivity for making the source region of wiping the grid region that is positioned at follow-up formation; Need carry out ion to this zone injects; Can continue said second photoresist layer 230 particularly and be mask, said substrate 110 carried out ion inject, form the source region.
Above-mentioned formation floating boom is a mask with said photoresist layer 230 all with forming the source region, can reach simplification technology, saves the effect of technology cost.
Shown in figure 10; Adopt wet etching, remove and sacrifice side wall 220b, because the material of said sacrifice side wall 220b is a silica; Said wet etching will be removed simultaneously and be positioned at the floating gate oxide layers 120 that exposes part on substrate 110 surfaces, and the floating gate oxide layers 120 that originally illustrates is all removed.The solution of said wet etching is hydrofluoric acid.
Because the outermost layer of the side wall 210b among the present invention is a silicon nitride; Removing sacrifice side wall 220b is in the technical process of silica; Said side wall 210b has effectively improved the uniformity of side wall because the protection of silicon nitride can not be removed, and improves the uniformity that writes of said discrete grid memory device.
Continuation is with reference to Figure 10; After removing said sacrifice side wall 220b; Said floating boom 131 exposes the former part top surface that is positioned at said sacrifice side wall 220b below; Be that said floating boom 131 protrudes in said control gate 151, expose said floating boom side direction protuberance, the surperficial follow-up of said floating boom protuberance will be formed with tunnel oxide.
Shown in figure 11, at first remove second photoresist layer 230 and sacrifice side wall 220a, form tunnel oxide 240, said tunnel oxide 240 adopts depositional mode to form, and is coated with the word line district simultaneously and wipes substrate 110 surfaces in grid region and the surface of side wall 210.
Said tunnel oxide 240 is had relatively high expectations for film quality.Its generation type can be plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD).Present embodiment is selected low-pressure chemical vapor phase deposition for use; Form oxide layer HTO, thickness be
this for
said tunnel oxide 240 thickness is
in that this is
Further; Because the outermost layer of the side wall among the present invention is a silicon nitride, in removing sacrifice side wall technical process, said side wall is not because the protection of silicon nitride can be removed; Effectively improve the uniformity of side wall, improved the uniformity that writes of said discrete grid memory device.
Shown in figure 12; Using photoresist layer will wipe the grid region covers; Be positioned on the word line district substrate tunnel oxide 240 and be positioned at hard mask layer 160 lip-deep tunnel oxides 240 with removal, and remove the floating gate oxide layers 120 that is positioned at the word line district, expose said substrate 110 surfaces.
Because the outermost layer of the side wall 210a among the present invention is a silicon nitride; In removing floating gate oxide layers 120 technical processs that cover its surperficial tunnel oxide 240 and word line district; Said side wall 210a is not because the protection of silicon nitride can be removed; Effectively improve the uniformity of side wall, improved the uniformity that writes of said discrete grid memory device.
Shown in figure 13; Through after the etching shown in figure 12, remove and cover the photoresist layer of wiping the grid region, form tunnel oxide 241; Said tunnel oxide 241 removes and is positioned at said control gate 151 sides and floating gate oxide layers surface, also is coated with the part side direction protuberance of said floating boom 131.The lateral thickness of said tunnel oxide 241 is less than the transverse width of said floating boom protuberance, so that the erase gate of follow-up formation and floating boom have the lap of side direction.
Then shown in figure 14; On said substrate 110 surfaces, form word line oxide layer 310; Said word line thickness of oxide layer is 1/3rd of floating gate oxide layers 120 thickness, the thickness range of said floating gate oxide layers 120 be
said word line oxide layer 310 thickness range is
Shown in figure 15, be mask with said side wall, comprise that side wall 210a and 210b are mask, formation is positioned at the word line (wordline:WL) 320 of said word line oxide layer 310 in said word line district, and is positioned at the erase gate 410 on the said tunnel oxide 241.Wherein erase gate 410 is polysilicon layer with word line 320, and generation type is a low-pressure chemical vapor phase deposition technology, and the film to deposit carries out patterning through photoetching, etching technics therebetween.Form device architecture shown in figure 14 at last.
Wherein, The lap that erase gate 410 and the FGS floating gate structure that forms has side direction; The width range of said lap effectively reduces the width of the potential barrier of tunnel oxide for
lap of said side direction, improves information erasing speed.
Said double-deck side wall 210a is between floating boom and word line simultaneously; Promptly as the clearance layer of floating boom and word line; And only etching oxidation silicon of needs and the two-layer material of silicon nitride layer can form clearance layer, effectively improve the uniformity of clearance layer, write uniformity thereby improve.
The discrete grid memory device that the present invention also provides a kind of formation method of said discrete grid memory device to form comprises:
Substrate, be positioned on the said substrate form the word line district and be adjacent wipe the grid region, said word line district and erase gate interval also are formed with FGS floating gate structure and are positioned at the surperficial control gate of said FGS floating gate structure;
Wherein, Said word line district comprises the word line oxide layer that is positioned on the said substrate and is positioned at the word line on the said word line oxide layer; Said FGS floating gate structure comprises the floating boom that is positioned at the floating gate oxide layers on the said substrate and is positioned at said floating gate oxide layers surface; Said floating boom protrudes in said control gate, is formed with floating boom side direction protuberance;
The said grid region of wiping comprises tunnel oxide and the erase gate that is positioned on the said substrate, and said tunnel oxide also is coated with said erase gate side and floating boom protuberance;
Also comprise side wall, said side wall is positioned between tunnel oxide and said control gate, and between tunnel oxide and FGS floating gate structure, between word line and control gate and between word line and FGS floating gate structure, wherein, said erase gate and floating boom have the lap of side direction.
Wherein, the width range of said floating boom side direction protuberance be
said tunnel oxide thickness is
Said side wall is the double-deck side wall of silica, silicon nitride, said word line thickness of oxide layer scope be
said floating gate oxide layers thickness range for the thickness range of
said floating boom for
said control gate thickness range is
Said erase gate and FGS floating gate structure have the lap of side direction; The width range of said lap effectively reduces the width of the potential barrier of tunnel oxide for
lap of said side direction, improves information erasing speed.
Compared with prior art, the present invention has the following advantages: sacrifice side wall through at first on said side wall, forming, and pass through said sacrifice side wall as mask; Said floating gate polysilicon layer is carried out etching; Form the floating boom of discrete grid memory device, remove said sacrifice side wall, the floating boom surface that exposes said sacrifice side wall below is to form floating boom side direction protuberance; Formation is coated with the tunnel oxide of said side wall and floating boom side direction protuberance; And the erase gate that forms and the lap with side direction of floating boom, the lap of said side direction effectively reduces the width of the potential barrier of tunnel oxide, improves information erasing speed;
Further; Said side wall is the double-deck side wall of silica-silicon nitride, and its formation method is difference cvd silicon oxide and the two-layer material of silicon nitride, and only said silica and silicon nitride is carried out etching one time; Form said double-deck side wall; Avoided the dimensional discrepancy that causes in the side wall forming process, effectively improved the uniformity of side wall, thereby improved the uniformity that writes;
Further, the outermost layer of said side wall is a silicon nitride, in the technical process of follow-up removal silica material; Said side wall not be because the protection of silicon nitride can be removed, as remove floating gate oxide layers with the technology that forms the word line oxide layer in, can not be etched solution such as hydrofluoric acid of said side wall is got rid of; For another example when removing the sacrifice side wall; Can not be etched equally solution such as hydrofluoric acid of said side wall is removed, and when being positioned at the tunnel oxide in the word line district like removal, can not be etched equally solution such as hydrofluoric acid of said side wall is removed; Effectively improve the uniformity of side wall, thereby improved the uniformity that writes;
Simultaneously said double-deck side wall is between floating boom and word line, promptly as the clearance layer of floating boom and word line, and only needs etching oxidation silicon and the two-layer material of silicon nitride layer can form clearance layer, effectively improve the uniformity of clearance layer, thereby raising writes uniformity.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (25)
1. the formation method of a discrete grid memory device is characterized in that, comprising:
Substrate is provided, is formed with floating gate oxide layers, floating gate polysilicon layer, dielectric layer and control gate polysilicon layer on the said substrate successively;
With said floating gate polysilicon layer is etching stop layer, and etching control gate polysilicon layer forms two control gates, and the space of a side is for wiping the grid region in opposite directions for said two control gates, and the space of said two opposing sides of control gate is the word line district;
Formation is positioned at the side wall of each control gate both sides, and said side wall also is positioned at a side in the nearly word line of said floating gate polysilicon layer district;
Form the sacrifice side wall on the surface of said side wall;
With said sacrifice side wall is mask, and the said floating gate polysilicon layer of etching forms floating boom; One end in the nearly word line of said floating boom district flushes with control gate; The other end removes and to be positioned at the control gate below, also be positioned at double-deck side wall and sacrifice the side wall below, said two floating booms in opposite directions the space of a side for wiping the grid region;
Substrate between two floating booms closely wiping the grid region is carried out ion inject, form the source region;
Remove said sacrifice side wall, said floating boom side direction protrudes in said control gate structure, is formed with the side direction protuberance of floating boom;
Form tunnel oxide, said tunnel oxide Coverage Control grid are closely wiped the surface of grid region one side and the surface that floating boom is closely wiped grid region one side, and the thickness of said tunnel oxide is less than the thickness of sacrificing side wall;
Formation be positioned at the word line in word line district and be positioned at word line and substrate between the word line oxide layer, form and to be positioned at the erase gate of wiping the grid region, said erase gate and FGS floating gate structure have the lap of side direction, are formed with side wall between said word line and floating boom.
2. according to the formation method of the said discrete grid memory device of claim 1; It is characterized in that the thickness range of said sacrifice side wall is
3. according to the formation method of the said discrete grid memory device of claim 1; It is characterized in that the thickness of said tunnel oxide is
4. according to the formation method of the said discrete grid memory device of claim 1; It is characterized in that the width range of the lap of said erase gate and FGS floating gate structure side direction is
5. according to the formation method of the said discrete grid memory device of claim 2, it is characterized in that the material of said sacrifice side wall is silica or polymer.
6. according to the formation method of the said discrete grid memory device of claim 1, it is characterized in that said side wall is the double-deck side wall of silica, silicon nitride.
7. according to the formation method of the said discrete grid memory device of claim 6; It is characterized in that; The formation method of said double-deck side wall comprises: at first form silicon oxide layer and silicon nitride layer at floating gate polysilicon layer and control gate surface; Then said silicon oxide layer of etching and silicon nitride layer form side wall in said control gate both sides, and said side wall also is positioned at a side in the nearly word line of said floating gate polysilicon layer district.
8. according to the formation method of the said discrete grid memory device of claim 1, it is characterized in that, comprise that also with said control gate be mask, inject, with the adjusting of the threshold voltage that carries out the word line district to carrying out ion in the substrate in said word line district.
9. the formation method of said according to Claim 8 discrete grid memory device is characterized in that, comprises that also with said control gate be mask, removes the floating gate polysilicon layer that is positioned at the word line district.
10. according to the formation method of the said discrete grid memory device of claim 1, it is characterized in that the method for said formation tunnel oxide is a low-pressure chemical vapor phase deposition technology.
11. the formation method according to the said discrete grid memory device of claim 1 is characterized in that, form said tunnel oxide after, also comprise and remove the floating gate oxide layers be positioned at said word line district.
12. the formation method according to the said discrete grid memory device of claim 10 is characterized in that, remove be positioned at the floating gate oxide layers in said word line district after, also be included on the substrate in said word line district and form the word line oxide layer.
13. formation method according to the said discrete grid memory device of claim 12; It is characterized in that said word line thickness of oxide layer scope is
14. formation method according to the said discrete grid memory device of claim 1; It is characterized in that the thickness of said floating gate oxide layers is
15. formation method according to the said discrete grid memory device of claim 1; It is characterized in that the thickness of said floating gate polysilicon layer is
16. formation method according to the said discrete grid memory device of claim 1; It is characterized in that the thickness of said control gate polysilicon layer is
17. a discrete grid memory device comprises:
Substrate, be positioned on the said substrate form the word line district and be adjacent wipe the grid region, said word line district and erase gate interval also are formed with FGS floating gate structure and are positioned at the surperficial control gate of said FGS floating gate structure;
Wherein, Said word line district comprises the word line oxide layer that is positioned on the said substrate and is positioned at the word line on the said word line oxide layer; Said FGS floating gate structure comprises the floating boom that is positioned at the floating gate oxide layers on the said substrate and is positioned at said floating gate oxide layers surface; Said floating boom protrudes in said control gate, is formed with floating boom side direction protuberance;
The said grid region of wiping comprises tunnel oxide and the erase gate that is positioned on the said substrate, and said tunnel oxide also is coated with said erase gate side and floating boom protuberance;
Also comprise side wall, said side wall is positioned between tunnel oxide and said control gate, between tunnel oxide and FGS floating gate structure, between word line and control gate and between word line and FGS floating gate structure.
Wherein, said erase gate and floating boom have the lap of side direction.
18. according to the said discrete grid memory device of claim 17; It is characterized in that the width range of said floating boom side direction protuberance is
19. according to the said discrete grid memory device of claim 17; It is characterized in that the thickness of said tunnel oxide is
20. according to the said discrete grid memory device of claim 17; It is characterized in that the width range of the lap of said erase gate and FGS floating gate structure side direction is
21., it is characterized in that said side wall is the double-deck side wall of silica, silicon nitride according to the said discrete grid memory device of claim 17.
22. according to the said discrete grid memory device of claim 17; It is characterized in that said word line thickness of oxide layer scope is
23. according to the said discrete grid memory device of claim 17; It is characterized in that the thickness range of said floating gate oxide layers is
24. according to the said discrete grid memory device of claim 17; It is characterized in that the thickness range of said floating boom is
25. according to the said discrete grid memory device of claim 17; It is characterized in that the thickness range of said control gate is
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