CN103715144B - Discrete grid storage device and forming method thereof - Google Patents
Discrete grid storage device and forming method thereof Download PDFInfo
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- CN103715144B CN103715144B CN201210378507.1A CN201210378507A CN103715144B CN 103715144 B CN103715144 B CN 103715144B CN 201210378507 A CN201210378507 A CN 201210378507A CN 103715144 B CN103715144 B CN 103715144B
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention provides a kind of discrete grid storage device and forming method thereof.The formation method of discrete grid storage device comprises: provide substrate, formation control grid structure on substrate, and the region between adjacent two control gate structures is erasing grid region, and adjacent two control gate structures side relative with described erasing grid region is wordline district; Described control gate structure periphery forms the first side wall; The second side wall is formed around first side wall; Formed around second side wall and sacrifice side wall; Form floating boom; Remove described sacrifice side wall, expose floating gate portion; Form tunneling medium layer, form wordline in wordline district, form erase gate in erasing grid region.The present invention also provides a kind of discrete grid storage device.First, second side wall of the present invention adds wordline and control gate, wordline and floating boom, isolation effect between control gate and erase gate, improve the programming efficiency of memory device, uniformity and efficiency of erasing, uniformity, especially the electric leakage between wordline and floating boom is reduced, to solve write interference problem.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly a kind of discrete grid storage device and forming method thereof.
Background technology
In current semiconductor industry, integrated circuit (IC) products mainly can be divided into three major types type: analog circuit, digital circuit and DA combination circuit, and wherein memory device is an important kind in digital circuit.In recent years, in memory device, the development of flash memory (flashmemory) is particularly rapid.The main feature of flash memory is the information that can keep for a long time when not powering up storing; And have that integrated level is high, access speed is fast, be easy to the advantages such as erasing and rewriting, be thus widely used in the multinomial field such as microcomputer, Automated condtrol.
Flash memory mainly comprises stacked gate flash memory and flash memory of discrete gate, and wherein, flash memory of discrete gate has the high advantage of low program voltage, programming efficiency and is used widely.
Fig. 1 gives a flash memory of discrete gate, comprise: Semiconductor substrate 100, be positioned at the erase gate (EG:erasinggate) 105 in Semiconductor substrate 100, tunnel oxide 108, described tunnel oxide 108 part is positioned in Semiconductor substrate 100, and part is positioned at the sidewall of erase gate 105; Be positioned at the source region (not shown) that Semiconductor substrate 100 is relative with erase gate 105; Be positioned at floating gate structure and the control gate structure of erase gate 105 both sides, described floating gate structure comprises the floating gate dielectric layer 102a being positioned at Semiconductor substrate 100 surface and the floating boom 102 be positioned on floating gate dielectric layer 102a, described control gate structure comprises the control gate dielectric layer 103a that is positioned at floating boom 102 surface and is positioned at the control gate 103 on control gate dielectric layer 103a, is positioned at floating gate structure and the control gate structure side wall 107 away from erase gate 105 side; Be positioned at side wall 107 away from the wordline 104 in the Semiconductor substrate 100 of erase gate 105 side; Wordline oxide layer 104a between wordline 104 and Semiconductor substrate 100; Be positioned at the drain region (not shown) of wordline 104 away from erase gate 105 side Semiconductor substrate 100.
The programming of existing flash memory of discrete gate and the efficiency of erasing and uniformity bad, especially write interference (disturb) larger.
More introductions about flash memory of discrete gate please refer to the Chinese patent that publication number is CN101202311A.
Summary of the invention
The problem that the present invention solves is that the programming of flash memory of discrete gate and efficiency of erasing and uniformity are bad, especially writes interference (disturb) larger.
For solving the problem, the invention provides a kind of formation method of discrete grid storage device, comprising:
Substrate is provided, described substrate is formed with first medium layer, floating gate layer, second dielectric layer and control grid layer successively;
Etch described control grid layer and second dielectric layer formation control grid structure, the region between adjacent two control gate structures is erasing grid region, and adjacent two control gate structures side relative with described erasing grid region is wordline district;
The first side wall is formed at described control gate structure periphery;
After forming the first side wall, remove the floating gate layer be positioned in wordline district;
After removing the floating gate layer be positioned in wordline district, around the first side wall, form the second side wall;
Formed around described second side wall and sacrifice side wall;
Formed after sacrificing side wall, remove the floating gate layer being positioned at erasing grid region, form floating boom;
Remove the described sacrifice side wall being positioned at erasing grid region, expose the floating gate portion of sacrificing side wall and covering;
Form tunneling medium layer, cover the second side wall between the floating gate portion exposed, the substrate wiping grid region, adjacent two control gate structures, the thickness of described tunneling medium layer is less than the thickness of sacrificing side wall;
Form wordline in wordline district, form erase gate in erasing grid region.
Optionally, the material of described floating gate layer and described control grid layer is all polysilicon.
Optionally, the first side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.
Optionally, the second side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.
Optionally, the material of described sacrifice side wall is silica or polymer.
Optionally, after removing described sacrifice side wall, also step is comprised: the second side wall removing erasing grid region.
Optionally, after forming the first side wall, also comprise step before removing the floating gate layer be positioned in wordline district: with described first side wall for mask, ion implantation is carried out to the substrate in described wordline district, to carry out the adjustment of the threshold voltage in wordline district.
Optionally, after forming described tunneling medium layer, before wordline district forms wordline, also comprise step: remove the first medium floor being positioned at described wordline district.
Optionally, remove after being positioned at the first medium floor in described wordline district, the substrate being also included in described wordline district forms wordline dielectric layer.
The present invention also provides a kind of discrete grid storage device, comprising:
Substrate;
Be positioned at the floating gate structure on described substrate, be positioned at the control gate structure in described floating gate structure and the first side wall, described first side wall is positioned at described control gate structure periphery; Region between adjacent two control gate structures is erasing grid region; Adjacent two control gate structures side relative with described erasing grid region is wordline district; Described floating gate structure comprises floating gate dielectric layer and is positioned at the floating boom on floating gate dielectric layer, and described control gate structure comprises control gate dielectric layer and is positioned at the control gate on control gate dielectric layer;
Have the second side wall around described floating gate structure and described first side wall, described in erasing side, grid region, floating gate structure has the boss of outstanding second side wall;
Tunneling medium layer, cover the second side wall between described boss, the substrate in erasing grid region, adjacent two control gate structures, the described thickness then wearing dielectric layer is less than the width of boss;
The wordline being positioned at the wordline dielectric layer in described wordline district and being positioned on described wordline dielectric layer;
Be positioned at the erase gate then wearing dielectric layer described in the covering on described erasing grid region.
Optionally, described first side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.
Optionally, described second side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.
Compared with prior art, such scheme has the following advantages:
The first side wall is formed at control gate structure periphery, with the first side wall for mask etches the floating gate layer below control gate structure, replace directly with control gate structure for mask etches described floating gate layer, reduce the damage of etching to control gate structure, namely, the formation of the first side wall can not make the thickness of control gate reduce or make control gate surface irregularity, improves the uniformity of control gate body structure surface, thus improves the efficiency of programming and the uniformity of programming.
The first side wall is formed and the second side wall replaces individual layer side wall of the prior art between control gate and wordline.Wherein, the first side wall is identical with the thickness of side wall of the prior art with the gross thickness of the second side wall.Between floating boom and wordline, form the second side wall replace individual layer side wall of the prior art.When separate gate memory part of the present invention enters programming state, while not affecting programming efficiency, change the internal structure of the side wall between control gate and wordline, between floating boom and wordline, add the isolation effect of side wall, thus reduce the generation of leakage current, further reduction leakage current enters the probability of floating boom under the effect of control gate, namely, reduce the electric leakage between wordline and floating boom, avoid making the unit that should not carry out writing change write change occur, to solve write interference problem during programming.
Have the second side wall around described floating gate structure and described first side wall, described in erasing side, grid region, floating gate structure has the boss of outstanding second side wall.Tunneling medium layer covers described boss, and covers the second side wall between the substrate in erasing grid region, adjacent two control gate structures.The described thickness then wearing dielectric layer is less than the thickness of boss, to there is lateral overlap part at the erase gate and floating boom of wiping grid region formation, described lateral overlap part can make the electronics of then wearing in tunneling medium layer increase, and then the electric current of then wearing in tunneling medium layer is increased, improve efficiency of erasing.
When separate gate memory part of the present invention enters erase status, form the first side wall, the second side wall and tunneling medium layer between control gate and erase gate and replace tunnel oxide of the prior art, wherein, the first side wall, the second side wall are identical with the thickness of tunnel oxide of the prior art with the gross thickness of tunneling medium layer.While not affecting efficiency of erasing, add the isolation effect of side wall, thus reduce the generation of leakage current, thus erasing uniformity when improving erasing.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawing indicates identical part.The drafting of accompanying drawing, not deliberately according to actual ratio, focuses on purport of the present invention is shown.In the accompanying drawings, for cheer and bright, part layer and region are amplified.
Fig. 1 is the structural representation of prior art discrete grid storage device;
Fig. 2 is the schematic flow sheet of the formation method of the discrete grid storage device of one embodiment of the invention;
Fig. 3 to Figure 16 is the embodiment cross-sectional view of the formation method of the discrete grid storage device of one embodiment of the invention.
Embodiment
With reference to figure 1, when existing flash memory of discrete gate is programmed, positive voltage is applied at control gate 103, wordline 104 applies operating voltage makes the channel region of below open, drain region applies negative voltage, and source region ground connection, when the voltage of control gate 103 is greater than drain voltage, electrons in conducting channel is accelerated and transits to floating boom 102 from channel region by the gap (gap) 10 between wordline 104 and floating boom 102, and then completes the action of programming (write); When existing flash memory of discrete gate is wiped, control gate 103 ground connection, erase gate 105 adds positive voltage, and electronics is worn to erase gate 105 then by floating boom 102, completes the erasing to electric charge in floating boom 102.
It is bad that inventor finds to affect the programming of flash memory of discrete gate and efficiency of erasing and uniformity, and the main cause especially writing interference (disturb) larger is as follows:
(1) uniformity of control gate body structure surface and flash memory of discrete gate carry out the efficiency of programming and wiping and uniformity positive correlation, be specially: the uniformity on control gate surface can affect the uniformity of programming and erasing electric current, programming and the erasing uniformity of electric current and the efficiency of programming and erasing and uniformity positive correlation, therefore the uniformity of control gate body structure surface is better, the uniformity of programming and erasing electric current is higher, and efficiency and the uniformity of programming and erasing are higher.
(2) in the process of existing making flash memory of discrete gate, the material of the side wall 107 formed is the single layer structure of silica, silica is easily damaged in subsequent wet etching technics, reduce thickness and the surface uniformity of side wall 107, namely, reduce the uniformity of flash memory of discrete gate program current, thus have impact on efficiency and the uniformity of programming.
(3) in the process of existing making flash memory of discrete gate, the side wall 107 formed is the single layer structure of silica, structure is single, well can not isolate between wordline and control gate, between wordline and floating boom, thus can not effectively stop leakage current to enter floating boom under the effect of control gate, reduce the electric leakage between wordline and floating boom, make the unit that should not carry out writing change that write change occur, and then produce write interference problem.
(4) key factor affecting flash memory of discrete gate efficiency of erasing is then wear electric current in tunneling medium layer, and then wear electric current large, the efficiency of erasing of memory is just high, if it is little then to wear electric current, the efficiency of erasing of memory is just low.Prior art normally improves erasing voltage and then wears electric current to increase in tunneling medium layer, and the raising of erasing voltage can affect the stability of flash memory of discrete gate and increase power consumption, therefore, in the prior art, improving flash memory of discrete gate efficiency of erasing is a difficult problem, and inventor finds that floating boom and tunneling medium layer, contact area between tunneling medium layer and erase gate are relevant with the size of then wearing electric current further.Increase floating boom and tunneling medium layer, contact area between tunneling medium layer and erase gate can increase the quantity of then wearing electronics, and then increase and then wear electric current in tunneling medium layer, and then improve efficiency of erasing.
(5) in prior art, tunnel oxide between control gate and erase gate 108 is single layer structure, can not to well isolating between control gate and erase gate, leakage current can not be reduced, thus flash memory of discrete gate produces the bad problem of erasing uniformity when wiping.
So inventor, through creative work, obtains a kind of formation method of discrete grid storage device.Fig. 2 is the formation method flow schematic diagram of the discrete grid storage device of one embodiment of the invention, and Fig. 3 to Figure 16 is the embodiment cross-sectional view of the formation method of the discrete grid storage device of one embodiment of the invention.Below Fig. 3 to Figure 16 is combined with Fig. 2 and the formation method of discrete grid storage device is described in detail.
First, with reference to figure 3, perform the step S1 in Fig. 2, substrate 300 is provided, described substrate 300 is formed with successively first medium layer 301, floating gate layer 302, second dielectric layer 303 and control grid layer 304.
Described substrate 300 can be silicon or the SiGe of monocrystalline, polycrystalline or non crystalline structure, also can be silicon-on-insulator (SOI).Or other material can also be comprised, such as GaAs etc. three or five compounds of group.
Described first medium layer 301, the present embodiment can be silica, and thickness range is 80 ~ 100 dusts.Described floating gate layer 302, the present embodiment can be polysilicon, and thickness range is 300 ~ 500 dusts.
Described second dielectric layer 303 can be silica or the laminated construction for oxide-nitride-oxide (ONO).Second dielectric layer 303 described in the present embodiment is the laminated construction of oxide-nitride-oxide (ONO).The thickness range of described second dielectric layer 303 is 140 ~ 160 dusts.
Described control grid layer 304, the present embodiment can be polysilicon, and thickness range is 500 ~ 900 dusts.
The material being arranged in the hard mask layer 305 on control grid layer 304 can be one or more of silica, silicon nitride, silicon oxynitride or metal hard mask.The present embodiment is silicon nitride, and thickness range is 800 ~ 1200 dusts, and described hard mask layer 305 is as polish stop layer when formation erase gate and wordline.
With reference to figure 4, perform the step S2 in Fig. 2, etch described control grid layer 304 and second dielectric layer 303 formation control grid structure 30, the region between adjacent two control gate structures 30 is erasing grid region 40, and adjacent two control gate structures 30 side relative with described erasing grid region 40 is wordline district 50.
Particularly, described etching adopts dry etching, and described dry etching adopts reactive ion etching, and process gas used is mainly fluoro-gas.The hard mask layer 305 of etching shown in Fig. 3 is also comprised in above-mentioned etch step.The control gate 307 that the control gate structure 30 that etching is formed comprises control gate dielectric layer 306 and is positioned on control gate dielectric layer 306.
With reference to figure 5, perform the step S3 in Fig. 2, around described control gate structure 30, form the first side wall 309.
Described first side wall 309 is the laminated construction of silicon oxide layer 309a and silicon nitride layer 309b, comprises silicon oxide layer 309a and silicon nitride layer 309b, and outside being exposed to is silicon nitride layer 309b.Silicon nitride layer 309b needs enough even, to improve the equal of follow-up the second side wall formed around silicon nitride layer 309b and property, and then improves the stability of flash memory of discrete gate.
Then, with reference to figure 6 and Fig. 7, perform the step S4 in Fig. 2, after forming the first side wall 309, remove the floating gate layer 302 be positioned in wordline district 50.
Concrete grammar is: with reference to figure 6, form mask layer 310, the present embodiment is photoresist layer, region between described mask layer 310 Coverage Control grid structure 30, and cover hard mask layer 305, with mask layer 310 and the first side wall 309 for mask, ion implantation is carried out to the substrate 300 being positioned at wordline district 50, to carry out threshold voltage adjustments to wordline district 50.
After ion implantation, with reference to figure 7, to continue with mask layer 310 and the first side wall 309, for mask, to etch described floating gate layer 302, remove the floating gate layer 302 be positioned in wordline district 50.Now, expose described first medium layer 301, then remove mask layer 310.
It should be noted that, be that mask etches the floating gate layer 302 below control gate structure 30 with the first side wall 309, replace directly etching described floating gate layer 302 for mask with control gate structure 30 in prior art, reduce the damage of etching to control gate structure 30, namely, first side wall 309 can not make the thickness of control gate structure 30 reduce or make control gate structure 30 surface irregularity, thus improve the uniformity on control gate structure 30 surface, and then improve programming, efficiency of erasing and programming, erasing uniformity.
In addition, above-mentioned to wordline district 50 carry out threshold voltage adjustments ion implantation and to the etching of the floating gate layer 302 in wordline district 50 all with described mask layer 310 for mask, simplify processing step.
Then, with reference to figure 8, perform the step S5 in Fig. 2, after removing the floating gate layer 302 be positioned in wordline district 50, around the first side wall 309, form the second side wall 311.
Described second side wall 311 is the laminated construction of silicon oxide layer 311a and silicon nitride layer 311b, and being exposed to outer is silicon nitride layer.
The gross thickness of the second side wall and the first side wall equals the thickness of individual layer side wall in prior art.If the too thick distance by the floating boom of the channel region made below follow-up formation wordline and follow-up formation of the gross thickness of the first side wall and the second side wall becomes large, when programming to memory device, when floating boom applies identical program voltage, the transition potential energy change of floating boom is transitted to greatly from channel region by making electronics, be unfavorable for the injection of electronics to floating boom of channel region, reduce size and the uniformity of program current, reduce efficiency and the uniformity of programming, when especially programming to multiple memory cell, this impact is particularly serious; If the gross thickness of the first side wall and the second side wall is too thin, the lateral separation of the floating boom of channel region and follow-up formation reduces, when programming, the transverse electric field that program voltage is applied to interstitial area between channel region and floating boom increases, be unfavorable for the injection of electronics to floating boom of channel region, reduce the size of program current, reduce efficiency and the uniformity of programming, when especially programming to multiple memory cell, this impact is particularly serious.
In the present embodiment, dry etching silicon oxide layer and silicon nitride layer is adopted to form the second side wall 311.It should be noted that, described dry etching carries out etch nitride silicon layer and silicon oxide layer in same etching machine bench, is and once etches, and simplifies technological process on the one hand; Avoid on the other hand the dimensional discrepancy caused at different etching equipment or different etching technique etch nitride silicon layer and silicon oxide layer, improve the uniformity of the second side wall 311.
With reference to figure 9, perform the step S6 in Fig. 2, formed around described second side wall 311 and sacrifice side wall 312.
The thickness range of the sacrifice side wall 312 formed is 200 ~ 400 dusts.In the present embodiment, sacrificing side wall 312 is silica.As other embodiments, described sacrifice side wall 312 can also be polymer, as photoresistance.
With reference to Figure 10 and Figure 11, perform the step S7 in Fig. 2, formed after sacrificing side wall 312, etching is positioned at the floating gate layer 302 in erasing grid region 40, forms floating boom 313.Be specially:
With reference to Figure 10, form mask layer 314, the present embodiment is photoresist layer, and described mask layer 314 covering is positioned at sacrifice side wall 312 surface in wordline district 50, first medium floor 301 surface in wordline district 50 and hard mask layer 305.
With reference to Figure 11, with described mask layer 314 for mask, described floating gate layer 302 is etched, form floating boom 313.First medium layer below floating boom 313 is floating gate dielectric layer, and its thickness range is
floating boom 313 forms floating gate structure with the floating gate dielectric layer under it.In the present embodiment, can continue with described mask layer 314 for mask, ion implantation is carried out to described substrate 300, form source region (not shown).
Above-mentioned formation floating boom 313 and formed source region all with described mask layer 314 for mask, simplify processing step, save process costs.
Please refer to Figure 11, perform the step S8 in Fig. 2, remove the described sacrifice side wall 312 being positioned at erasing grid region 40, expose the floating gate portion of sacrificing side wall 312 and covering.
Remove around the second side wall 311 and the method for sacrifice side wall 312 being positioned at erasing grid region 40 is wet etching, the solution of described wet etching is hydrofluoric acid.In the present embodiment, because the material of first medium layer 301 is all silica with the material of sacrifice side wall 312, while removing the sacrifice side wall 312 being positioned at erasing grid region 40, the first medium layer 301 in erasing grid region 40 can be removed.
It should be noted that; because the outermost layer of the second side wall 311 in the present invention is silicon nitride layer 311b; in the process of sacrifice side wall 312 removing erasing grid region 40; second side wall 311 in erasing grid region 40 can not reduce or surface irregularity by thickness because there being the protection of silicon nitride layer 311b; effectively improve the uniformity of the second side wall 311, improve the programming uniformity of described discrete grid storage device.
After removing the sacrifice side wall 312 being positioned at erasing grid region 40, expose the floating boom 313 of sacrificing side wall 312 and covering, that is, form the boss of outstanding second side wall 311 at the floating gate structure place in erasing grid region 40.
After floating gate structure forms boss, remove mask layer 314.
Then, with reference to Figure 14, perform the step S9 in Fig. 2, form tunneling medium layer 316, cover the second side wall 311 between the floating gate portion exposed, the substrate 300 wiping grid region 40, adjacent two control gate structures 30, the thickness of described tunneling medium layer 316 is less than the thickness of sacrificing side wall 312.
The method of concrete formation tunneling medium layer 316 comprises: with reference to Figure 12, adopts the method for deposition to form the material layer 316 ' of tunneling medium layer.The material layer 316 ' of described tunneling medium layer requires higher for film quality, and the present embodiment is silicon oxide layer.Its generation type is specifically as follows plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD).The present embodiment selects low-pressure chemical vapor phase deposition, and the thickness of the material layer 316 ' of described tunneling medium layer is
in this case
In conjunction with reference Figure 13 and Figure 14, form mask layer 317, the present embodiment is photoresist layer, is covered in erasing grid region 40.Be positioned at the material layer 316 ' of tunneling medium layer on wordline district 50 substrate with mask layer 317 for mask removal, be positioned at the material layer 316 ' of the tunneling medium layer on hard mask layer 305, be positioned at the sacrifice side wall 312 in wordline district 50 and be positioned at the first medium floor 301 in wordline district 50.Described removal is wet etching.Described wet etching solution is hydrofluoric acid.
Remove mask layer 317 afterwards, form tunneling medium layer 316.The thickness of described tunneling medium layer 316 is less than the transverse width of described floating boom boss.
It should be noted that; because the outermost layer of the second side wall 311 in the present invention is silicon nitride layers; remove in wordline district 50 in the process of the sacrifice side wall 312 covering its surface; second side wall 311 can not be damaged because of the protection of silicon nitride; namely; the thickness of the second side wall 311 can not reduce or the second side wall 311 surface still smooth, effectively improve the uniformity of the second side wall 311, improve the programming uniformity of described discrete grid storage device.
Then, with reference to Figure 15 and Figure 16, perform the step S10 in Fig. 2, form wordline 319 in wordline district 50, form erase gate 320 in erasing grid region 40.
Formed after then wearing dielectric layer 316, with reference to Figure 15, the wordline district 50 on described substrate 300 surface forms wordline dielectric layer 318, and the present embodiment is oxide layer, and the thickness range of described wordline dielectric layer 318 is
with reference to Figure 16, described wordline district 50 is formed the wordline (wordline:WL) 319 being positioned at described wordline dielectric layer 318, and is positioned at the erase gate 320 in described tunneling medium layer 316.Wherein erase gate 320 and wordline 319 are polysilicon layer, and generation type is low-pressure chemical vapor phase deposition technique, then carry out photoetching, etching technics to the polysilicon layer of deposit, finally form device architecture as shown in figure 16.
Wherein, it should be noted that, described erase gate 320 has lateral overlap part with floating boom 313.The forming process of described lateral overlap part please refer to step S6 to step S10: after forming floating boom 313, remove the sacrifice side wall 312 being positioned at erasing grid region 40, expose the floating gate portion of sacrificing side wall 312 and covering, namely, form the boss of outstanding second side wall at the floating gate structure place in erasing grid region 40, and the thickness of the tunneling medium layer 316 formed on boss is less than the transverse width of described floating boom boss.Just have lateral overlap part at the erase gate 320 then wearing formation on dielectric layer 316 with floating gate structure like this, the width range of described lap is
the design of described lateral overlap part avoids and adopts the method improving erasing voltage to improve the quantity of tunelling electrons in prior art.Erase gate 320 and floating gate structure are carried out lateral overlap and add floating boom 313 and tunneling medium layer 316, contact area between tunneling medium layer 316 and erase gate 320 by the present invention, thus increase the quantity of tunelling electrons, electric current of then wearing in tunneling medium layer is increased, and then improves erasing speed.
In other embodiment, after forming floating boom 313, except removing the sacrifice side wall 312 being positioned at erasing grid region 40, the second side wall 311 can also be continued to remove, increase to make the boss area of floating gate structure.Be specially, first can will be positioned at the silicon nitride layer place to go of erasing grid region 40 second side wall 311, the silicon oxide layer of the second side wall 311 being positioned at erasing grid region 40 as etching stop layer, and then is removed by the silicon oxide layer inside it, and now the silicon nitride layer of the first side wall 309 is as etching stop layer.The wet etching solution that etching is positioned at the silicon nitride layer of second side wall 311 in erasing grid region 40 is hot phosphoric acid, and the wet etching solution of the silicon oxide layer in it is hydrofluoric acid.It should be noted that; during the silicon oxide layer of the second side wall 311 around removal first side wall 309; the outermost layer of the first side wall 309 is silicon nitrides; the first side wall 309 can be protected injury-free; ensure that the uniformity on the first side wall 309 surface, further enhance the protection of the uniformity of the first side wall 309 pairs of control gate structures.Improve the programming uniformity of described discrete grid storage device.
The boss area of floating gate structure increases, then, erase gate 320 also increases with the area of floating boom 313 lateral overlap part, thus adds the quantity of tunelling electrons, and then improves efficiency of erasing.It should be noted that, even if remove the second side wall, the first side wall too increases isolation effect, now, tunneling medium layer equal the thickness of existing tunnel oxide with the gross thickness of the first side wall.That is, improve efficiency of erasing and the uniformity of discrete grid storage device.
What needs went on to say is, the formation of the first side wall in the present invention, not only makes control gate body structure surface even, and can improve the isolation effect between control gate and wordline, between control gate and erase gate, improve the uniformity of programming and erasing, thus improve the efficiency of programming and erasing.
Further, form the first side wall and the second side wall replaces individual layer side wall of the prior art between control gate and wordline, wherein, the first side wall is identical with the thickness of side wall of the prior art with the gross thickness of the second side wall.Between floating boom and wordline, form the second side wall replace individual layer side wall of the prior art.When separate gate memory part of the present invention enters programming state, while not affecting programming efficiency, change the internal structure of the side wall between control gate and wordline, between floating boom and wordline, add the isolation effect of side wall, thus reduce the generation of leakage current, reduce the probability that leakage current enters floating boom under the effect of control gate further, namely, reduce the electric leakage between wordline and floating boom, make the unit that should not carry out writing change write change occur, to solve write interference problem during programming.
In addition, form the first side wall, the second side wall and tunneling medium layer between control gate and erase gate and replace tunnel oxide of the prior art, wherein, the first side wall, the second side wall are identical with the thickness of tunnel oxide of the prior art with the gross thickness of tunneling medium layer.While not affecting efficiency of erasing, add the isolation effect of side wall, thus reduce the generation of leakage current, thus improve erasing uniformity.
Further, described second side wall is filled with the gap (gap) between wordline and floating boom.The outermost layer of described second side wall is silicon nitride, and at removal floating gate dielectric layer to be formed in the technique of wordline dielectric layer, described second side wall solution such as the hydrofluoric acid that can not be etched is got rid of; Remove sacrifice side wall time, described second side wall solution such as the hydrofluoric acid that can not be etched equally is removed; When removing the tunneling medium layer being positioned in wordline district, described second side wall solution such as the hydrofluoric acid that can not be etched equally is removed, that is, the gap (gap) protected between wordline and floating boom can not be corroded.When programming to a point grid memory, the electronics of channel region transits to floating boom side wall via gap and reduces the impact of program current, improves the uniformity of program current, thus improves efficiency and the uniformity of programming.
With reference to Figure 16, the present invention also provides a kind of institute discrete grid storage device, comprising:
Substrate 300;
Be positioned at the floating gate structure on described substrate 300, be positioned at the control gate structure 30 in described floating gate structure and the first side wall 309, described first side wall 309 is positioned at around described control gate structure 30; Region between adjacent two control gate structures 30 is erasing grid region 40; Adjacent two control gate structures 30 side relative with described erasing grid region 40 is wordline district 50; Described floating gate structure comprises floating gate dielectric layer and is positioned at the floating boom 313 on floating gate dielectric layer, the control gate 307 that described control gate structure 30 comprises control gate dielectric layer 306 and is positioned on control gate dielectric layer 306.
Have the second side wall 311 around described floating gate structure and described first side wall 309, described in erasing side, grid region 40, floating gate structure has the boss of outstanding second side wall 311; Tunneling medium layer 316 covers described boss, and covers the second side wall 311 between the substrate in erasing grid region 40, adjacent two control gate structures 30, and the described thickness then wearing dielectric layer 316 is less than the thickness of boss;
The wordline 319 being positioned at the wordline dielectric layer 318 in described wordline district 50 and being positioned on described wordline dielectric layer 318;
Be positioned at then wearing dielectric layer 316 and then wearing the erase gate 320 of dielectric layer 316 described in covering on described erasing grid region 40.
Wherein, described first side wall 309 comprises silicon oxide layer 309a and is formed at the silicon nitride layer 309b on described silicon oxide layer 309a.Described second side wall 311 comprises silicon oxide layer 311a and is formed at the silicon nitride layer 311b on described silicon oxide layer 311a.
The thickness range of described wordline dielectric layer 318 is
the thickness range of described floating gate dielectric layer is
the thickness range of described floating boom is
the thickness range of described control gate 307 is
described erase gate 320 and floating gate structure have the lap of side direction, and the width range of described lap is
the lap of described side direction effectively increases the quantity of tunelling electrons, improves erasing speed.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (12)
1. a formation method for discrete grid storage device, is characterized in that, comprising:
Substrate is provided, described substrate is formed with first medium layer, floating gate layer, second dielectric layer and control grid layer successively;
Etch described control grid layer and second dielectric layer formation control grid structure, the region between adjacent two control gate structures is erasing grid region, and the side that adjacent two control gate structures deviate from described erase gate is wordline district;
The first side wall is formed at described control gate structure periphery;
After forming the first side wall, remove the floating gate layer be positioned in wordline district;
After removing the floating gate layer be positioned in wordline district, around the first side wall, form the second side wall;
Formed around described second side wall and sacrifice side wall;
Formed after sacrificing side wall, remove the floating gate layer being positioned at erasing grid region, form floating boom;
Remove the described sacrifice side wall being positioned at erasing grid region, expose the floating gate portion of sacrificing side wall and covering;
Form tunneling medium layer, cover the second side wall between the floating gate portion exposed, the substrate wiping grid region, adjacent two control gate structures, the thickness of described tunneling medium layer is less than the thickness of sacrificing side wall;
Form wordline in wordline district, form erase gate in erasing grid region.
2. the formation method of discrete grid storage device according to claim 1, it is characterized in that, the material of described floating gate layer and described control grid layer is all polysilicon.
3. the formation method of discrete grid storage device according to claim 1, is characterized in that, the first side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.
4. the formation method of discrete grid storage device according to claim 1, is characterized in that, the second side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.
5. the formation method of discrete grid storage device according to claim 1, it is characterized in that, the material of described sacrifice side wall is silica or polymer.
6. the formation method of discrete grid storage device according to claim 1, is characterized in that, after removing described sacrifice side wall, also comprise step: the second side wall removing erasing grid region.
7. the formation method of discrete grid storage device according to claim 1, it is characterized in that, after forming the first side wall, also step is comprised: with described first side wall for mask before removing the floating gate layer be positioned in wordline district, ion implantation is carried out to the substrate in described wordline district, to carry out the adjustment of the threshold voltage in wordline district.
8. the formation method of discrete grid storage device according to claim 1, is characterized in that, after forming described tunneling medium layer, before wordline district forms wordline, also comprises step: remove the first medium floor being positioned at described wordline district.
9. the formation method of discrete grid storage device according to claim 8, is characterized in that, removes after being positioned at the first medium floor in described wordline district, and the substrate being also included in described wordline district forms wordline dielectric layer.
10. a discrete grid storage device, is characterized in that, comprising:
Substrate;
Be positioned at the floating gate structure on described substrate, be positioned at the control gate structure in described floating gate structure and the first side wall, described first side wall is positioned at described control gate structure periphery; Region between adjacent two control gate structures is erasing grid region; The side that adjacent two control gate structures deviate from described erase gate is wordline district; Described floating gate structure comprises floating gate dielectric layer and is positioned at the floating boom on floating gate dielectric layer, and described control gate structure comprises control gate dielectric layer and is positioned at the control gate on control gate dielectric layer;
Have the second side wall around described floating gate structure and described first side wall, described in erasing side, grid region, floating gate structure has the boss of outstanding second side wall;
Tunneling medium layer, cover the second side wall between described boss, the substrate in erasing grid region, adjacent two control gate structures, the thickness of described tunneling medium layer is less than the width of boss;
The wordline being positioned at the wordline dielectric layer in described wordline district and being positioned on described wordline dielectric layer;
Be positioned at the erase gate of the described tunneling medium layer of covering on described erasing grid region.
11. discrete grid storage devices as claimed in claim 10, is characterized in that, described first side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.
12. discrete grid storage devices as claimed in claim 10, is characterized in that, described second side wall comprises silicon oxide layer and is formed at the silicon nitride layer on described silicon oxide layer.
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| DE102019112410A1 (en) * | 2018-09-27 | 2020-04-02 | Taiwan Semiconductor Manufacturing Co. Ltd. | Device area layout for embedded flash memory |
| CN109378314B (en) * | 2018-10-09 | 2020-07-07 | 武汉新芯集成电路制造有限公司 | Method for manufacturing flash memory device |
| CN112234096B (en) * | 2020-10-27 | 2024-05-28 | 上海华虹宏力半导体制造有限公司 | Split gate flash memory and preparation method thereof |
| CN113206010B (en) * | 2021-04-30 | 2023-10-24 | 广东省大湾区集成电路与系统应用研究院 | Semiconductor device and method for manufacturing the same |
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| CN101364614A (en) * | 2007-08-06 | 2009-02-11 | 美商矽储科技股份有限公司 | Non-volatile flash memory cell, array and method of manufacturing same |
| CN102543885A (en) * | 2010-12-31 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Split-gate memory device and forming method thereof |
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| CN102543885A (en) * | 2010-12-31 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Split-gate memory device and forming method thereof |
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