CN103165615B - Split-gate flash memory and forming method thereof - Google Patents
Split-gate flash memory and forming method thereof Download PDFInfo
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Abstract
A kind of Split-gate flash memory and forming method thereof, comprising: provide Semiconductor substrate, described semiconductor substrate surface is formed with first medium layer, the first polysilicon layer, second dielectric layer and the second polysilicon layer successively; Etch described second polysilicon layer and second dielectric layer and form two discrete control gate structures; The first side wall is formed at the sidewall of control gate structure both sides; Etch described first polysilicon layer and first medium layer, form floating boom and floating gate dielectric layer and the second opening between two floating booms; The second side wall is formed at floating boom and floating gate dielectric layer sidewall and the first side wall surface; Along the second opening, ion implantation is carried out to Semiconductor substrate, form source region; Remove the second side wall of the second opening sidewalls, form tunnel oxide at the second opening sidewalls and bottom; In the second opening, form erase gate, the Semiconductor substrate of control gate away from erase gate side forms wordline.The embodiment of the present invention improves programming efficiency and the uniformity of Split-gate flash memory.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of Split-gate flash memory and forming method thereof.
Background technology
In current semiconductor industry, integrated circuit (IC) products mainly can be divided into three major types type: analog circuit, digital circuit and DA combination circuit, and wherein memory device is an important kind in digital circuit.In recent years, in memory device, the development of flash memory (flashmemory) is particularly rapid.The main feature of flash memory is the information that can keep for a long time when not powering up storing; And have that integrated level is high, access speed is fast, be easy to the advantages such as erasing and rewriting, be thus widely used in the multinomial field such as microcomputer, Automated condtrol.
Flash memory mainly comprises stacked gate flash memory and Split-gate flash memory, and wherein, Split-gate flash memory has the high advantage of low program voltage, programming efficiency and is used widely.
Fig. 1 gives a Split-gate flash memory, comprise: Semiconductor substrate 100, be positioned at the erase gate (EG:erasinggate) 105 in Semiconductor substrate 100, tunnel oxide 108 between Semiconductor substrate 100 and erase gate 105, described tunnel oxide 108 part is positioned in Semiconductor substrate 100, and part is positioned at the sidewall of erase gate 105; Be positioned at the source region (not shown) that Semiconductor substrate 100 is relative with erase gate 105; Be positioned at the floating gate structure in the Semiconductor substrate 100 of erase gate 105 both sides and control gate build stack, described floating gate structure comprises the floating gate dielectric layer 102a being positioned at Semiconductor substrate 100 surface and the floating boom 102 being positioned at floating gate dielectric layer 102a surface, described control gate structure comprises the control gate dielectric layer 103a being positioned at floating boom 102 surface and the control gate 103 being positioned at control gate dielectric layer 103a surface, and described control gate structure also comprises the side wall 106 being positioned at control gate 103 both sides sidewall on control gate dielectric layer 103a; Be positioned at floating gate structure and the control gate structure side wall 107 away from erase gate 105 side sidewall; Be positioned at side wall 107 away from the wordline 104 in the Semiconductor substrate 100 of erase gate 105 side; Wordline oxide layer 104a between wordline 104 and Semiconductor substrate 100; Be positioned at the drain region (not shown) of wordline 104 away from erase gate 105 side Semiconductor substrate 100.
Composition graphs 1, is described Split-gate flash memory operation principle: due to physical characteristic and the structure of floating boom 102, when it is injected into negatron, and this position is just written to " 0 " by numeral " 1 ", and this process is write, also can be described as programming mode; Relative, after negatron is removed from floating boom 102, this position is just become " 1 " by digital " 0 ", and this process is called erasing.Wherein, tunneling injection method (channelhotinjection) mechanism is adopted during programming, source region (not shown) ground connection, wordline 104 connects operating voltage, when the voltage of control gate 103 is greater than drain region (not shown) voltage, electrons in wordline 104 underlying conductive raceway groove is accelerated to be transitted to floating boom 102 from raceway groove, and then completes the action of programming (write); Used Fowler-Nordheim tunneling effect during erasing, control gate 103 ground connection, erase gate 105 adds positive voltage, and electronics to erase gate 105, completes the erasing to electric charge in floating boom 102 by floating boom 102 tunnelling.Efficiency and the uniformity of programming during existing Split-gate flash memory programming are bad.
More introductions about Split-gate flash memory please refer to the Chinese patent that publication number is CN101202311A.
Summary of the invention
The problem that the present invention solves is to provide a kind of Split-gate flash memory and forming method thereof, improves programming efficiency and uniformity.
For solving the problem, the invention provides a kind of formation method of Split-gate flash memory, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with first medium layer, the first polysilicon layer, second dielectric layer and the second polysilicon layer successively;
Etch described second polysilicon layer and second dielectric layer and form two discrete control gate structures, have the first opening between two control gate structures, described control gate structure comprises control gate dielectric layer and is positioned at the control gate on control gate dielectric layer;
The first side wall is formed at the sidewall of control gate structure both sides;
With described control gate structure and the first side wall for mask, etch described first polysilicon layer and first medium layer, form floating boom and floating gate dielectric layer and the second opening between two floating booms;
Form the second side wall at floating boom and floating gate dielectric layer sidewall and the first side wall surface, described second side wall is the laminated construction of silicon oxide layer and silicon nitride layer;
Along the second opening, ion implantation is carried out to Semiconductor substrate, form source region;
Remove the second side wall of the second opening sidewalls, form tunnel oxide at the second opening sidewalls and bottom;
In the second opening, form erase gate, at control gate and floating boom, the Semiconductor substrate away from erase gate side forms wordline.
Optionally, the formation method of described second side wall is: form the silicon oxide layer covering floating boom and floating gate dielectric layer sidewall and Semiconductor substrate, the first side wall and control gate body structure surface and silicon nitride layer successively; Etch described silicon nitride layer and silicon oxide layer successively, form the second side wall of silicon oxide layer and silicon nitride layer laminated construction at floating boom and floating gate dielectric layer sidewall and the first side wall surface.
Optionally, the thickness range of described silicon oxide layer is 20 ~ 40 dusts.
Optionally, the thickness range of described silicon nitride layer is 90 ~ 110 dusts.
Optionally, the thickness range of described second side wall is 110 ~ 150 dusts.
Optionally, described first side wall is the laminated construction of silicon oxide layer and silicon nitride layer.
Optionally, the silicon oxide layer thickness range of described first side wall is 40 ~ 60 dusts, and silicon nitride layer thickness range is 90 ~ 110 dusts.
Optionally, described second polysilicon layer surface is also formed with hard mask layer.
Optionally, the method for described formation tunnel oxide is low-pressure chemical vapor deposition process.
Optionally, the thickness range of described tunnel oxide is 110 ~ 150 dusts.
Optionally, the thickness range of described first medium layer is 80 ~ 100 dusts.
Optionally, the thickness range of described first polysilicon layer is 300 ~ 500 dusts.
Optionally, the thickness range of described second dielectric layer is 140 ~ 160 dusts.
Optionally, the thickness range of described second polysilicon layer is 500 ~ 900 dusts.
Optionally, before described formation wordline, also comprise, form wordline oxide layer with floating boom relative in the Semiconductor substrate of the second opening side far away at control gate.
Optionally, also comprise, in the Semiconductor substrate of wordline away from erase gate side, form drain region.
Present invention also offers a kind of Split-gate flash memory, comprising:
Semiconductor substrate; Be positioned at the erase gate in Semiconductor substrate; Tunnel oxide between Semiconductor substrate and erase gate, described tunnel oxide layer segment is positioned in Semiconductor substrate, and part is positioned at the sidewall of erase gate; Be positioned at the source region that Semiconductor substrate is relative with erase gate; Be positioned at the floating gate structure in the Semiconductor substrate of erase gate both sides and control gate build stack, described floating gate structure comprises the floating gate dielectric layer being positioned at semiconductor substrate surface and the floating boom being positioned at floating gate dielectric layer surface, and described control gate structure comprises the control gate dielectric layer being positioned at floating boom surface and the control gate being positioned at control gate dielectric layer surface; Be positioned at the first side wall of control gate structure both sides sidewall on floating boom; Be positioned at second side wall of floating gate structure away from erase gate side sidewall and the first side wall surface, described second side wall is the laminated construction of silicon oxide layer and silicon nitride layer; Be positioned at the second side wall away from the wordline in the Semiconductor substrate of erase gate side; Wordline oxide layer between wordline and Semiconductor substrate; Be positioned at the drain region of wordline away from erase gate side Semiconductor substrate.
Optionally, the thickness range of the silicon oxide layer of described second side wall is 20 ~ 40 dusts.
Optionally, the thickness range of the silicon nitride layer of described second side wall is 90 ~ 110 dusts.
Optionally, the thickness range of described second side wall is 110 ~ 150 dusts.
Optionally, described first side wall is the laminated construction of silicon oxide layer and silicon nitride layer.
Optionally, described control gate surface also has hard mask layer.
Compared with prior art, technical solution of the present invention has the following advantages:
Form the second side wall of silicon oxide layer and silicon nitride layer laminated construction, the surface of the second side wall is silicon nitride spacer, when follow-up formation tunnel oxide and wordline oxide layer, because etching solution hydrofluoric acid has high etching selection ratio to silicon oxide layer and silicon nitride layer, the thickness of the second side wall can not be made to reduce or make the second side wall surface irregularity, improve the uniformity on the second side wall surface, follow-up when forming wordline in the Semiconductor substrate of the second side wall away from erase gate side, gap (gap) between wordline and floating boom is filled by uniform second side wall, when programming to a point grid memory, the electronics of channel region transits in the process in floating boom via gap, the transverse electric field that second side wall can not make program voltage be applied to gap changes, second side wall reduces the impact of program current, improve the uniformity of program current, thus improve efficiency and the uniformity of programming, in addition, the second side wall improves the isolation effect between control gate and wordline, improves the puncture voltage between control gate and wordline,
Further, the thickness range of the second side wall is 110 ~ 150 dusts, improve uniformity and the efficiency of programming, the too thick distance by the channel region made below follow-up formation wordline and floating boom of second side wall thicknesses becomes large, because the Semiconductor substrate bottom the second side wall is not conducting, when programming to memory device, when floating boom applies identical program voltage, the transition potential energy change of floating boom is transitted to greatly from channel region by making electronics, be unfavorable for the injection of electronics to floating boom of channel region, reduce size and the uniformity of program current, reduce efficiency and the uniformity of programming, when especially multiple memory cell being programmed, this impact is particularly serious, the words that second side wall thicknesses is too thin, the lateral separation of channel region and floating boom reduces, when programming, the transverse electric field that program voltage is applied to interstitial area between channel region and floating boom increases, be unfavorable for the injection of electronics to floating boom of channel region, reduce the size of program current, reduce efficiency and the uniformity of programming, when especially programming to multiple memory cell, this impact is particularly serious.
Accompanying drawing explanation
The cross-sectional view of the existing Split-gate flash memory of Fig. 1;
Fig. 2 is the schematic flow sheet of embodiment of the present invention Split-gate flash memory formation method;
Fig. 3 ~ Fig. 9 is the cross-sectional view of embodiment of the present invention Split-gate flash memory forming process.
Embodiment
With reference to figure 1, when existing Split-gate flash memory is programmed, positive voltage is applied at control gate 103, wordline 104 applies operating voltage makes the channel region of below open, drain region (not shown) applies negative voltage, source region (not shown) ground connection, when the voltage of control gate 103 is greater than drain region (not shown) voltage, the electrons in conducting channel is accelerated and transits to floating boom 102 from channel region by the gap (gap) 10 between wordline 104 and floating boom 102.
Inventor finds, fill efficiency and uniformity positive correlation that the uniformity of the side wall 107 in gap 10 between wordline 104 and floating boom 102 and Split-gate flash memory carry out programming, side wall uniformity can affect the uniformity of program current, the uniformity of program current and the efficiency of programming and uniformity positive correlation, the uniformity of side wall 107 is better, the uniformity of program current is higher, and efficiency and the uniformity of programming are higher.
Inventor studies discovery further, in the existing process making Split-gate flash memory, the material of the side wall 107 formed is the single layer structure of silica, and silica is easily damaged in subsequent wet etching technics, reduces thickness and the surface uniformity of side wall 107.
For solving the problem, inventor proposes a kind of Split-gate flash memory and forming method thereof, Split-gate flash memory formation method comprises: provide Semiconductor substrate, and described semiconductor substrate surface is formed with first medium layer, the first polysilicon layer, second dielectric layer and the second polysilicon layer successively; Etch described second polysilicon layer and second dielectric layer and form two discrete control gate structures, have the first opening between two control gate structures, described control gate structure comprises control gate dielectric layer and is positioned at the control gate on control gate dielectric layer; The first side wall is formed at the sidewall of control gate structure both sides; With described control gate structure and the first side wall for mask, etch described first polysilicon layer and first medium layer, form floating boom and floating gate dielectric layer and the second opening between two floating booms; Form the second side wall at floating boom and floating gate dielectric layer sidewall and the first side wall surface, described second side wall is the laminated construction of silicon oxide layer and silicon nitride layer; Along the second opening, ion implantation is carried out to Semiconductor substrate, form source region; Remove the second side wall of the second opening sidewalls, form tunnel oxide at the second opening sidewalls and bottom; In the second opening, form erase gate, at control gate and floating boom, the Semiconductor substrate away from erase gate side forms wordline.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.
With reference to the schematic flow sheet that figure 2, Fig. 2 is Split-gate flash memory formation method of the present invention, comprising:
Step S201, provides Semiconductor substrate, and described semiconductor substrate surface is formed with first medium layer, the first polysilicon layer, second dielectric layer, the second polysilicon layer and hard mask layer successively;
Step S202, etch described hard mask layer, the second polysilicon layer and second dielectric layer and form two discrete control gate structures, have the first opening between two control gate structures, described control gate structure comprises control gate dielectric layer and is positioned at the control gate on control gate dielectric layer;
Step S203, forms the first side wall at the sidewall of control gate structure both sides;
Step S204, with described control gate structure and the first side wall for mask, etches described first polysilicon layer and first medium layer, forms floating boom and floating gate dielectric layer and the second opening between two floating booms;
Step S205, form the second side wall at floating boom and floating gate dielectric layer sidewall and the first side wall surface, described second side wall is the laminated construction of silicon oxide layer and silicon nitride layer;
Step S206, carries out ion implantation along the second opening to Semiconductor substrate, forms source region;
Step S207, removes the second side wall of the second opening sidewalls, forms tunnel oxide at the second opening sidewalls and bottom;
Step S208, forms erase gate in the second opening, at control gate and floating boom, the Semiconductor substrate away from erase gate side forms wordline;
Step S209, forms drain region in the Semiconductor substrate of wordline away from erase gate side.
Fig. 3 ~ Fig. 9 is the cross-sectional view of embodiment of the present invention Split-gate flash memory forming process.
With reference to figure 3, provide Semiconductor substrate 300, described Semiconductor substrate 300 surface is formed with first medium layer 301, first polysilicon layer 302, second dielectric layer 303, second polysilicon layer 304 and hard mask layer 305 successively.
Described Semiconductor substrate 300 can be silicon or the SiGe of monocrystalline, polycrystalline or non crystalline structure, also can be silicon-on-insulator (SOI).Or other material can also be comprised, such as GaAs etc. three or five compounds of group
Described first medium layer 301 is for the formation of follow-up floating gate dielectric layer, the material of described first medium layer 301 is silica, thickness range is 80 ~ 100 dusts, the formation process of first medium layer 301 is boiler tube thermal oxidation technology, atom layer deposition process (ALD), chemical vapor deposition method (CVD) or plasma enhanced chemical vapor deposition processes (PECVD), the present embodiment adopts boiler tube thermal oxidation technology.
Described first polysilicon layer 302 is for follow-up formation floating boom, and the thickness range of described first polysilicon layer 302 is 300 ~ 500 dusts, and formation process is chemical vapor deposition method (CVD) or low-pressure chemical vapor deposition process (LPCVD).
Described second dielectric layer 303 is silica structure or the laminated construction for oxide-nitride-oxide (ONO).Second dielectric layer 303 described in the present embodiment is the laminated construction of oxide-nitride-oxide (ONO).The thickness range of described second dielectric layer 303 is 140 ~ 160 dusts.
Described second polysilicon layer 304 is for follow-up formation control grid, the thickness range of described second polysilicon layer 304 is 500 ~ 900 dusts, and formation process is chemical vapor deposition method (CVD) or low-pressure chemical vapor deposition process (LPCVD).
The material of described hard mask layer 305 is silicon nitride, and thickness range is 800 ~ 1200 dusts, and described hard mask layer 305 is as polish stop layer when formation erase gate and wordline.
With reference to figure 4, hard mask layer 305, second polysilicon layer 304 of etching shown in Fig. 3 and second dielectric layer 303 form two discrete control gate knots 30, there is the first opening 308, the control gate 307 that described control gate structure 30 comprises control gate dielectric layer 306 and is positioned on control gate dielectric layer 306 between two control gate structures 30.
Particularly, described etching adopts dry etching, and described dry etching adopts reactive ion etching, and process gas used is mainly fluoro-gas.
With reference to figure 5, form the first side wall 309 at the sidewall of control gate structure 30 both sides.
Described first side wall 309 is the laminated construction of silicon oxide layer and silicon nitride layer, comprise monox lateral wall 309a and silicon nitride spacer 309b, outside being exposed to is silicon nitride spacer 309b, and the silicon oxide layer thickness range of described first side wall is 40 ~ 60 dusts, and silicon nitride layer thickness range is 90 ~ 110 dusts.The concrete forming process of described first side wall 309 is: adopt depositing operation to be formed successively to cover Semiconductor substrate 300, the silicon oxide layer of hard mask layer 305 surface and control gate structure 30 sidewall and silicon nitride layer (not shown); Etch described silicon nitride layer and silicon oxide layer successively, form monox lateral wall 309a and silicon nitride spacer 309b, described monox lateral wall 309a in " L " type, described silicon nitride spacer 309b is positioned at " L " type surface of monox lateral wall 309a.Etch described silicon nitride layer and silicon oxide layer carries out in same etching machine bench, adopt dry etch process.
Dry etch process is adopted to the etching of silicon nitride layer and silicon oxide layer, carry out in same etching machine bench, form the first side wall 309, avoid and form at different etching board or different etching technique etch nitride silicon layer and silicon oxide layer the dimensional discrepancy that the first side wall 309 causes, the surface of the first side wall 309 is silicon nitride spacer 309b, during the second side wall avoiding follow-up hydrofluoric acid to remove in the second opening, to the damage of the first side wall 309, ensure that the uniformity on the first side wall 309 surface, improve the equal of the tunnel oxide of follow-up formation and property, improve the stability of Split-gate flash memory, silicon nitride spacer 309b improves the isolation performance between the erase gate of follow-up formation and control gate 307 in addition, improve puncture voltage.
With reference to figure 6, with described control gate structure 30 and the first side wall 309 for mask, etch described first polysilicon layer 302 and first medium layer 301 (shown in Fig. 5), form floating boom 311 and floating gate dielectric layer 310 and the second opening 312 between two floating booms 311, floating boom 311 and floating gate dielectric layer 310 form floating gate structure 40.
Particularly, described etching adopts dry etching, and described dry etching adopts reactive ion etching, and process gas used is mainly fluoro-gas.
With reference to figure 7, form the second side wall 313 at floating boom 311 and floating gate dielectric layer 310 sidewall and the first side wall 309 surface, described second side wall 313 be the laminated construction of silicon oxide layer and silicon nitride layer, and being exposed to outer is silicon nitride layer; Carry out ion implantation along the second opening 312 pairs of Semiconductor substrate 300, form source region 314.
Described second side wall 313 is the laminated construction of silicon oxide layer and silicon nitride layer, outside being exposed to is silicon nitride layer, concrete described second side wall 313 comprises monox lateral wall 313a and silicon nitride spacer 313b, being exposed to outer is silicon nitride spacer 313b, and the process that described second side wall 313 is formed is: adopt depositing operation to be formed successively to cover hard mask layer 305, the silicon oxide layer of Semiconductor substrate 300, first side wall 309 surface and floating boom 311 and floating gate dielectric layer 310 sidewall and silicon nitride layer (not shown); Etch described silicon nitride layer and silicon oxide layer successively, form monox lateral wall 313a and silicon nitride spacer 313b, described monox lateral wall 313a in " L " type, described silicon nitride spacer 313b is positioned at " L " type surface of monox lateral wall 313a.Etch described silicon nitride layer and silicon oxide layer carries out in same etching machine bench, adopt dry etch process.The thickness range of described silicon oxide layer is 20 ~ 40 dusts, the thickness range of described silicon nitride layer is 90 ~ 110 dusts, second side wall 313 thickness range of the laminated construction of silicon oxide layer and silicon nitride layer is 110 ~ 150 dusts, the thickness of silicon oxide layer described in the embodiment of the present invention is 30 dusts, the thickness of described silicon nitride layer is 100 dusts, and the second side wall 313 thickness of the laminated construction of silicon oxide layer and silicon nitride layer is 130 dusts.
The too thick distance by the channel region made below follow-up formation wordline and floating boom 311 of second side wall 313 thickness becomes large, Semiconductor substrate 300 bottom second side wall 313 is not conductings, when programming to memory device, when floating boom 311 applies identical program voltage, the transition potential energy change of floating boom 311 is transitted to greatly from channel region by making electronics, be unfavorable for the injection of the electronics of channel region to floating boom 311, reduce size and the uniformity of program current, reduce efficiency and the uniformity of programming, when especially multiple memory cell being programmed, this impact is particularly serious, the words that second side wall 313 thickness is too thin, the lateral separation of channel region and floating boom 311 reduces, when programming, the transverse electric field that program voltage is applied to interstitial area between channel region and floating boom 311 increases, be unfavorable for the injection of the electronics of channel region to floating boom 311, reduce the size of program current, reduce efficiency and the uniformity of programming, when especially programming to multiple memory cell, this impact is particularly serious.
When forming the second side wall 313, etch described silicon nitride layer and silicon oxide layer carries out in same etching machine bench, adopt dry etch process, avoid and form at different etching equipment or different etching technique etch nitride silicon layer and silicon oxide layer the dimensional discrepancy that the second side wall 313 causes, improve the uniformity of the second side wall 313, the surface of the second side wall 313 is silicon nitride spacer 313b, when avoiding follow-up formation tunnel oxide and wordline oxide layer, etching solution hydrofluoric acid is to the damage of the second side wall 313, the thickness of the second side wall 313 can not be made to reduce or make the second side wall 313 surface element smooth, further ensure the uniformity on the second side wall 313 surface, follow-up at the second side wall 313 away from when the Semiconductor substrate 300 of erase gate side forms wordline, gap (gap) between wordline and floating boom 311 is filled by uniform second side wall 313, when programming to a point grid memory, the electronics of channel region transits in the process in floating boom 311 via gap, second side wall 313 reduces the impact of program current, improve the uniformity of program current, thus improve the uniformity of the efficiency of programming.
Second side wall 313 covers the first side wall 309 surface, is the laminated construction of silicon oxide layer and silicon nitride layer, further increases the isolation effect of the wordline of control gate 307 and follow-up formation, improve the puncture voltage between control gate 307 and wordline.
After formation second side wall 313, with described control gate structure 30 and the second side wall 313 for mask, ion implantation is carried out along the second opening 312 pairs of Semiconductor substrate 300, form source region 314, concrete process is: form the photoresist layer (not shown) covering described Semiconductor substrate 300, hard mask layer 305 and the second side wall 313 surface, graphical described photoresist layer, described patterned photoresist layer exposes opening 312 and is positioned at opening 312 second side wall 313; With the second side wall 313 in described patterned photoresist layer and opening 312 for mask, ion implantation is carried out to the Semiconductor substrate 300 in opening 312, and carries out annealing process, activate Doped ions, form source region 314.
With reference to figure 8, remove the second side wall 313 of the second opening 312 sidewall shown in Fig. 7, form tunnel oxide 315 at the second opening 312 sidewall and bottom.
The second side wall 313 removing the second opening 312 sidewall adopts wet-etching technology, detailed process is: continue to adopt the patterned photoresist layer formed when forming source region 314 to be mask (not shown), first hot phosphoric acid solution is adopted to etch the silicon nitride spacer 313b of the second side wall 313, then adopt the hydrofluoric acid solution of dilution to etch the monox lateral wall 313a of the second side wall 313, remove described patterned photoresist layer.The hydrofluoric acid solution of dilution is adopted when etching the monox lateral wall 313a of the second side wall 313, outside due to the first side wall 309 is silicon nitride spacer 309b, the hydrofluoric acid of dilution has high etching selection ratio to silica and silicon nitride, therefore can not cause damage to the first side wall 309 during etching, in addition, in this step, do not need again to form mask layer, save processing step.
The formation process of described tunnel oxide 315 is low-pressure chemical vapor deposition process (LPCVD), the quality of the film that low-pressure chemical vapor deposition process (LPCVD) is formed is better, and the thickness of described tunnel oxide 315 is 110 ~ 150 dusts.
The process forming described tunnel oxide 315 is: form the tunnel oxide (not shown) covering described Semiconductor substrate 300, second side wall 313, hard mask layer 305 surface; Form patterned photoresist layer on described tunnel oxide surface, described patterned photoresist layer exposes the tunnel oxide except the second opening 312 sidewall and bottom; Employing hydrofluoric acid solution removes the tunnel oxide outside the second opening 312 sidewall and bottom, forms tunnel oxide 315 at the second opening 312 sidewall and bottom; Remove described patterned photoresist layer.When adopting hydrofluoric acid solution to remove the tunnel oxide outside the second opening 312 sidewall and bottom, the outside of the second side wall 313 is silicon nitride spacer 313b, because hydrofluoric acid solution has high etching selection ratio to silica and silicon nitride, when removing tunnel oxide, can not cause damage to silicon nitride spacer 313b, the thickness of the second side wall 313 can not be made to reduce or make the second side wall 313 surface element smooth, improve the uniformity of the second side wall 313, follow-up at the second side wall 313 away from when the Semiconductor substrate 300 of erase gate side forms wordline, gap (gap) between wordline and floating boom 311 is filled by uniform second side wall 313, when programming to a point grid memory, the electronics of channel region transits in the process in floating boom 311 via gap, second side wall 313 reduces the impact of program current, improve the uniformity of program current, thus improve the uniformity of the efficiency of programming.
With reference to figure 9, in the second opening shown in Fig. 8, fill full polysilicon layer form erase gate 316, at control gate 307 and floating boom 311, the Semiconductor substrate 300 away from erase gate 316 side forms wordline 317.
Described erase gate 316 and wordline 317 can be formed simultaneously, also can separately be formed.
Wordline oxide layer 318 is also formed between described wordline 317 and Semiconductor substrate 300.
Described wordline 317 is also formed with the drain region (not shown) of Split-gate flash memory away from the Semiconductor substrate 300 of erase gate 316 side.
The embodiment of the present invention additionally provides a kind of Split-gate flash memory, with reference to figure 9, comprising: Semiconductor substrate 300; Be positioned at the erase gate 316 in Semiconductor substrate 300; Tunnel oxide 315 between Semiconductor substrate 300 and erase gate 316, described tunnel oxide 315 part is positioned in Semiconductor substrate 300, and part is positioned at the sidewall of erase gate 316; Be positioned at Semiconductor substrate 300 source region relative with erase gate 316 314; Be positioned at floating gate structure 40 in the Semiconductor substrate of erase gate 316 both sides and control gate structure 30 stacking, described floating gate structure 40 comprises the floating gate dielectric layer 310 being positioned at Semiconductor substrate 300 surface and the floating boom 311 being positioned at floating gate dielectric layer 310 surface, and described control gate structure 40 comprises the control gate dielectric layer 306 being positioned at floating boom 311 surface and the control gate 307 being positioned at control gate dielectric layer 306 surface; Be positioned at the hard mask layer 305 on control gate 307 surface; Be positioned at the first side wall 309 of control gate structure 30 and hard mask layer 305 both sides sidewall on floating boom 311, described first side wall 309 is the stacked structure of silicon oxide layer and silicon nitride layer, and described first side wall 309 comprises monox lateral wall 309a and is positioned at the silicon nitride spacer 309b on monox lateral wall 309a surface; Be positioned at second side wall 313 of floating gate structure 40 away from erase gate 316 side sidewall and the first side wall 309 surface, described second side wall 313 is the laminated construction of silicon oxide layer and silicon nitride layer, and the second side wall 313 comprises monox lateral wall 313a and is positioned at the silicon nitride spacer 313b on monox lateral wall 313a surface; Be positioned at the second side wall 313 away from the wordline 317 in the Semiconductor substrate 300 of erase gate 316 side; Wordline oxide layer 318 between wordline 317 and Semiconductor substrate 300; Be arranged in the drain region (figure for illustrate) of wordline 317 away from erase gate 316 side Semiconductor substrate 300.
To sum up, Split-gate flash memory that the embodiment of the present invention provides and forming method thereof, form the second side wall of silicon oxide layer and silicon nitride layer laminated construction, the surface of the second side wall is silicon nitride spacer, when follow-up formation tunnel oxide and wordline oxide layer, because etching solution hydrofluoric acid has high etching selection ratio to silicon oxide layer and silicon nitride layer, the thickness of the second side wall can not be made to reduce or make the second side wall surface irregularity, improve the uniformity on the second side wall surface, follow-up when forming wordline in the Semiconductor substrate of the second side wall away from erase gate side, gap (gap) between wordline and floating boom is filled by uniform second side wall, when programming to a point grid memory, the electronics of channel region transits in the process in floating boom via gap, the transverse electric field that second side wall can not make program voltage be applied to gap changes, second side wall reduces the impact of program current, improve the uniformity of program current, thus improve efficiency and the uniformity of programming, in addition, the second side wall improves the isolation effect between control gate and wordline, improves the puncture voltage between control gate and wordline.
Further, the thickness range of the second side wall is 110 ~ 150 dusts, improve uniformity and the efficiency of programming, the too thick distance by the channel region made below follow-up formation wordline and floating boom of second side wall thicknesses becomes large, because the Semiconductor substrate bottom the second side wall is not conducting, when programming to memory device, when floating boom applies identical program voltage, the transition potential energy change of floating boom is transitted to greatly from channel region by making electronics, be unfavorable for the injection of electronics to floating boom of channel region, reduce size and the uniformity of program current, reduce efficiency and the uniformity of programming, when especially multiple memory cell being programmed, this impact is particularly serious, the words that second side wall thicknesses is too thin, the lateral separation of channel region and floating boom reduces, when programming, the transverse electric field that program voltage is applied to interstitial area between channel region and floating boom increases, be unfavorable for the injection of electronics to floating boom of channel region, reduce the size of program current, reduce efficiency and the uniformity of programming, when especially programming to multiple memory cell, this impact is particularly serious.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Claims (22)
1. a formation method for Split-gate flash memory, is characterized in that, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with first medium layer, the first polysilicon layer, second dielectric layer and the second polysilicon layer successively;
Etch described second polysilicon layer and second dielectric layer and form two discrete control gate structures, have the first opening between two control gate structures, described control gate structure comprises control gate dielectric layer and is positioned at the control gate on control gate dielectric layer;
The first side wall is formed at the sidewall of control gate structure both sides;
With described control gate structure and the first side wall for mask, etch described first polysilicon layer and first medium layer, form floating boom and floating gate dielectric layer and the second opening between two floating booms;
Form the second side wall at floating boom and floating gate dielectric layer sidewall and the first side wall surface, described second side wall is the laminated construction of silicon oxide layer and silicon nitride layer;
Along the second opening, ion implantation is carried out to Semiconductor substrate, form source region;
Remove the second side wall of the second opening sidewalls, form tunnel oxide at the second opening sidewalls and bottom, the forming process of described tunnel oxide is: form the tunnel oxide away from the second side wall on the second opening side sidewall, hard mask layer surface covering described Semiconductor substrate, control gate structure; Form patterned photoresist layer on described tunnel oxide surface, described patterned photoresist layer exposes the tunnel oxide except the second opening sidewalls and bottom; Employing hydrofluoric acid solution removes the tunnel oxide outside the second opening sidewalls and bottom, forms tunnel oxide at the second opening sidewalls and bottom; Remove described patterned photoresist layer;
In the second opening, form erase gate, at control gate and floating boom, the Semiconductor substrate away from erase gate side forms wordline.
2. the formation method of Split-gate flash memory as claimed in claim 1, it is characterized in that, the formation method of described second side wall is: form the silicon oxide layer covering floating boom and floating gate dielectric layer sidewall and Semiconductor substrate, the first side wall and control gate body structure surface and silicon nitride layer successively; Etch described silicon nitride layer and silicon oxide layer successively, form the second side wall of silicon oxide layer and silicon nitride layer laminated construction at floating boom and floating gate dielectric layer sidewall and the first side wall surface.
3. the formation method of Split-gate flash memory as claimed in claim 2, it is characterized in that, the thickness range of described silicon oxide layer is 20 ~ 40 dusts.
4. the formation method of Split-gate flash memory as claimed in claim 2, it is characterized in that, the thickness range of described silicon nitride layer is 90 ~ 110 dusts.
5. the formation method of Split-gate flash memory as claimed in claim 2, it is characterized in that, the thickness range of described second side wall is 110 ~ 150 dusts.
6. the formation method of Split-gate flash memory as claimed in claim 1, it is characterized in that, described first side wall is the laminated construction of silicon oxide layer and silicon nitride layer.
7. the formation method of Split-gate flash memory as claimed in claim 6, it is characterized in that, the silicon oxide layer thickness range of described first side wall is 40 ~ 60 dusts, and silicon nitride layer thickness range is 90 ~ 110 dusts.
8. the formation method of Split-gate flash memory as claimed in claim 1, it is characterized in that, described second polysilicon layer surface is also formed with hard mask layer.
9. the formation method of Split-gate flash memory as claimed in claim 1, it is characterized in that, the method for described formation tunnel oxide is low-pressure chemical vapor deposition process.
10. the formation method of Split-gate flash memory as claimed in claim 1, it is characterized in that, the thickness range of described tunnel oxide is 110 ~ 150 dusts.
The formation method of 11. Split-gate flash memory as claimed in claim 1, is characterized in that, the thickness range of described first medium layer is 80 ~ 100 dusts.
The formation method of 12. Split-gate flash memory as claimed in claim 1, is characterized in that, the thickness range of described first polysilicon layer is 300 ~ 500 dusts.
The formation method of 13. Split-gate flash memory as claimed in claim 1, is characterized in that, the thickness range of described second dielectric layer is 140 ~ 160 dusts.
The formation method of 14. Split-gate flash memory as claimed in claim 1, is characterized in that, the thickness range of described second polysilicon layer is 500 ~ 900 dusts.
The formation method of 15. Split-gate flash memory as claimed in claim 1, is characterized in that, before described formation wordline, also comprise, and forms wordline oxide layer at control gate with floating boom relative in the Semiconductor substrate of the second opening side far away.
The formation method of 16. Split-gate flash memory as claimed in claim 1, is characterized in that, also comprise, in the Semiconductor substrate of wordline away from erase gate side, form drain region.
17. 1 kinds of Split-gate flash memory, is characterized in that, comprising:
Semiconductor substrate; Be positioned at the erase gate in Semiconductor substrate; Tunnel oxide between Semiconductor substrate and erase gate, described tunnel oxide layer segment is positioned in Semiconductor substrate, and part is positioned at the sidewall of erase gate; Be positioned at the source region that Semiconductor substrate is relative with erase gate; Be positioned at the floating gate structure in the Semiconductor substrate of erase gate both sides and control gate build stack, described floating gate structure comprises the floating gate dielectric layer being positioned at semiconductor substrate surface and the floating boom being positioned at floating gate dielectric layer surface, and described control gate structure comprises the control gate dielectric layer being positioned at floating boom surface and the control gate being positioned at control gate dielectric layer surface; Be positioned at the first side wall of control gate structure both sides sidewall on floating boom; Be positioned at second side wall of floating gate structure away from erase gate side sidewall and the first side wall surface, described second side wall is the laminated construction of silicon oxide layer and silicon nitride layer, when described second side wall avoids and forms tunnel oxide and wordline oxide layer, etching solution hydrofluoric acid is to the damage of the second side wall; Be positioned at the second side wall away from the wordline in the Semiconductor substrate of erase gate side; Wordline oxide layer between wordline and Semiconductor substrate; Be positioned at the drain region of wordline away from erase gate side Semiconductor substrate.
18. Split-gate flash memory as claimed in claim 17, is characterized in that, the thickness range of the silicon oxide layer of described second side wall is 20 ~ 40 dusts.
19. Split-gate flash memory as claimed in claim 17, is characterized in that, the thickness range of the silicon nitride layer of described second side wall is 90 ~ 110 dusts.
20. Split-gate flash memory as claimed in claim 17, is characterized in that, the thickness range of described second side wall is 110 ~ 150 dusts.
21. Split-gate flash memory as claimed in claim 17, it is characterized in that, described first side wall is the laminated construction of silicon oxide layer and silicon nitride layer.
22. Split-gate flash memory as claimed in claim 17, it is characterized in that, described control gate surface also has hard mask layer.
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| CN104091803A (en) * | 2014-07-24 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Split gate memory, semiconductor device and method for making semiconductor device |
| CN106206445B (en) * | 2015-04-29 | 2019-07-30 | 中芯国际集成电路制造(上海)有限公司 | The forming method of memory construction |
| CN105336705B (en) * | 2015-12-04 | 2018-06-26 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of flash memory structure |
| CN106129060B (en) * | 2016-08-30 | 2019-05-03 | 武汉新芯集成电路制造有限公司 | A kind of floating gate type flash memory and preparation method thereof |
| US10586705B2 (en) * | 2017-11-28 | 2020-03-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fluorine doped non-volatile memory cells and methods for forming the same |
| CN108039323B (en) * | 2017-12-13 | 2019-05-31 | 武汉新芯集成电路制造有限公司 | The production method and integrated circuit of floating gate type flash memory |
| CN109659237B (en) * | 2019-01-02 | 2021-10-26 | 上海华虹宏力半导体制造有限公司 | Forming method of flash memory device |
| CN113517295A (en) * | 2020-04-10 | 2021-10-19 | 合肥晶合集成电路股份有限公司 | Preparation method of nonvolatile memory |
| CN111524810A (en) * | 2020-04-30 | 2020-08-11 | 华虹半导体(无锡)有限公司 | Flash memory device and method of manufacturing the same |
| CN111987105B (en) * | 2020-09-29 | 2023-09-08 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split gate type memory |
| CN112185973B (en) * | 2020-10-27 | 2024-05-24 | 上海华虹宏力半导体制造有限公司 | Memory, manufacturing method and operation method of memory |
| CN112750790B (en) * | 2021-01-22 | 2023-11-21 | 上海华虹宏力半导体制造有限公司 | Flash memory and method for manufacturing the same |
| CN112750789B (en) * | 2021-01-22 | 2024-02-06 | 上海华虹宏力半导体制造有限公司 | Split gate flash memory and preparation method thereof |
| CN112908856B (en) * | 2021-03-09 | 2024-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory device |
| CN113192959B (en) * | 2021-04-27 | 2023-11-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split gate type flash memory |
| CN113903789B (en) * | 2021-09-29 | 2024-05-28 | 上海华虹宏力半导体制造有限公司 | Flash memory, manufacturing method and operating method thereof |
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