CN103178018A - Method for manufacturing separation gate quick-flashing memory unit - Google Patents
Method for manufacturing separation gate quick-flashing memory unit Download PDFInfo
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- CN103178018A CN103178018A CN2011104359236A CN201110435923A CN103178018A CN 103178018 A CN103178018 A CN 103178018A CN 2011104359236 A CN2011104359236 A CN 2011104359236A CN 201110435923 A CN201110435923 A CN 201110435923A CN 103178018 A CN103178018 A CN 103178018A
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Abstract
The invention provides a method for manufacturing separation gate quick-flashing memory unit. A step of etching a floating gate polycrystalline silicon is divided into two steps, the floating gate polycrystalline silicon at the bottom of a second groove (corresponding to a word line) is first etched, then floating gate side wall oxidation layers are formed on a first groove (corresponding to an erasure gate) and on a side wall of the second groove, and finally etching of the floating gate polycrystalline silicon at the bottom of a first groove is performed. Due to the fact that the floating gate side wall oxidation layer generated on the side wall of the first groove blocks the etching of the floating gate polycrystalline silicon under the floating gate side wall oxidation layers when the etching of the floating gate polycrystalline silicon at the bottom of the first groove is performed, and, and the part of blocked floating gate polycrystalline silicon forms a convex top corner after etched. Therefore, the convex top corner of the floating gate polycrystalline silicon can be achieved without an additional sacrificial layer, a technical process is simplified, and the cost is further reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of manufacture method of separate gate flash memory unit.
Background technology
Representative instance with nonvolatile semiconductor memory member of electricity programming and erase feature is flash (Flash memory) unit.Flash memory cell can be classified as stacking (stack) structure and separate gate (split gate) structure.after the flash memory cell of stacked structure easily appears at repeatedly repeatedly the write/erase circulation, the unit threshold values may be changed, it is the excessive problem of erase feature, and separate gate can be good at overcoming this problem, a typical separate gate flash memory unit as shown in Figure 1, comprise the semiconductor base 100 with source electrode 111 and drain electrode (not shown), be formed on floating gate oxide layers 101 on semiconductor base 100 in the mode of storehouse successively, floating boom 102, between grid, dielectric layer 103, control gate 104, control gate silicon nitride layer 105, control gate silicon oxide layer 106, control gate hard mask layer 107, also comprise the control gate side wall layer 108 that is formed on control gate 104 both sides, the sidewall oxide 109 of control gate side wall layer 108 surfaces that form and floating boom 102 both sides, be formed with erase gate tunnel oxide 113 on source electrode 111, be formed with erase gate 121 on erase gate tunnel oxide 113, be formed with word line 122 in drain electrode.
When separate gate flash memory unit is carried out data write operation, apply a high positively biased and be pressed on control gate, make hot electron pass oxide layer and inject floating boom from source electrode, programming time is generally the microsecond rank; When separate gate flash memory is carried out data erase, apply high negative bias and be pressed on control gate, make the hot electron that is injected into floating boom utilize Fowler-Nordheim (Fowler-Nordheim, FN) tunneling effect, pass sidewall oxide and flow into source electrode.Be subject to the impact of FN tunneling effect due to the erasing time, will be longer than programming time far away, sometimes even reach a millisecond rank, and the long erasing time has been limited the separate gate flash memory operating efficiency.
In order to solve long problem of separate gate flash memory unit erasing time, prior art is to be formed with the drift angle of protrusion in the side that floating boom closes on erase gate, the formation of drift angle can reduce the channel voltage of FN tunneling effect, make hot electron easier from floating boom inflow erase gate, and drift angle infiltrates in erase gate, be conducive to point discharge, can promote the electric current that in erase process, hot electron forms, further promote efficiency of erasing.In order to form above-mentioned structure, realize through following steps on technique, with reference to Fig. 2 a～Fig. 2 c, as shown in Fig. 3 a, forming successively dielectric layer 103, control gate 104, control gate silicon nitride layer 105, control gate silicon oxide layer 106, control gate hard mask layer 107 between floating gate oxide layers 101, floating boom 102, grid on semiconductor base 100, dielectric layer 103 between etching control gate hard mask layer 107, control gate silicon oxide layer 106, control gate silicon nitride layer 105, control gate 104, grid, to expose floating boom 102, formation control grid structure; In control gate 104 both sides formation control grid side wall layer 108, and at control gate side wall layer 108 surface formation sacrifice layers 201; As shown in Fig. 3 b, sacrifice layer 201 is in order to when the first interior formation photoresist 202 of groove 401, and as floating boom 102 being carried out the mask of Implantation, and etching is removed sacrifice layer 201 parts in the second groove 402 after injection; As shown in Fig. 3 c, after removing photoresist 202, carry out etching take the control gate side wall layer 108 of sacrifice layer 201 parts of control gate hard mask layer 107, the first recess sidewall 401 interior reservations, the second groove 402 sides as mask, and remove the first interior sacrifice layer 201 parts of groove 401, form the drift angle 102a that protrudes.
Utilize existing technique to generate in the drift angle process of protruding, need the steps such as the additional deposition that carry out sacrifice layer and etching, this can increase the complexity of technique undoubtedly, and then increases cost, is problem demanding prompt solution so simplify above-mentioned technical process.
Summary of the invention
The invention provides a kind of manufacture method of separate gate flash memory unit, solve the problem of separate gate flash memory unit complex process that has the drift angle floating boom of protrusion in making that has now.
The technological means that the present invention adopts is as follows: a kind of manufacture method of separate gate flash memory unit, comprise: semiconductor base is provided, is forming successively dielectric layer between floating gate oxide layers, floating gate polysilicon, grid, control gate polysilicon, control gate silicon nitride layer, control gate silicon oxide layer, control gate hard mask layer on described semiconductor base;
Form the first photoresist of patterning on described control gate hard mask layer, and take described the first photoresist as mask etching dielectric layer between described control gate hard mask layer, control gate silicon oxide layer, control gate silicon nitride layer, control gate polysilicon, grid, to expose floating gate polysilicon, form the first groove and the second groove, and the control gate structure between described the first groove and the second groove;
Remove described the first photoresist, in described control gate structure both sides formation control grid side wall layer;
Form the second photoresist in described the first groove, after take described the second photoresist as mask, the semiconductor base at the bottom of described the second groove being carried out Implantation formation drain electrode, etching is removed the floating gate polysilicon at the bottom of described the second groove;
Remove described the second photoresist, form the floating boom side wall layer on described the second groove and the first recess sidewall;
Floating gate polysilicon at the bottom of described the first groove of etching removal and the part floating gate oxide layers of the second groove
Form the erase gate tunnel oxide in described the first recess sidewall and bottom deposition;
Deposit spathic silicon forms erase gate on described erase gate tunnel oxide, and forms the word line in described the second groove.
Further, described control gate side wall layer is made of oxide-nitride thing composite bed.
Further, between described grid, dielectric layer is made of the composite bed of oxide-nitride thing-oxide.
in the manufacture method of a kind of separate gate flash memory unit provided by the invention, the step of etching floating gate polysilicon is divided into successively two step etchings, first etching is carried out in the floating gate polysilicon of the second groove (corresponding to the word line) bottom, then form the floating boom sidewall oxide on the first groove (corresponding to erase gate) and the second recess sidewall, last again the floating gate polysilicon of the first bottom portion of groove is carried out etching, due to when the floating gate polysilicon to the first bottom portion of groove carries out etching, the first recess sidewall generates the floating boom sidewall oxide, the floating boom sidewall oxide has stopped the etching that is positioned at the floating gate polysilicon under this floating boom sidewall oxide, this part floating gate polysilicon that is blocked has formed protrusion drift angle of the prior art after etching is completed.
Description of drawings
Fig. 1 is existing typical separate grid flash memory unit structure schematic diagram;
Fig. 2 a～2c closes on for the existing floating boom that forms the manufacturing process schematic diagram that erase gate one side has the protrusion drift angle;
Fig. 3 is the manufacture method flow chart of a kind of separate gate flash memory unit of the present invention;
Fig. 4 a～Fig. 4 f is the manufacture process schematic diagram of a kind of separate gate flash memory unit of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.
At first the present invention provides a kind of manufacture method of separate gate flash memory unit, as shown in Figure 3, comprises the steps:
Semiconductor base is provided, is forming successively dielectric layer between floating gate oxide layers, floating gate polysilicon, grid, control gate polysilicon, control gate silicon nitride layer, control gate silicon oxide layer, control gate hard mask layer on semiconductor base;
Form the first photoresist of patterning on the control gate hard mask layer, and take the first photoresist as mask etching dielectric layer between described control gate hard mask layer, control gate silicon oxide layer, control gate silicon nitride layer, control gate polysilicon, grid, to expose floating gate polysilicon, form a plurality of the first grooves and the second groove, and the control gate structure between described the first groove and the second groove;
Remove the first photoresist, in control gate structure both sides formation control grid side wall layer;
Form the second photoresist in the first groove, after take the second photoresist as mask, the floating gate polysilicon at the bottom of the second groove being carried out Implantation, the floating gate polysilicon at the bottom of etching the second groove;
Remove the second photoresist, form the floating boom side wall layer on the second groove and the first recess sidewall;
Floating gate polysilicon at the bottom of described the first groove of etching removal and the part floating gate oxide layers of the second groove;
Form the erase gate tunnel oxide in the first recess sidewall and bottom deposition;
Deposit spathic silicon forms erase gate on described erase gate tunnel oxide, and forms the word line in described the second groove.
Below in conjunction with accompanying drawing 4a～4f, above-mentioned manufacturing step is described in detail.
With reference to Fig. 4 a, semiconductor base 100 is provided, semiconductor base can be part of silicon chip, silicon-on-insulator substrate or integrated circuit and other elements etc., utilize existing technique, as chemical vapour deposition (CVD), forming successively dielectric layer 103, control gate polysilicon 104, control gate silicon nitride layer 105, control gate silicon oxide layer 106, control gate hard mask layer 107 between floating gate oxide layers 101, floating gate polysilicon 102, grid on semiconductor base 100.Wherein floating gate oxide layers 101 can be silicon oxide layer, and between grid, dielectric layer 103 is made of the composite bed of oxide-nitride thing-oxide (ONO) usually.
spin coating photoresist on the hard mask 107 of control gate, and graphically form the first photoresist (not shown), take the first photoresist as mask, adopt dry etching etching control gate hard mask layer 107, continue to adopt dry etching figure control gate silicon oxide layer 106 with the control gate hard mask layer 107 after the first photoresist and etching again, control gate silicon nitride layer 105, control gate 104, between grid, dielectric layer 103, to expose floating boom 102, formation control grid structure and the first groove 401 and the second groove 402, the control gate structure is between the first groove 401 and the second groove 402.
With reference to Fig. 4 b, remove the first photoresist, in control gate structure both sides formation control grid side wall layer 108, this control gate side wall layer 108 can be made of the composite bed of oxide-nitride thing (ON), and control gate side wall layer 108 has covered dielectric layer 103 between grid, control gate silicon nitride layer 105, control gate oxide layer 106 and control gate hard mask layer 107; At the first interior formation the second photoresist 202 of groove 401, take the second photoresist 202 as mask, the semiconductor base at second 402 ends of groove is carried out Implantation and form drain electrode 110, preferably increase the step of annealing so that the ion diffusion after Implantation.
As shown in Fig. 4 c, after the floating gate polysilicon to second 402 ends of groove carried out Implantation, 402 the floating gate polysilicon at the bottom of removal the second groove take the second photoresist 202 as mask etching still was to expose floating gate polysilicon oxide layer 101.
With reference to 4d, the second photoresist 202 is removed in ashing, form floating boom side wall layer 109 on the second groove 402 and the first groove 401 sidewalls, wherein, the floating boom side wall layer 109 of the first groove 401 side-walls has covered the control gate sidewall 108 of the first groove 401 side-walls, the floating boom side wall layer 109 of the second groove 402 side-walls has also covered floating gate polysilicon 102 edges after second groove 402 place's etchings except the control gate side wall layer 108 that has covered the second groove 402 side-walls.
As shown in Fig. 4 e, take floating boom side wall layer 109 as mask, dry etching is removed at the bottom of the floating gate polysilicon 102 at first 401 ends of groove and the second groove 402 part floating gate oxide layers 101, for fear of the impact of subsequent technique on substrate 100, to have kept a small amount of floating gate oxide layers 101, not shown in the drawings.
As shown in Fig. 4 f, the semiconductor base 100 at first 401 ends of groove is carried out Implantation form source electrode 111, form erase gate tunnel oxide 113 at the first groove 401 sidewalls and bottom deposition, deposit spathic silicon, and deposit spathic silicon forms erase gate 121 on erase gate tunnel oxide 113, at the second interior drain electrode 110 places formation of groove 402 word line 122.Can find out by Fig. 4 f, due to when the floating gate polysilicon 102 to the first groove 401 bottoms carries out etching, the floating boom sidewall oxide 109 that the first groove 401 sidewalls generate has stopped the etching that is positioned at the floating gate polysilicon 102 under this floating boom sidewall oxide 109, and this part floating gate polysilicon 102 that is blocked has formed protrusion drift angle 102a of the prior art after etching is completed.Therefore, method provided by the present invention, need not separately increases the protrusion drift angle that sacrifice layer can be realized floating gate polysilicon, has simplified technological process, and then has reduced cost.
The above is only preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (3)
1. the manufacture method of a separate gate flash memory unit, comprise,
Semiconductor base is provided, is forming successively dielectric layer between floating gate oxide layers, floating gate polysilicon, grid, control gate polysilicon, control gate silicon nitride layer, control gate silicon oxide layer, control gate hard mask layer on described semiconductor base;
Form the first photoresist of patterning on described control gate hard mask layer, and take described the first photoresist as mask etching dielectric layer between described control gate hard mask layer, control gate silicon oxide layer, control gate silicon nitride layer, control gate polysilicon, grid, to expose floating gate polysilicon, form the first groove and the second groove, and the control gate structure between described the first groove and the second groove;
Remove described the first photoresist, in described control gate structure both sides formation control grid side wall layer;
Form the second photoresist in described the first groove, after take described the second photoresist as mask, the semiconductor base at the bottom of described the second groove being carried out Implantation formation drain electrode, etching is removed the floating gate polysilicon at the bottom of described the second groove;
Remove described the second photoresist, form the floating boom side wall layer on described the second groove and the first recess sidewall;
Floating gate polysilicon at the bottom of described the first groove of etching removal and the part floating gate oxide layers of the second groove;
Form the erase gate tunnel oxide in described the first recess sidewall and bottom deposition;
Deposit spathic silicon forms erase gate on described erase gate tunnel oxide, and forms the word line in described the second groove.
2. method according to claim 1, is characterized in that, described control gate side wall layer is made of oxide-nitride thing composite bed.
3. method according to claim 1, is characterized in that, between described grid, dielectric layer is made of the composite bed of oxide-nitride thing-oxide.
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| CN2011104359236A CN103178018A (en) | 2011-12-22 | 2011-12-22 | Method for manufacturing separation gate quick-flashing memory unit |
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| CN2011104359236A CN103178018A (en) | 2011-12-22 | 2011-12-22 | Method for manufacturing separation gate quick-flashing memory unit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105470127A (en) * | 2014-09-12 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | Method to remove photoresist from deep groove and manufacturing method of flash memory |
| CN108807393A (en) * | 2017-05-05 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
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| US20030227047A1 (en) * | 2002-06-11 | 2003-12-11 | Cheng-Yuan Hsu | Split-gate flash memory structure and method of manufacture |
| CN1967811A (en) * | 2005-11-17 | 2007-05-23 | 茂德科技股份有限公司 | Separable grid flash memory cell and its forming method |
| CN101364614A (en) * | 2007-08-06 | 2009-02-11 | 美商矽储科技股份有限公司 | Non-volatile flash memory cell, array and method of manufacturing same |
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2011
- 2011-12-22 CN CN2011104359236A patent/CN103178018A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030227047A1 (en) * | 2002-06-11 | 2003-12-11 | Cheng-Yuan Hsu | Split-gate flash memory structure and method of manufacture |
| CN1967811A (en) * | 2005-11-17 | 2007-05-23 | 茂德科技股份有限公司 | Separable grid flash memory cell and its forming method |
| CN101364614A (en) * | 2007-08-06 | 2009-02-11 | 美商矽储科技股份有限公司 | Non-volatile flash memory cell, array and method of manufacturing same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105470127A (en) * | 2014-09-12 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | Method to remove photoresist from deep groove and manufacturing method of flash memory |
| CN105470127B (en) * | 2014-09-12 | 2018-11-09 | 上海华虹宏力半导体制造有限公司 | The production method for removing the method and flash memory of residual photoresist in deep trench |
| CN108807393A (en) * | 2017-05-05 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
| CN108807393B (en) * | 2017-05-05 | 2020-12-22 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
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Application publication date: 20130626 |