CN103872059A - P-type channel flash memory and manufacturing method thereof - Google Patents
P-type channel flash memory and manufacturing method thereof Download PDFInfo
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- CN103872059A CN103872059A CN201410110060.9A CN201410110060A CN103872059A CN 103872059 A CN103872059 A CN 103872059A CN 201410110060 A CN201410110060 A CN 201410110060A CN 103872059 A CN103872059 A CN 103872059A
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Abstract
The invention provides a manufacturing method of a P-type channel flash memory. The method includes the first step of forming an N trap through an ion implantation technology and depositing a tunneling oxidation layer, a first polycrystalline silicon floating grid structure and a silicon nitride layer, the second step of forming a shallow separating groove through a dry etching process, the third step of enabling the shallow separating groove to be filled with a silicon dioxide dielectric layer through a high aspect ratio process, the fourth step of removing part of the silicon dioxide dielectric layer through a wet etching process and depositing an ONO dielectric oxidation layer, the fifth step of depositing a second polycrystalline silicon control grid structure, the sixth step of forming control grid electrodes and floating grids through the dry etching process, and the seventh step of injecting different dose of P-type dopant into source electrode regions and drain electrode regions. According to the method, a self-aligning shallow groove separation process is adopted on the basis of the P-type channel flash memory, and the storage density of the P-type channel flash memory is increased; the higher floating grids are adopted to enhance the voltage coupling effect of the P-type channel flash memory, and consequently the high reading speed and low power consumption can be achieved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of P type raceway groove flush memory device and manufacture method thereof.
Background technology
The application of nonvolatile storage in semiconductor device (Non-volatile Memory, NVM) is very extensive, is characterized in still can preserving the data of storage after power-off.Nonvolatile storage is the earliest Erarable Programmable Read only Memory (Erasable Programmable Read Only Memory, EPROM), and its programming adopts hot electron to inject, and wipes and adopts UV ultraviolet light.But described Erarable Programmable Read only Memory need carry out UV ultraviolet light with quartz glass to be wiped, with high costs.
In order to reduce manufacturing cost, EEPROM (Electrically Erasable Programmable Read Only Memo) (the Electrically Erasable Programmable Read Only Memory that now utilizes FN tunneling effect to carry out electricity to wipe, EEPROM), when electronic injection and be stored in interval scale information " 0 " in floating boom; When electronics is wiped free of interval scale information " 1 " from floating boom.Apparently, described EEPROM (Electrically Erasable Programmable Read Only Memo) is low compared with erasable programmable memory cost, but the programming of described EEPROM (Electrically Erasable Programmable Read Only Memo) and wipe and need byte-by-byte (Byte) to carry out, and speed is too low.
In order to improve device reading speed, on the device architecture of described EEPROM (Electrically Erasable Programmable Read Only Memo), carry out circuit design improvement, and develop existing conventional flash memory (Flash EEPROM), make multiple memory cell (Cell) to programme simultaneously and to wipe.
Described existing flash memory is the same with EEPROM, and programming all adopts hot electron injection mode (Channel Hot Electron Injection, CHEI).In order to produce hot electron, conventionally require to apply high voltage at described grid and described drain electrode.Due to the physical characteristic of hot electron injection itself, its power consumption is large, and Carrier Injection Efficiency is low, seriously runs counter to, so defect is further highlighted with the demand of the low-power consumption in current market.On the other hand, in order to improve Carrier Injection Efficiency, those skilled in the art have proposed to utilize the source hot electron method for implanting (Source-side Channel Hot Electron, SSCHE) of grid dividing structure, and the 2T flash cell that utilizes FN tunnelling to programme.But described technology all adopts the flush memory device of N-type raceway groove.
P type channel flash memory is the earliest by Hsu., the propositions such as et al, described P type channel flash memory is different from described traditional N-type channel flash memory, described traditional N-type channel flash memory operation is in current saturation interval, and described P type channel flash memory is to be operated in reverse-biased district, therefore power consumption greatly declines.Described P type channel flash memory utilizes electron tunneling effect simultaneously, and reading speed is fast, has more and more important market application foreground now.
Apparently, hold intelligibly as those skilled in the art, in order to make technological knowledge popular and to meet the need of market, described P channel flash memory is improving storage density, improve the voltage coupling efficiency (Couple Ratio) of device, and the aspect such as faster devices reading speed need further raising.
Therefore the problem existing for prior art, this case designer relies on the industry experience for many years of being engaged in, and active research improvement, so had a kind of P type raceway groove flush memory device of the present invention and manufacture method thereof.
Summary of the invention
The present invention be directed in prior art, traditional P channel flash memory is improving storage density, improve the voltage coupling efficiency (Couple Ratio) of device, and the aspect such as faster devices reading speed need the defects such as further raising a kind of P type raceway groove flush memory device is provided.
The present invention's another object is in prior art, traditional P channel flash memory is improving storage density, improve the voltage coupling efficiency (Couple Ratio) of device, and the aspect such as faster devices reading speed need the defects such as further raising a kind of manufacture method of P type raceway groove flush memory device is provided.
In order to address the above problem, the invention provides a kind of P type raceway groove flush memory device, described P type raceway groove flush memory device comprises: N trap, described N trap is arranged on the P type silicon chip that crystal orientation is <110>; Floating boom, described floating boom and described N trap arrange by described tunneling oxide layer interval; P type doping source region and P p doped drain p district, described P type doping source region and P p doped drain p district are separately positioned on the both sides of described floating boom; Control grid, described control grid is disposed on described floating boom by described ONO dielectric oxide layer.
Alternatively, the thickness range of described tunneling oxide layer is 6～12nm, and the thickness of described floating boom is 60～120nm, and the thickness of described control grid is 150～250nm, and the thickness of the ONO dielectric oxide layer between described floating boom and described control grid is 10～20nm.
Alternatively, BF is injected in described source area
2, B is injected in described drain region.
For realizing the present invention's another object, the invention provides a kind of manufacture method of P type raceway groove flush memory device, described method comprises:
Execution step S1: form described N trap by ion implantation technology, and deposit successively and form described tunneling oxide layer, the first multi-crystal silicon floating bar structure and silicon nitride layer on described N trap;
Execution step S2: by dry etch process form described shallow trench isolation from;
Execution step S3: by described high-aspect-ratio technique (High Aspect Ratio Process, HARP) to described shallow trench isolation from carrying out the filling of silica dioxide medium layer;
Execution step S4: remove described silica dioxide medium layer by wet etching part, and deposit described ONO(Oxide-Nitride-Oxide) dielectric oxide layer;
Execution step S5: in the second polysilicon control grid structure described in an outgrowth that differs from described N trap of described the first multi-crystal silicon floating bar structure and described ONO dielectric oxide layer;
Execution step S6: by dry etch process, described the second polysilicon control grid structure is carried out to etching and form described control grid, described the first multi-crystal silicon floating bar structure is carried out to etching and form described floating boom;
Execution step S7: the P type doping of injecting respectively various dose in source area and the described drain region of described floating boom, to complete the manufacture of described P type raceway groove flush memory device.
Alternatively, described N trap adopts phosphonium ion to inject, and amounts to three roads and injects.
Alternatively, described tunneling oxide layer and described ONO(Oxide-Nitride-Oxide) dielectric oxide layer all adopts situ steam method of formation (In-Situ Steam Generation, ISSG) technique.
Alternatively, the partial etching amount of described silica dioxide medium layer to be to make voltage coupling efficiency inadequate because etching is very few, and the isolation effect that does not too much reduce device because of etching is limited.
Alternatively, BF is injected in described source area
2, B is injected in described drain region, after Implantation, anneals, and realizes ion and intensifies, to complete the manufacture of described P type raceway groove flush memory device.
In sum, the manufacture method of P type raceway groove flush memory device of the present invention adopts autoregistration shallow ditch groove separation process on the basis of described P type channel memory devices, not only increases device stores density, makes its memory cell area be about 2F
2, and by adopting higher floating boom (60～120nm), strengthened greatly the voltage coupling effect of device, so realize that voltage coupling efficiency is high, reading speed is fast, low in energy consumption, and effect such as storage density is large.
Accompanying drawing explanation
Figure 1 shows that the flow chart of the manufacture method of P type raceway groove flush memory device of the present invention;
Figure 2 shows that the electronic scanning collection of illustrative plates of P type raceway groove flush memory device of the present invention;
Fig. 3 (a)～3(g) be depicted as the interim structural representation of the manufacture of P type raceway groove flush memory device of the present invention.
Embodiment
By describe in detail the invention technology contents, structural feature, reached object and effect, below in conjunction with embodiment and coordinate accompanying drawing to be described in detail.
Refer to Fig. 1, Figure 1 shows that the flow chart of the manufacture method of P type raceway groove flush memory device of the present invention.The manufacture method of described P type raceway groove flush memory device comprises the following steps,
Execution step S1: form described N trap by ion implantation technology, and deposit successively and form described tunneling oxide layer, the first multi-crystal silicon floating bar structure and silicon nitride layer on described N trap;
Execution step S2: by dry etch process form described shallow trench isolation from;
Execution step S3: by described high-aspect-ratio technique (High Aspect Ratio Process, HARP) to described shallow trench isolation from carrying out the filling of silica dioxide medium layer;
Execution step S4: remove described silica dioxide medium layer by wet etching part, and deposit described ONO(Oxide-Nitride-Oxide) dielectric oxide layer;
Execution step S5: in the second polysilicon control grid structure described in an outgrowth that differs from described N trap of described the first multi-crystal silicon floating bar structure and described ONO dielectric oxide layer;
Execution step S6: by dry etch process, described the second polysilicon control grid structure is carried out to etching and form described control grid, described the first multi-crystal silicon floating bar structure is carried out to etching and form described floating boom;
Execution step S7: the P type doping of injecting respectively various dose in source area and the described drain region of described floating boom, to complete the manufacture of described P type raceway groove flush memory device.
For disclosing more intuitively the present invention's technical scheme, highlight the present invention's beneficial effect, now set forth in conjunction with concrete execution mode, in embodiment, related concrete material composition, thickness range are only for enumerating, the material that the equal effect such as can obtain also belongs to the scope that the present invention advocates, should not be considered as the restriction to the technical program.
Refer to Fig. 2, Fig. 3 (a)～3(g), Figure 2 shows that the electronic scanning collection of illustrative plates of P type raceway groove flush memory device of the present invention.Fig. 3 (a)～3(g) be depicted as the interim structural representation of the manufacture of P type raceway groove flush memory device of the present invention.Described P type raceway groove flush memory device 1 comprises: N trap 11; Floating boom 121, described floating boom 121 arranges by described tunneling oxide layer 13 intervals with described N trap 11; P type doping source region 122 and P p doped drain p district 123, described P type doping source region 122 and P p doped drain p district 123 are separately positioned on the both sides of described floating boom 121; Control grid 141, described control grid 141 is disposed on described floating boom 121 by described ONO dielectric oxide layer 15.
The manufacture method of P type raceway groove flush memory device 1 of the present invention, comprises the following steps:
Execution step S1: form described N trap 11 by ion implantation technology, and deposit successively and form described tunneling oxide layer 13, the first multi-crystal silicon floating bar structure 12 and silicon nitride layer 16 on described N trap 11;
Without limitation, adopt in the present invention P type substrate, the silicon chip that crystal orientation is <110> carries out subsequent technique flow process.In described step S1, described N trap 11 adopts phosphonium ion to inject, and amounts to three roads and injects, and in order to carry out device threshold voltage adjusting and device isolation, prevents electric leakage; As execution mode particularly, the thickness of described tunneling oxide layer 13 is 6～12nm; The thickness of described the first multi-crystal silicon floating bar structure 12 is 60～120nm.Described tunneling oxide layer 13 adopts situ steam method of formation (In-Situ Steam Generation, ISSG) technique, in order to improve film quality, improves the reliability of flush memory device.
Execution step S2: form described shallow trench isolation from 17 by dry etch process;
More specifically, etching form described shallow trench isolation from 17 in, further active area 10, tunneling oxide layer 13, the first multi-crystal silicon floating bar structure 12 and silicon nitride layer 16 described in etching, and guarantee described pattern after etching and the described shallow trench isolation degree of depth from 17.
Execution step S3: by described high-aspect-ratio technique (High Aspect Ratio Process, HARP), described shallow trench isolation is carried out to silica dioxide medium layer 18 from 17 and fill;
Execution step S4: remove described silica dioxide medium layer 18 by wet etching part, and deposit described ONO(Oxide-Nitride-Oxide) dielectric oxide layer 15;
More preferably, the partial etching amount of described silica dioxide medium layer 18 is optimized, not make voltage coupling efficiency inadequate because etching is very few, the isolation effect that does not too much reduce device because of etching is advisable.Described ONO dielectric oxide layer 15 adopts situ steam method of formation (In-Situ Steam Generation, ISSG) technique, in order to improve film quality, improves the reliability of flush memory device.
Execution step S5: in the second polysilicon control grid structure 14 described in an outgrowth that differs from described N trap 11 of described the first multi-crystal silicon floating bar structure 12 and described ONO dielectric oxide layer 15;
Wherein, the thickness of the ONO dielectric oxide layer 15 between described the second polysilicon control grid structure 14 and described the first multi-crystal silicon floating bar structure 12 is 10～20nm.
Execution step S6: by dry etch process, described the second polysilicon control grid structure 14 is carried out to etching and form described control grid 141, described the first multi-crystal silicon floating bar structure 12 is carried out to etching and form described floating boom 121;
More specifically, the thickness of described floating boom 121 is 60～120nm; The thickness of described control grid 141 is 150～250nm; The thickness of the ONO dielectric oxide layer 15 between described floating boom 121 and described control grid 141 is 10～20nm.
Execution step S7: the P type doping of injecting respectively various dose in source area 122 and the described drain region 123 of described floating boom 121, to complete the manufacture of described P type raceway groove flush memory device 1.
More specifically, inject BF in described source area 122
2, inject B in described drain region, after Implantation, anneal, realize ion and intensify, to complete the manufacture of described P type raceway groove flush memory device 1.
As those skilled in the art, hold intelligibly, the manufacture method of P type raceway groove flush memory device of the present invention adopts autoregistration shallow ditch groove separation process on the basis of described P type channel memory devices, not only increases device stores density, makes its memory cell area be about 2F
2, and by adopting higher floating boom (60～120nm), strengthened greatly the voltage coupling effect of device, so realize that voltage coupling efficiency is high, reading speed is fast, low in energy consumption, and effect such as storage density is large.
In sum, the manufacture method of P type raceway groove flush memory device of the present invention adopts autoregistration shallow ditch groove separation process on the basis of described P type channel memory devices, not only increases device stores density, makes its memory cell area be about 2F
2, and by adopting higher floating boom (60～120nm), strengthened greatly the voltage coupling effect of device, so realize that voltage coupling efficiency is high, reading speed is fast, low in energy consumption, and effect such as storage density is large.
Those skilled in the art all should be appreciated that, in the situation that not departing from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any modification or modification fall in the protection range of appended claims and equivalent, think that the present invention contains these modifications and modification.
Claims (8)
1. a P type raceway groove flush memory device, is characterized in that, described P type raceway groove flush memory device comprises:
N trap, described N trap is arranged on the P type silicon chip that crystal orientation is <110>;
Floating boom, described floating boom and described N trap arrange by described tunneling oxide layer interval;
P type doping source region and P p doped drain p district, described P type doping source region and P p doped drain p district are separately positioned on the both sides of described floating boom;
Control grid, described control grid is disposed on described floating boom by described ONO dielectric oxide layer.
2. P type raceway groove flush memory device as claimed in claim 1, it is characterized in that, the thickness range of described tunneling oxide layer is 6～12nm, the thickness of described floating boom is 60～90nm, the thickness of described control grid is 150～250nm, and the thickness of the ONO dielectric oxide layer between described floating boom and described control grid is 10～20nm.
3. P type raceway groove flush memory device as claimed in claim 1, is characterized in that, BF is injected in described source area
2, B is injected in described drain region.
4. a manufacture method for P type raceway groove flush memory device as claimed in claim 1, is characterized in that, described method comprises:
Execution step S1: form described N trap by ion implantation technology, and deposit successively and form described tunneling oxide layer, the first multi-crystal silicon floating bar structure and silicon nitride layer on described N trap;
Execution step S2: by dry etch process form described shallow trench isolation from;
Execution step S3: by described high-aspect-ratio technique (High Aspect Ratio Process, HARP) to described shallow trench isolation from carrying out the filling of silica dioxide medium layer;
Execution step S4: remove described silica dioxide medium layer by wet etching part, and deposit described ONO(Oxide-Nitride-Oxide) dielectric oxide layer;
Execution step S5: in the second polysilicon control grid structure described in an outgrowth that differs from described N trap of described the first multi-crystal silicon floating bar structure and described ONO dielectric oxide layer;
Execution step S6: by dry etch process, described the second polysilicon control grid structure is carried out to etching and form described control grid, described the first multi-crystal silicon floating bar structure is carried out to etching and form described floating boom;
Execution step S7: the P type doping of injecting respectively various dose in source area and the described drain region of described floating boom, to complete the manufacture of described P type raceway groove flush memory device.
5. the manufacture method of P type raceway groove flush memory device as claimed in claim 4, is characterized in that, described N trap adopts phosphonium ion to inject, and amounts to three roads and injects.
6. the manufacture method of P type raceway groove flush memory device as claimed in claim 4, it is characterized in that, described tunneling oxide layer and described ONO(Oxide-Nitride-Oxide) dielectric oxide layer all adopts situ steam method of formation (In-Situ Steam Generation, ISSG) technique.
7. the manufacture method of P type raceway groove flush memory device as claimed in claim 4, is characterized in that, the partial etching amount of described silica dioxide medium layer to be to make voltage coupling efficiency inadequate because etching is very few, and the isolation effect that does not too much reduce device because of etching is limited.
8. the manufacture method of P type raceway groove flush memory device as claimed in claim 4, is characterized in that, BF is injected in described source area
2, B is injected in described drain region, after Implantation, anneals, and realizes ion and intensifies, to complete the manufacture of described P type raceway groove flush memory device.
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| CN104733433A (en) * | 2015-03-24 | 2015-06-24 | 上海新储集成电路有限公司 | Structure and method achieving partial interconnection |
| CN109904069A (en) * | 2019-03-20 | 2019-06-18 | 上海华虹宏力半导体制造有限公司 | The forming method of ono dielectric layer |
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